2.2 Implementation of Transformer-Based Integrated Passive Devices

.PDFDevices and Dual-Band Bandpass Filters for
Wireless Applications

Chien-Hsiang Huang
October 2011
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Acknowledgments
At first, I want to express the deep gratitude to the enthusiastic guidance of my adviser, Dr. Tzyy-Sheng Horng. He taught me how to research intensively and inspirited me to overcome problems. Without his assistance, this dissertation is difficult to be accomplished. In addition, He also shows me how to become a true researcher and sets a good example with his own conduct. I would like to thank Dr. Kin-Lu Wong, Dr. Chih-Wen Kuo, Dr. Ken-Huang Lin, Dr. Lih-Tyng Hwang, Dr. Chie-In Lee, Dr. Sung-Mao Wu, and Dr. Jian-Ming Wu, suggested many valuable comments in this dissertation. I also owe many thanks to the people at RF & microwave laboratory that I have the pleasure to work with: Chien-Yuan Pan, Cheng-Yu Ho, Chien-Hsun Chen, Tzu-Chiang Wei and Yong-Jun Chen. I would not be able to complete this project without their great help. My labmates, Yi-Chieh Lin and Kuan-Chung Lu help me deal with my research projects and I had really enjoyed company during my Ph. D student life. Finally, I deeply appreciate the strong encouragement, patience to thank my parents, Mr. Hsiu-Hsiung Huang and Mrs. Kuei-Mei Hsieh, for their love, and vast support through these years. Special thank to my wife, Kao-Wei Yu, and my son, Yi-Hsun Huang, for their spiritual support and endless love. Only dedicate this dissertation to them.
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Abstract
This dissertation aims to design and implement wireless passive components
using domestic integrated passive device (IPD) technology. The research focuses on
exploiting novel 3-D structures for various kinds of IPD-based wireless passive
components including high-quality and high-efficiency planar transformers, baluns,
filters, and combiners to achieve miniature size and high performance. A physical
model has been developed for modeling the planar transformers. In this dissertation, a
scalable transformer model in integrated passive device technology is further used to
correlate with the coupled-line sections of a conventional Marchand balun. This
improves the efficiency of the design of planar transformers with equivalent
coupled-line parameters such as the coupling factor, and even- and odd-mode
characteristic impedances and quality factors. Additionally, the proposed model-based
design approach provides effective optimization techniques that incorporate
geometrical and material parameters. In addition, a compact transformer-based
coupled balun bandpass filter design is proposed based on integrated circuit
technology and the equivalent circuit is established. Using a planar transformer with
high-density fully symmetrical wiring not only greatly reduces the component size but
also provides a superior stopband rejection and selectivity. Finally, by using the
spiral-shaped resonators, the dual-band third-order bandpass filter has been
implemented on organic substrates. The proposed BPF design is verified to overcome
the elements’ parasitic effects, and thus can be miniaturized and optimized with high
degree of freedom. The simulation and measurement results have good agreement for
the proposed design in this dissertation.
Keywords : Integrated Passive Device, Planar Transformer, Dual-Band Bandpass Filter, Equivalent Circuit, Modeling
vi
1.2.2 Technology Realization of IPDs ............................................................3
1.3 Overview of Dissertation...............................................................................7
Passive Devices for Wireless Applications 10
2.1 Planar Transformer Winding and Physical Modeling .................................11
2.2 Implementation of Transformer-Based Integrated Passive Devices ...........20
2.2.1 Planar Transformer-based Balun ..........................................................20
3 Optimum Design of Transformer-Type Marchand Balun Using Scalable
Integrated Passive Device Technology 37
3.1 Planar Transformer-Type Marchand Balun Design.....................................38
3.1.1 IPD Balun Structure .............................................................................38
3.1.2 Marchand Balun Design with a Symmetric Transformer Model .........40
3.1.3 Transformer Model with Scalability ....................................................47
3.2 Design Optimization and Results ................................................................49
3.2.1 Marchand Balun in Silicon IPD Technology .......................................52
3.2.2 Marchand Balun in Glass IPD Technology..........................................57
vii
4 Design and Analysis of Compact Bandpass Filter Using Transformer-Based
Coupled Resonators on Integrated Passive Device Glass Substrate 63
4.1 Filter Design Approach and Transmission Zero Analysis ...........................65
4.1.1 Design of Transformer-based Coupled Resonator Bandpass Filter .....65
4.1.2 Transmission-Zero Analysis of Filter...................................................68
Spiral-Shaped Resonators 81
5.1.3 Transmission Zeros ..............................................................................87
viii
List of Figures 1.1. Schematic description of the different wafer-level IPD types and combinations.
(a) Wire bond with wire bond (b) Wire bond with flip chip (c) Flip chip with flip chip.. ............................................................................................................3
1.2. Cross-sectional view of thin-film integrated passive devices structure.............4 1.3. Simple process flow for the fabrication of wafer-level IPD.. ............................7 2.1 Integrated passive device cross section with physical parasitic effects
illustrated in the inset. ......................................................................................12 2.2 Integrated passive device cross section with physical geometric parameters
illustrated in the inset.. .....................................................................................12 2.3 On-chip transformer. (a) Chip photo of symmetrical 2:2 transformer (b)
S-parameter of the planar 2:2 bifilar on-chip transformer. ..............................17 2.5 Comparison among modeled, EM simulated and measured results of : (a) self
inductance and (b) coupling coefficient for the planar 2:2 bifilar on-chip transformer. ......................................................................................................18
2.6 Comparison among modeled, EM simulated and measured results of (a) quality factor and (b) passive efficiency for the planar 2:2 bifilar on-chip transformer. ......................................................................................................19
2.7 (a) A silicon balun using a planar 2:2 bifilar transformer and (b) its simplified circuit schematic. .............................................................................................20
2.8 Comparisons of modeled and measured S-parameters of the bifilar 2:2 transformer-based balun : (a) magnitude of S21, (b) phase of S21, (c) magnitude of S31, (d) phase of S31......................................................................................23
2.9 Modeled, EM simulated, and measured results of (a) amplitude and (b) phase imbalance of the implemented bifilar 2:2 transformer-based balun. .....24
ix
2.11 (a) A silicon bandpass filter using a planar 1.5:1.5 bifilar transformer and (b) its simplified circuit schematic. .......................................................................27
2.12 Modeled, EM simulated and measured results of the silicon bandpass filter. (a) |S11| in decibels. (b) |S21| in decibels.. ...............................................................28
2.13 (a) A silicon power combiner using a 1:1:2 SCT of octagonal shape and (b) its simplified circuit schematic.. ...........................................................................30
2.14 (a) A silicon power combiner using a 1:1:2 PCT of hexagonal shape and (b) its simplified circuit schematic.. ...........................................................................31
2.15 Modeled, EM simulated and measured results of the 1:1:2 SCT power combiner: (a) Magnitude of S12 (b) Phase of S12..............................................32
2.16 Modeled, EM simulated and measured results of the 1:1:2 SCT power combiner: (a) Magnitude imbalance (b) Phase imbalance...............................33
2.17 Modeled, EM simulated and measured results of the 1:1:2 PCT power combiner: (a) Magnitude of S12 (b) Phase of S12..............................................34
2.18 Modeled, EM simulated and measured results of the 1:1:2 PCT power combiner: (a) Magnitude imbalance (b) Phase imbalance...............................35
2.19 Modeled, EM simulated and measured results of DMRR and DL for the silicon power combiners. (a) SCT-type (b) PCT-type......................................36
3.1. Cross-sectional view of IPDs with interconnect line, resistor, inductor and
capacitor...........................................................................................................40
3.2. Layout of Marchand balun using two planar transformers..............................40
3.3. Block diagram of an ideal Marchand balun with two identical λ/4 coupled-line
sections.............................................................................................................41
3.4. Equivalent circuit of a symmetric transformer.................................................41
3.5. Even-mode circuit of (a) a coupled-line section and (b) a symmetric
transformer. ......................................................................................................42
3.6. Odd-mode circuit of (a) a coupled-line section and (b) a symmetric
transformer. ......................................................................................................43
3.7. Chip photographs of Marchand baluns fabricated by (a) silicon IPD and (b)
glass IPD technologies.....................................................................................51
3.8. Comparisons of modeled and measured S-parameters of the Marchand balun
in silicon IPD technology: (a) magnitude of S11, (b) phase of S11, (c) magnitude
of S21, (d) phase of S21, (e) magnitude of S31, and (f) phase of S31...................55
x
3.9. Modeled and measured results of the Marchand balun in silicon IPD
technology: (a) CMRR and (b) insertion loss. .................................................56
3.10. Comparisons of modeled and measured S-parameters of the Marchand balun
in glass IPD technology: (a) magnitude of S11, (b) phase of S11, (c) magnitude
of S21, (d) phase of S21, (e) magnitude of S31, and (f) phase of S31...................60
3.11. Modeled and measured results of the Marchand balun in glass IPD technology:
(a) CMRR and (b) insertion loss......................................................................61
4.1 Cross-sectional view of thin-film glass-based substrate integrated passive
devices structure containing three passive components...................................65 4.2 Design flow of the bandpass filter using coupled resonators technique..........66 4.3 (a) Conventional coupled resonator circuit with magnetic coupling. (b)
Modified coupled resonator circuit with magnetic coupling. ..........................66 4.4 Configuration of proposed transformer-coupled bandpass filter: (a) Type-A (b)
Type-B..............................................................................................................67 4.5 Equivalent circuits of the transformer-based coupled bandpass filter: (a)
4.7 Equivalent-circuit models for the type-B filter using the proposed transformer-based coupled resonators. (a) Even-mode model. (b) Odd-mode model................................................................................................................70
4.8 Equivalent-circuit modeled results of the BPF. (a) Type-A filter (b) Type-B filter.. ................................................................................................................73
4.9 (a) Simulated responses of the filter circuit model of the type-A BPF for various values of Cc1 and (b) curves to relate the transmission-zero frequencies to the values of Cc1...........................................................................................74
4.10 (a) Simulated responses of the filter circuit model of the type-B BPF for various values of Cc2 and (b) curves to relate the transmission-zero frequencies to the values of Cc2...........................................................................................75
4.11 Measured and simulated results of the proposed transformer-based coupled BPFs: (a) type-A and (b) type-B. .....................................................................78
4.12 Comparison of the measured and simulated group delay for the transformer-based coupled BPFs: (a) type-A and (b) type-B. .........................79
4.13 Photograph of the fabricated BPFs implemented on integrated passive device glass substrate: (a) type-A and (b) type-B........................................................80
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5.2 Simulated S11 phase responses of different half-wavelength microstrip resonators. ........................................................................................................84
5.3 Layout geometry of the proposed dual-band bandpass filter. ..........................86 5.4 Coupling coefficient versus the spacing between two adjacent spiral-shaped
microstrip resonators........................................................................................86 5.5 External quality factor versus the tapped position of a single spiral-shaped
Magnitude of S21 (b) Magnitude of S11. ...........................................................90 5.8 Measured and simulated results of the proposed bandpass filter near (a) 1st
passband of 2.45 GHz and (b) 2nd passband of 5.2 GHz. ................................91 5.9 Comparison of the measured and simulated group delay for the proposed BPF:
(a) 1st passband of 2.45 GHz and (b) 2nd passband of 5.2 GHz. ......................92 5.10 Simulated current density of the proposed BPF at the frequency of: (a) 2.45
GHz and (b) 5.2 GHz. ......................................................................................93 5.11 Photograph of the designed dual-band bandpass filter implemented on a
RT/Duroid 6010 substrate. ...............................................................................94
List of Tables
3.1 Summary of Even- and Odd-Mode Parameters and Balun Performance at
Different Widths and Spacing of a Transformer in Silicon-Based IPD
Technology....................................................................................................50
3.2 Summary of Even- and Odd-Mode Parameters and Balun Performance at
Different Widths and Spacing of a Transformer in Glass-Based IPD
Technology....................................................................................................50
IPD Technology ............................................................................................62
5.1 Comparisons of Performances of Dual-Band Bandpass Filter with Other
Designs..........................................................................................................94
1
Chapter 1 Introduction
1.1 Research Motivation
With the rapid growth of wireless communication markets, silicon is recognized as
an especially promising material to meet the demands of low cost, high integration for
RF passive components [1]-[4]. Conventional discrete passive components consume
60%-70% of the footprint area of the system. These components are typically made
using ceramic technology [5]-[6], because of ceramic’s good electrical and thermal
characteristics. However, integrated passives devices (IPDs) based on semiconductor
processes offer the advantage of excellent parameter control, and allow simplified and
compact module designs.
A key requirement is the fabrication of high-Q inductors for passive components.
Typically, silicon substrates have higher substrate losses than GaAs or ceramic
materials [7]-[8]. In order to overcome this difficulty, various approaches have been
tried. In the early development of high-Q inductors and transformers on silicon
substrates, good results have been reported using high resistivity silicon wafer
[9]-[10]. Owing to the fact that IPDs are generally fabricated using standard wafer
fabrication technologies such as thin film and photo-lithography processing, they can
be manufactured with low cost and small size with excellent reproducibility [11]-[12].
IPD processes can be used to make high density capacitors, high-Q inductors and
large value resistors [13]-[15].
lPDs can be applied to existing fields of applications that use whole passive
CHAPTER 1. INTRODUCTION 2
devices, and have already been applied to the front-end modules (FEMs) of mobile
systems [16]-[17]. To meet a variety of requirements on RF modules such as technical
performance, size, and cost considerations, two major design concepts system-in-
package (SiP) and system-on-package (SoP) were introduced recently. IPD
technology not only offers compatibility with the existing active devices but also
ensures the compatibility of semiconductor processes, making it an essential
technology for SiP and SoP developments that are expected to be the key
next-generation system implementation approaches [18]. In wireless communication
systems, many functional blocks, such as baluns, low pass filters (LPFs), power
divider/combiner and bandpass filters (BPFs), were realized by IPD technology
[19]-[22].
1.2.1 IPDs Concept on Wafer Level Package
Three common 3-D module structures are shown in Figure 1.1 [22]. Active RFICs
are electrically connected to the silicon or glass substrate by either flip-chip solder
bumps or by wire bonds. In order to increase the package density, it is possible to
combine these basic wafer-level IPD types to form stacks of them. Wafer-level IPDs
can be designed as flip chip mountable as well as wire bondable components by using
different thin film substrates like silicon, glass or alumina.
The option to combine flip chip mountable and wire bondable wafer-level IPDs is
given in Figure 1.1(b). Figure 1.1(c) shows the example of getting a lower profile by
using thinned wafer-level IPDs. The large solder balls of the carrier, which is RFIC,
deliver enough standoff height for IPD to be located underneath the carrier during its
assembly to the board. Besides the different options of stacking it is also possible to
combine the wafer-level IPDs with integrated circuits to form a true system in
package. The large variety of different possibilities emphasizes the flexibility and the
high potential of the technology.
RFIC
(c)
Figure 1.1 Schematic description of the different wafer-level IPD types and
combinations. (a) Wire bond with wire bond (b) Wire bond with flip chip (c) Flip chip
with flip chip.
1.2.2 Technology Realization of IPDs
In Figure 1.2, a cross-section of the thin film multilayer buildup used in this work
is shown. The different sputtered metal layers are separated by thin spun-on layers of
photo-sensitive benzocylcobutene (BCB) dielectric (εr = 2.65 and tan δ = 8·10-4)
stacked on a low loss borosilicate based glass carrier substrate (εr = 6.2 and tan δ =
9·10-4). Immediately on the carrier substrate, TaN resistors and Ta2O5 capacitors (εr =
25) may be realized. These resistors and capacitors are contacted with an aluminum
metallization, while the further interconnections and the spiral inductors are made
using the other high conductivity copper layers. Vias with a minimum diameter of 20
μm are used to connect the different metal layers. The top copper layer is coated with
NiAu in order to allow easy mounting of other active devices (flip-chip,
wire-bonding).
The process flow given in Figure 1.3 allows the wafer level fabrication of IPDs
with planar coils, metal–insulator–metal (MIM) capacitors, resistors, solder
stop/passivation layer, and pad metallization [23]-[24]. Only when all of the three
passive types have to be realized in one wafer-level IPD, the whole process chain has
to be worked through.
TaN Ta2O5
Figure 1.2 Cross-sectional view of thin-film integrated passive devices structure.
First of all, a 5-μm-thick polymer planarization layer of Benzocyclobutene is
realized by spin coating of the photosensitive. Next, the BCB is fully exposed except
the areas of the future dicing streets. After development the BCB is cured in an oven
under nitrogen atmosphere in Figure 1.3(a). This first layer is only a planarization
layer, which is necessary when very rough substrates like ceramics are used.
In the next step, a nickel/chromium layer is deposited by direct current
(DC)-sputtering a target consisting of Ni and Cr. To define the resistor structures, this
layer is masked by the photo resist. In a further step, the masked layer is structured by
wet chemical etching creating the resistor structures, as shown in Figure 1.3(b). Then
the resist is removed by wet stripping, followed by a short oxygen plasma treatment in
a reactive ion etcher.
Next a titanium/tungsten (Ti:W) adhesion layer followed by a copper seed layer
are deposited by DC-sputtering. Then the copper is masked by photo resist to define
the structures of the first metal layer. Now the metal structures are formed by
electroplating of copper into the resist mask openings. After the deposition process the
resist mask is stripped and differential etching steps of the copper as well as the Ti:W
layers are done. Finally, a short dry etch step in plasma is performed to remove the
upper layer of the BCB, which was interspersed with Ti:W during sputtering in Figure
1.3(c).
Now the interlayer polymer has to be realized. For this purpose, a spin coating
process using the same BCB formulation as for the planarization layer is applied.
Next the prepolymer is exposed and developed using puddle development to define
the via holes connecting the first with the following metal layer. After polymer curing,
a dry etch step has to be carried out in plasma. This plasma treatment removes BCB
residues that have remained in the vias after development.
For the realization of the second metal layer, the same process steps as for the first
one are carried out, including sputtering of adhesion and seed layers, realization of
resist mask, electroplating of metal structures, as well as resist removing and
differential etching in Figure 1.3(d) followed by BCB spin on and BCB development.
Finally, the pad metallization has to be realized. Therefore, adhesion and seed
layers are sputtered, followed by the spin coating of resist and photolithographic
definition of the plating mask. In the following step, nickel is deposited into the resist
mask openings by electroplating, as shown in Figure 1.3(e). After resist stripping and
differential etching an electro-less gold deposition is done to protect the nickel pads
from oxidization in Figure 1.3(f). The created metal pads can either serve as pads for
wire bonding or under bump metallization for a subsequent bumping process like
stencil printing or placing of preformed solder balls. After dicing, the wafer level IPDs
are ready for assembly.
(e)
(f)
S u b s t r a t e B C B C u
N i C r T i : W
N i A u
Figure 1.3 Simple process flow for the fabrication of wafer-level IPD.
1.3 Overview of Dissertation
This dissertation is organized into six chapters. Chapter 1 is the introduction. The
contents of the other chapters are summarized as follows.
Chapter 2 presents design and modeling techniques for integrated passive devices
that can be stacked with RF chips in a highly integrated three dimensional IC for
wireless applications. The research starts to study winding and modeling techniques
for high-efficiency planar transformers. In an Above-IC process for silicon IPDs, the
planar transformers realized can provide a passive efficiency as high as near 90%.
Based upon the proposed and modeled high-efficiency planar transformers, the
research explores novel planar transformer-based structures for various kinds of
wireless passive components including baluns, bandpass filters and power combiners
to achieve miniature size as well as high performance.
Chapter 3 presents a simple and effective technique for designing spiral-type
Marchand baluns. The symmetric lossy coupled transmission lines are modeled based
on compatible spiral transformer lumped-equivalent circuits. This technique was
adopted to design Marchand baluns and the results were confirmed to be in agreement
with measured results having a wide range of layout and process parameters. The
scalable transformer-based model enables the prediction and optimization of
Marchand balun performance. To validate the analytical results and demonstrate the
design approach, Marchand baluns were designed for implementation on integrated
passive device (IPD) process technology, including both silicon-based and glass-based
substrates. In this chapter, integrated spiral-type Marchand baluns for wireless
applications are presented and shown to exhibit excellent measured performances
with an insertion loss of 1 dB, amplitude imbalance of 0.45 dB, phase imbalance of 3
degree, and common-mode rejection ratio of 30 dB at designed 2.45 GHz. Finally, an
experimental verification showed very good agreement between the modeled and
measured results, thereby validating the IPD design process.
Chapter 4 presents a transformer-based coupled resonator structure to design a
bandpass filter (BPF) using integrated passive device technology on glass substrate.
The use of the transformer not only greatly reduces the size of the bandpass filter, but
also easily employs the coupling to control the bandwidth of the filter. Using such a
transformer-based coupled BPF structure not only provides the advantage of compact
size, but also creates extra transmission zeros to enhance roll-off rate or desired
stopband rejection. Measured results verify the validity of this design methodology
and show good agreement with simulated ones. For demonstration purpose, two
example filters are implemented with different bandwidths. Both good performance
and miniaturization are achieved for the proposed filters, and the expected
transmission zeros are also observed. The fabricated filter is more promising for low
cost wireless and RF applications, since it has miniaturized size and can be directly
integrated to wafer level system-in-packaging technology.
Chapter 5 demonstrates a new and simple dual-band bandpass filter design
configuration. It consists of spiral-shaped microstrip resonators. The filter is designed
to achieve the 2.4 GHz and 5.2 GHz dual-band operations for WLAN applications.
Meanwhile, a skew-symmetric tapped feed structure is applied to introduce two
transmission zeros on both sides of individual passbands, and thereby improve the
filter selectivity. The measured results of the designed third-order dual-band bandpass
filter for 2.4/5.2 GHz wireless local area network applications are in good agreement
with the simulated predictions. Moreover, the filter has a size reduction of 40%, as
compared with the conventional square open-loop bandpass filters.
Chapter 6 draws the conclusions
10
Chapter 2 Design and Modeling of Planar Transformer-Based Silicon Integrated Passive Devices for Wireless Applications
This chapter describes IPDs that are built using thin-film process technology on a
silicon wafer substrate. The IPD consists of three layers of metal with an inter-metal
polyimide dielectric. The bottom metal layer of aluminum is used exclusively for the
bottom electrodes of capacitors. This research demonstrates a scalable broadband
equivalent lump element circuit model for transformers fabricated on a conductive
silicon substrate. The scalable model components can be calculated using analytical
expressions incorporating skin effect and substrate loss that use geometrics and
process technological data. Based upon a scalable physical parameterized layout, we
can further try to optimize and simulate quickly the transformers with the geometry
that best suits the needs of the circuit applications, such as transformer-based balun,
bandpass filter, and power combiner. This study validates good agreement between
modeled and measured results. Therefore, this work presents a novel approach to
design on-chip balun, the proposed bandpass filter, and power combiner using
transformers. Finally, the current work presents transformer-based balun, bandpass
filter and power combiner designs using silicon-based IPD technology. The IPDs in
this chapter demonstrates are simulated using the full-wave EM simulator ANSYS
Ansoft HFSS. Comparing the simulations with measurements shows good agreement.
CHAPTER 2. DESIGN AND MODELING OF TRANSFORMER-BASED SILICON INTEGRATED PASSIVE DEVICES FOR WIRELESS APPLICATIONS
11
Conventional winding approaches for planar transformers include parallel winding,
interwound winding, overlay winding, and concentric spiral winding [25]. The planar
transformers using these winding approaches are usually not symmetrical and have
difficulties in applications to balanced RF components. Symmetrical bifilar and trifilar
transformers can solve the asymmetry problem and have been applied to balun
components [26]. However, they are typically of square shape and difficult to achieve
an arbitrary winding turn ratio while maintaining a good symmetry property. In this
research, new winding layout principles for symmetrical bifilar and trifilar
transformers with an arbitrary winding turn ratio are developed. The transformer
shape is not limited to a square, but may take diverse shapes such as a hexagon and an
octagon. Special care is also taken for designing transformers common-ground
network which is crucial to the self-resonant frequency and balanced parameters.
Figures 2.1 and 2.2 depicted cross section of integrated passive device with physical
parasitic effects and physical geometric parameters, respectively. Figure 2.1 illustrated
the resistive, inductive, and capacitive effects for the corresponding physical layout
mechanism. Figure 2.2 shows the physical geometric parameters of integrated
passive device including the material parameters of the conductor and substrate.
Figure 2.3(a) illustrates the layout of a symmetrical 2:2 transformer and the two
parallel coils in this structure are symmetrically inter-wound side-by-side using the
same metal layer. Figure 2.3(b) shows the simplified schematic circuit of a
transformer. The transformer is primarily designed to couple alternating current from
one winding to the other without signal power loss. Impedance levels between the
windings can be transformed as the ratio of terminal voltage to current flow changes
across windings. The transformer isolates the direct current flow between input port
and output port and the windings can be biased at different voltages. Figure 2.3(c)
shows the compact model for a transformer with four independently driven ports. The
primary and secondary inductances in the transformer are modeled by ideal
inductances Lp and Ls, respectively. The ohmic losses dissipated in the conductors are
represented by the series resistances Rp and Rs. The capacitor Cps is adopted to
describe the mutual coupling behavior between two inter-winding coils. This research
uses Cp and Cs to describe the parasitic coupling effect between segments on the
winding metals. Cpo1 to Cpo2 describe the parasitic capacitive effects into the
12
inter-metal dielectric of polymer between transformer and silicon substrate. Csub1 to
Csub2 and Rsub1 to Rsub2 represent the substrate capacitances and substrate loss,
respectively.
LpRp
Cpo
Cp
Figure 2.1 Integrated passive device cross section with physical parasitic effects illustrated in the inset.
Polyimide
Silicon
Figure 2.2 Integrated passive device cross section with physical geometric parameters illustrated in the inset.
13
(c)
Figure 2.3 On-chip transformer (a) Chip photo of symmetrical 2:2 transformer (b) Simple schematic circuit (c) Equivalent circuit.
In the proposed model shown in Figure 2.3(c), the self inductances of the primary
and secondary port of the symmetrical transformer can be calculated using the
empirical formula [27]
w t l + = + + +
(2.1)
where l, w and t denotes the length, width and thickness in centimeter of coil
conductor strip. The mutual inductance M in Figure 2.3(c) can be given by
( )2 nHM lQ= (2.2)
l l GMD GMDQ GMD GMD l l
= + + − + + (2.3)
14
2 4 4 8 10 ln ln
12 60 168 306 660 w w w w wGMD d d d d d d
≈ − − − − − (2.4)
where GMD is the geometric mean distance of the variable metal width estimated
using the Grover calculations [28] and d is the distance between the centers of the two
strips in the transformer. The estimate for Rp and Rs related to a planar transformer can
be obtained from the following equation, which extends with the frequency dependent
skin effect [29]:
= Ω ⋅ ⋅ −
(2.5)
where σc is the conductivity of the strip. δc is skin depth and μ is the permeability of
the material. The self and mutual capacitances are calculated using the following
equations [30]-[31]:
v C N w
ε= −
(2.7)
( )1,2 1 F 2sub subC lwC= (2.9)
where εpo is the permittivity. tpo(M1-M2) is the distance of underpass. tpo is the distance
between the substrate and bottom metal. Csub is the substrate capacitance per unit area.
Rsub1 to Rsub4 can be determined by using formula addressed in [32]
( )1,2 61 ln 2 coth
8 po
πσ
+ + = ⋅ Ω
. (2.10)
lmp is the mean perimeters of the of the primary turns. σsub is the conductivity of the
substrate. hpo is the distance between the strip and silicon substrate. hsub is the
15
thickness of the substrate.
The passive power transfer efficiency η of the transformer, calculated as the ratio
between the input RF power and the RF power delivered to the load RL can be
computed as [33]
R P n
LP R Q L L Rn k L Q Q n
η ω
ω ω
(2.11)
where Qp and Qs are the quality factor of the primary and the secondary inductors, and
they can be calculated by
p p
L n
L ≈ (2.14)
Figure 2.4 shows comparison of S-parameters among the modeled, EM simulated
and measured results of the planar 2:2 bifilar transformer. The comparisons show
good agreement in a frequency range up to 5 GHz. Figures 2.5(a), 2.5(b), 2.6(a), and
2.6(b) show comparison of self inductance, magnetic coupling coefficient, quality
factor and passive efficiency, respectively, among the modeled, EM simulated and
measured results. The comparisons show good agreement in a frequency range up to
the self-resonant frequency at 4 GHz. In 1.9 GHz PCS band, the measurements show
a maximum passive efficiency of 87% and a peak Q factor of 18.
16
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-5
0
-100
-50
0
50
100
150
200
17
-25
-20
-15
-10
-5
0
(c)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (GHz)
-120 -100
100
(d)
Figure 2.4 Comparison among modeled, EM simulated and measured results of S-parameter of the planar 2:2 bifilar on-chip transformer.
18
-20 -15 -10 -5 0 5
10 15 20 25
0
0.2
0.4
0.6
0.8
1
(b)
Figure 2.5 Comparison among modeled, EM simulated and measured results of (a) self inductance and (b) coupling coefficient for the planar 2:2 bifilar on-chip transformer.
19
-5
0
5
10
15
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
(b)
Figure 2.6 Comparison among modeled, EM simulated and measured results of (a) quality factor and (b) passive efficiency for the planar 2:2 bifilar on-chip transformer.
20
2.2 Implementation of Transformer-Based Integrated Passive Devices 2.2.1 Planar Transformer-based Balun
Balun is commonly used to convert an unbalanced input signal into a balanced
output signal in a wireless front-end [34]. A Marchand balun is conventionally popular
because of the advantage of broadband characteristics [35]-[36]. However, the size of
this configuration is the main drawback, as it employs quarter wavelength
transmission lines at the operating frequency. A square symmetric transformer balun
introduced in [25] possesses an inherent balance and occupies only a very small area
on the IC. But this type of transformer balun usually encounters the high-frequency
limitation due to self-resonant frequency. This study proposes a novel balun design
using a compact symmetrical bifilar transformer of octagonal shape with an inner
common-ground network to achieve a higher self-resonant frequency. As an example,
Figure 2.7(a) shows a silicon IPD balun using the same bifilar transformer shown in
Figure 2.3(a) with a simplified circuit schematic shown in Figure 2.7(b).
1.05 mm
1. 05
m
m
(a)
(b)
Figure 2.7 (a) A silicon balun using a planar 2:2 bifilar transformer and (b) its simplified circuit schematic.
21
This work carried out the measurement on an RF 4-port electrical network
analyzer and an on-wafer RF probe station using G-S-G probes. The measurements
and simulations achieve good agreement. To characterize the performance of a
three-port balun, this investigation evaluates amplitude and phase imbalance, using
the following equations [37]:
Phase Imbalance = 21 31180o S S− ∠ −∠ (2.16)
Common mode rejection ratio (CMRR) is a figure of merit researchers commonly use
to evaluate balanced circuit performance. The CMRR is defined as the ratio between
differential mode and common mode transmission-coefficient magnitude [37]. The
CMRR of a three-port balun can be expressed in terms of three port single-ended
S-parameters as
( )21 31
S S S S
. (2.17)
Dissipated loss (DL) and common-mode-rejection-ratio (CMRR) are two important parameters to evaluate the on-chip balun performance. The DL is regarded as an insertion loss that only considers the dissipated losses such as conductor and dielectric loss [38]. The CMRR is defined as the ratio between differential-mode and common-mode transmission-coefficient magnitude. They can be generally expressed in terms of single-ended S-parameters as follows.
( ) ( )22 2 11 21 31DL 10log dBS S S= − + + . (2.18)
Figure 2.8 depicts the S-parameter responses for the simulated, modeled, and
measured results. Figures 2.9(a) and 2.9(b) show the simulated, modeled and
measured results of amplitude and phase imbalance, respectively. The balun operates
within an amplitude imbalance of 1 dB over the frequency range from 0.1 to 5 GHz
and a phase imbalance of 3 between 0.1 and 3.5 GHz. Figures 2.10(a) and 2.10(b)
22
show comparison of CMRR and DL, respectively, among the modeled, EM simulated
and measured results. One can see from Figures 2.10(a) and 2.10(b) that the modeled
results have an acceptable agreement with the EM simulated and measured ones up to
the self-resonant frequency at 4 GHz. The measured CMRR and DL is larger than 26
dB and less than 1.4 dB, respectively, over the frequency range up to 4 GHz. The size
of this balun is 0.82 mm × 0.82 mm.
0 1 2 3 4 5 Frequency (GHz)
-30
-25
-20
-15
-10
-5
-100 -80 -60 -40 -20
0 20 40 60 80
100
23
-30
-25
-20
-15
-10
-5
-200 -150 -100
(d)
Figure 2.8 Comparisons of modeled and measured S-parameters of the bifilar 2:2 transformer-based balun : (a) magnitude of S21, (b) phase of S21, (c) magnitude of S31, (d) phase of S31.
24
0 1 2 3 4 5 Frequency (GHz)
-5 -4 -3 -2 -1 0 1 2 3 4 5
A m
pl itu
de Im
ba la
nc e
(d B
-10
-5
0
5
10
Modeled EM Simulation Measured
(b) Figure 2.9 Modeled, EM simulated, and measured results of (a) amplitude and (b) phase imbalance of the implemented bifilar 2:2 transformer-based balun.
25
0 5
C M
R R
(d B
0
1
2
3
4
5
Modeled EM Simulated Measured
(b) Figure 2.10 Modeled, EM simulated and measured results of the bifilar transformer-based balun. (a) CMRR (b) DL.
26
2.2.2 Transformer-based Coupled Bandpass Filter
A bandpass filter is also commonly used in a wireless front-end to prevent the
interference of RF signals. Conventional miniaturized bandpass filter structures
mainly rely on an LC resonator ladder network [39]. This kind of LC resonator-based
bandpass filter has difficulty in further reducing its size because of too many element
requirements. This paper presents a novel bandpass filter structure using a planar
transformer. The proposed design technique can realize a small size bandpass filter
over a wide bandwidth range by precisely calculating the required mutual inductance
to couple the transformer coils where each coil resonates with a small capacitor. The
design skillfully applies parasitic mutual capacitances to create transmission zeros for
enhancing the stopband rejection ratio.
Figure 2.11(a) a photograph of a silicon bandpass filter using a planar 1.5:1.5
bifilar transformer. The size of the proposed filter only occupies a 1.82 mm × 1.32
mm area. The bandpass filter has a passband center frequency of 5 GHz and adopts a
second order Chebyshev design with a ripple level of 0.1 dB and a fractional
bandwidth (Δ) of 20%. Figure 2.11(b) illustrates the overall configuration of the
proposed filter, composed of one transformer and two capacitors. Thus, the coupling
coefficients Mij between resonator i and resonator j, and the external input/output
quality factor Qei/Qeo can be calculated as follows:
12 1 2
= = . (2.19)
Δ . (2.21)
where gi’s are filter prototype parameters [40]. As described in [41], the tapped-line
input/output coupling can generate transmission zeros. This configuration can
effectively create multiple attenuation poles near the passband. Figure 2.12 illustrates
the modeled, measured and EM simulated filter results and compares the simulated
results and the measured results in the frequency range of 0.1 ~ 8 GHz. The measured
27
passband return losses shown in Figure 2.12(a) are both below 18 dB while passband
insertion losses shown in Figure 2.12(b) are approximately 3.4 dB. This work
observes two extra transmission zeros on opposite sides of the passbands due to
controlling by the tap coupling input/output position. As a result, two extra
transmission zeros are observable at approximately 3.8 and 5.8 GHz. Good agreement
exists between measured and simulated results.
1.44 mm
0. 66
m m
(b)
Figure 2.11 (a) A silicon bandpass filter using a planar 1.5:1.5 bifilar transformer and (b) its simplified circuit schematic.
28
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
(b)
Figure 2.12 Modeled, EM simulated and measured results of the silicon bandpass filter. (a) |S11| in decibels. (b) |S21| in decibels.
29
CMOS power amplifier has recently aroused widespread interest in silicon-based
SoC designs for wireless applications. However, the issue of oxide breakdown limits
the maximum output power obtainable from the power amplifier. Power combiners
can solve this problem by adding the output power of two or more power amplifiers
[42]-[43]. The CMOS compatible power combiners introduced in [44] usually use a
laterally or vertically coupled transformer as a core element, which generally still has
the balance problem to cause degradation of the power combining efficiency. This
paper demonstrates wideband power combiners using a symmetrical trifilar
transformer with a novel common-ground network design to achieve good balance
performance.
The trifilar transformer can be further categorized as either a series-combining
transformer (SCT) or a parallel-combining transformer (PCT) according to the voltage
or current combining at the load [45]. Figure 2.13(a) shows an power combiner using
a 1:1:2 SCT of octagonal shape with a simplified circuit schematic shown in Figure
2.13(b) while, in contrast, Figure 2.14(a) shows another power combiner using a 1:1:2
PCT of hexagonal shape with a simplified circuit schematic shown in Figure 2.14(b).
Figures 2.15(a) and 2.15(b) show the simulated, modeled, and measured results of the
transmission magnitude and phase of the 1:1:2 SCT power combiner, respectively.
Figures 2.16(a) and 2.16(b) show the simulated, modeled, and measured results of the
magnitude imbalance and phase imbalance of the 1:1:2 SCT power combiner,
respectively. It can be seen that these three kinds of results agree with each other well
in the frequency range up to 4 GHz. The measured amplitude and phase imbalance is
within 1 dB and 3°, respectively, in the frequency range up to 4 GHz. Figures 2.17(a)
and 2.17(b) show the simulated, modeled, and measured results of the transmission
magnitude and phase of the 1:1:2 PCT power combiner, respectively. Figures 2.18(a)
and 2.18(b) show the simulated, modeled, and measured results of the amplitude
imbalance and phase imbalance of the 1:1:2 PCT power combiner, respectively. The
comparisons among the modeled, EM simulated and measured results show
reasonable agreements in 1:1:2 PCT case. The measured amplitude and phase
imbalance is within 0.5 dB and 5°, respectively, in the frequency range up to 4 GHz.
In a similar fashion as an on-chip balun, DL and differential-mode-rejection-ratio
(DMRR) are two important parameters to evaluate the on-chip power combiner
30
performance. The DMRR is calculated as an inverse of the CMRR expressed in (2.17).
Figures 2.19(a) and 2.19(b) compare the DL and DMRR for the two different power
combiners shown in Figures 2.13(a) and 2.14(a). The comparisons among the
modeled, EM simulated and measured results have reasonable agreements in both
cases. The case of the SCT-type power combiner achieves better agreement than the
other case of PCT-type power combiner. The comparisons on performance indicate
that the SCT-type power combiner has a lower DL while the PCT-type power
combiner has a higher DMRR. It is finally noted that the size of the SCT- and
PCT-type power combiner is 1.29 mm × 0.64 mm and 0.94 mm × 0.82 mm,
respectively.
(a)
(b)
Figure 2.13 (a) A silicon power combiner using a 1:1:2 SCT of octagonal shape and (b) its simplified circuit schematic.
31
(a)
(b)
Figure 2.14 (a) A silicon power combiner using a 1:1:2 PCT of hexagonal shape and (b) its simplified circuit schematic.
32
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-35
-30
-25
-20
-15
-10
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-60 -40 -20
100
(b)
Figure 2.15 Modeled, EM simulated and measured results of the 1:1:2 SCT power combiner: (a) Magnitude of S12 (b) Phase of S12.
33
-5
-4
-3
-2
-1
0
-10
-5
0
5
10
Modeled EM Simulated Measured
(b) Figure 2.16 Modeled, EM simulated and measured results of the 1:1:2 SCT power combiner: (a) Magnitude imbalance (b) Phase imbalance.
34
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-30
-25
-20
-15
-10
-5
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-100 -80 -60 -40 -20
0 20 40 60 80
100
re e) Modeled
EM Simulated Measured
(b) Figure 2.17 Modeled, EM simulated and measured results of the 1:1:2 PCT power combiner: (a) Magnitude of S12 (b) Phase of S12.
35
-3
-2
-1
0
1
-10
-5
0
5
10
Modeled EM SImulated Measured
(b) Figure 2.18 Modeled, EM simulated and measured results of the 1:1:2 PCT power combiner: (a) Magnitude imbalance (b) Phase imbalance.
36
D M
R R
(d B
D M
R R
(d B
(b)
Figure 2.19 Modeled, EM simulated and measured results of DMRR and DL for the silicon power combiners. (a) SCT-type (b) PCT-type
37
Chapter 3 Optimum Design of Transformer- Type Marchand Balun Using Scalable Integrated Passive Device Technology
A balun is an important component in balanced microwave front-end circuits such
as balanced mixers [46], and push-pull amplifiers [47], and also in several other
applications. Baluns are mainly used to convert an unbalanced input signal into two
balanced output signals. Baluns can be further classified into active and passive
baluns. The major advantage of active baluns is their small size, which makes them
suitable to be integrated into integrated circuits (ICs). However, the performance of
active baluns in terms of their linearity, noise figure, and balance property is usually
unsatisfactory [48]. Passive baluns can be subclassified as lumped-element baluns and
Marchand baluns. Lumped-element baluns provide balanced outputs only around the
designed frequency, and the balance degrades severely at frequencies away from this
frequency [49]. Marchand baluns [35] have received a great deal of attention because
of their compact size, good balance performance, and wide operating frequency range.
Marchand baluns can be made of coupled-line sections [50], Lange couplers [51], or
planar transformers [52]. A Marchand balun that employs planar transformers has
the advantages of a compact layout and increased mutual coupling, leading to a
shorter required metal length for a given operating frequency. Hence, such a
transformer-type Marchand balun has been widely used in double-balanced mixer
RFIC designs [36], [38].
CHAPTER 3. OPTIMUM DESIGN OF TRANSFORMER-TYPE MARCHAND BALUN USING SCALABLE INTEGRATED PASSIVE DEVICE TECHNOLOGY
38
The Marchand balun model has been analyzed using a curve-fitting technique for
the measurements [46]. However, it is difficult to correlate this type of empirical
model with new or modified designs, because it is not directly linked to the physical
parameters of the balun. Conversely, electromagnetic (EM) simulation can provide a
physical-structure-based analysis [52]; however, it requires a long computation time
and is not easy to tune the multiple parameters of the balun to achieve desired
performance, especially when optimization has been enabled. Complicated analytical
formulas for Marchand baluns have been reported [50], but the extension of this
model to an equivalent circuit model is not straightforward. In general, distinct
guidelines for the circuit design and optimization of Marchand baluns are not
available.
In this chapter, we propose a scalable transformer model in integrated passive
device technology to correlate with the coupled-line sections of a conventional
Marchand balun. The coupled-line section can be modeled as an equivalent lumped
transformer circuit based on our previous work [53]. This improves the efficiency of
the design of planar transformers with equivalent coupled-line parameters such as the
coupling factor, and even- and odd-mode characteristic impedances and Q factors.
Additionally, the proposed model-based design approach provides effective
optimization techniques that incorporate geometrical and material parameters.
Accordingly, through the manufacture of IPD on silicon and glass substrates, this
study explores the achievement of transformer-type Marchand balun designs that are
optimized for minimum insertion loss at the nominal center frequency while providing
good impedance matching and balance over a wide frequency range.
3.1 Planar Transformer-Type Marchand Balun Design 3.1.1 IPD Balun Structure
The current trend toward further miniaturization of electronic system products
increases the demands for their high performance, increased reliability, and reduced
cost. More functions continue to be added to electronic products, and yet, their overall
size continues to shrink. However, the use of a larger number of passive components
in an electronic system will not only require a larger area, but will also increase the
assembly cost. System-in-package (SiP) offers a promising solution for improving
39
device performance and decreasing their size for high-volume applications of passive
components. Among the various SiP approaches, the fabrication of wafer-level IPDs
[54]-[55] is the most attractive way to overcome the above-mentioned drawbacks. The
main feature of such IPDs is that they are fabricated by the same or an additional
process during the fabrication of the devices on the wafer. The IPDs described in this
paper were constructed by applying thin-film process technology to specially prepared
silicon or glass substrates. A cross section of the structure is shown in Figure 3.1. It
consists of three layers of metal with a polyimide interlevel dielectric. The bottom
metal layer is used exclusively for the bottom electrodes of capacitors. This bottom
layer of metal is aluminum, and the top two layers, used for inductor coils, are 10-μm-
and 6-μm-thick layers of copper. The thin film build-up technology allows for a high
level of integration and meets the demands of basic passive elements, such as resistors,
inductors, and capacitors. In this interconnection technology, it is possible to realize
integrated passive components in the RF front-end sub-system with high performance
for wireless communication applications. Based on the above-mentioned fact that
IPDs are generally fabricated by standard wafer fabrication technologies, it is possible
to manufacture a small, low-cost, physical balun structure with excellent
reproducibility.
The basic circuit of a conventional Marchand balun consists of two coupled-line
sections in a planar structure. The length of each coupled-line section at the desired
center operating frequency should be equal to one-quarter wavelength. The coiling of
the coupled-line section into a planar transformer is advantageous in that it increases
the mutual inductance. Consequently, for a Marchand balun designed to operate in a
particular frequency range, the transformer is more compact than the meander
coupled-line sections because it requires a smaller overall length of wire [56]. As
illustrated in Figure 3.2, the transformer composed of two coplanar rectangular spiral
inductors with inner and outer windings, is symmetrical. The Marchand balun design
is based on two transformers cascaded in series, which were fabricated by an IPD
process on 700-μm-thick silicon and glass substrates with the layer structure depicted
in Figure 3.1.
40
Figure 3.1 Cross-sectional view of IPDs with interconnect line, resistor, inductor and capacitor.
w d
Figure 3.2 Layout of Marchand balun using two planar transformers
3.1.2 Marchand Balun Design with a Symmetric Transformer Model
Figure 3.3 shows the block diagram of an ideal Marchand balun, which consists of
two identical λ/4 coupled-line sections [35]. Figure 3.4 shows the proposed equivalent
circuit for the planar transformers of a transformer-type Marchand balun. Each
element in the equivalent circuit of Figure 3.4 has the following physical properties:
Rs denotes the series resistance values of the spiral metal coils. The self-inductance
and mutual inductance of the transformer coils are denoted as Ls and M, respectively.
The capacitance Cps is used to model the mutual electrical coupling of the two
41
interwound coils. Cs denotes the inter-coil and underpass capacitance, and Cpo is the
spiral coil-to-substrate coupling capacitance. Rsub and Csub denote the lossy substrate
resistance and capacitance, respectively.
Figure 3.3 Block diagram of an ideal Marchand balun with two identical λ/4 coupled-line sections
Csub
Figure 3.4 Equivalent circuit of a symmetric transformer.
In order to determine the conditions for model equivalence between the
coupled-line section and the planar transformer, an even- and odd-mode analysis is
42
employed; this analysis decomposes the circuits into two-port networks for
simplifying the complexity of the problem [57]-[58]. Figure 3.5(a) and Figure 3.6(a)
show the even- and odd-mode circuits, respectively, of a coupled-line section. The
characteristic impedances of the even- and odd-mode transmission lines can be
denoted as Zoe and Z0o, respectively. The length of the coupled line is equal to l. The
even- and odd-mode circuits corresponding to a symmetric transformer are shown in
Figure 3.5(b) and Figure 3.6(b), respectively.
l
(a)
(b)
Figure 3.5 Even-mode circuit of (a) a coupled-line section and (b) a symmetric transformer.
43
l
(a)
(b)
Figure 3.6 Odd-mode circuit of (a) a coupled-line section and (b) a symmetric transformer.
The S-parameters of a lossy transmission line with an electrical length of π/2 that use
the even-mode characteristic impedance Z0e or the odd-mode characteristic impedance
Z0o, as shown in Figure 3.5(a) and Figure 3.6(a), respectively, can be obtained as
follows:
e
e
=
+ +
0 0 0 0
e
S Z Z
44
o
o
=
+ +
0 0 0 0
o
S Z Z
(3.4)
where Z0 is the terminal impedance and Q0e and Q0o are the even- and odd-mode Q
factors, respectively. The four-port S-parameters of the coupled lines can therefore be
expressed as [59]
S C I R T I C T R
=
(3.5)
where R, T, C, and I denote the reflection, transmission, coupling, and isolation
coefficients, respectively, of the coupled line.
The various elements of the scattering matrix of a four-port coupled line can be
written in terms of even- and odd-mode scattering parameters and further expressed as
follows:
( )0 011 11 1 2
e oR S S= + (3.6)
( )0 021 21 1 2
e oT S S= + (3.7)
( )0 011 11 1 2
e oC S S= − (3.8)
( )0 021 21 1 2
e oI S S= − (3.9)
The analysis for designing a Marchand balun is based on a coupled line analysis
and further extended to a three-port balun network [60]. The S-parameters of the
Marchand balun in Figure 3.3 can be derived as
45
S S S
1 1 1 1 2 1 2 2 1 2
1 1 1 1 1 1 2 2
1 2 1 1 2 1 2 1 1 22 1 2
1 1 1 1 1 1 2 2
1 2 1 1 2 1 2 1 1 22 1 2
1 1 1 1 1 1
4 2 2 1 1 1
1 12 1 1 1
1 12 1 1 1
x y x y x x x x x x x y x y x y
+ − − − − − − − − − −
− − − − + − − − − +− = − − − − − − − − − − + − − − − +− −
− − − − − −
TCI T R C R x R
R R I − + − −
TCI T R C R y R
R I
R I
TCI T R C R y R
R R I − − − +
(3.14)
Equation (3.11) indicates that the S-parameters of the Marchand balun are determined
by the four coefficients R, T, C and I, obtained from the coupled-line model.
Apparently, the balun design can be reduced to an optimum coupled-line design.
Generally, the insertion loss (I. L.) of a balun can be further estimated as [52]
( ) ( )22 10 21 31. . 10 log dBI L S S≈ − ⋅ + (3.15)
The common-mode rejection ratio (CMRR) is a figure of merit for characterizing a
three-port Marchand balun and is widely used to evaluate the performance of
balanced circuits. CMRR is defined as the ratio of the differential-mode
46
transmission-coefficient magnitude to the common-mode transmission-coefficient
magnitude [37]. The CMRR of a three-port balun can be expressed in terms of the
three port single-ended S-parameters as
( )21 31
S S S S
(3.16)
As mentioned above, a coupled-line section is equivalent to the four-port symmetric
transformer model. Thus, the values of Z0e and Z0o can be derived by equating their
( ) ( )
( ) ( )
po sub sub
C C C R
po sub sub
ω
ω
ω
(3.18)
The most popular definition of the Q factor of a transmission line is that it is the ratio
of the phase constant to twice the attenuation constant. What follows summarizes the
procedure for extracting the effective complex propagation constant (γ = α + jβ) from
the modeled two-port S-parameters. As shown in Figure 3.5(a) and 3.6(a), the
even-mode complex propagation constant γe and odd-mode complex propagation
constant γo were extracted from the two-port S-parameters as [61]
( ) ( ) ( )2 22 2 2 2 2 11, 21, 11, 21, 11,
21,
i
S α βγ +
− + + − + − = (3.19)
where i = e or o, and γi, αi and βi are the complex propagation constant, attenuation
constant and phase constant of mode i, respectively. With (3.19), the even-mode
Q-factor Q0e and odd-mode Q-factor Q0o can be further estimated as
47
Starting from the proposed transformer model for Marchand baluns, scalable physical
lumped models for transformers can be developed and the model elements can be
determined from an analytical expression that uses the geometric and process
technology data. With a physical parameterized layout scheme, the designers can
quickly optimize the planar transformer geometry that best suits the needs of
Marchand balun designs. Further details will be discussed in the following sections.
3.1.3 Transformer Model with Scalability
The exact self-inductances of the primary and secondary ports of the symmetrical
transformer can be calculated using the empirical formula provided in [27] for general
planar inductors. That is
+ = + + + (3.22)
where l, w, and t denote the length, width, and thickness, respectively, of the coiled
conductor strip in centimeters. When designing a balun, it is first necessary to
determine the length of the interwinding metal strip. By analogy with the coupled-line
theory, the band center occurs at the quarter-wavelength resonant frequency of the
individual segments. The metal lines of the nested spiral inductors are equivalent to
quarter-wavelength electrical lengths at the designed operating frequency. The mutual
inductance M between two parallel conductors of equal length l and the geometric
mean distance GMD are given by [28]
2 (nH)mM l Q= (3.23)
where
48
l l GMD GMDQ GMD GMD l l
= + + − + + (3.24)
2 4 6 8 10 ln ln .
12 60 168 360 660 w w w w wGMD d d d d d d
≈ − − − − − (3.25)
Note that GMD is a function of the coil conductor strip width (w) and the distance (d)
between the primary and secondary coils in a transformer. In Figure 3.2, the distance d
is equal to the sum of the conductor strip width w and spacing s.
The self-capacitance and mutual capacitance are approximately calculated based
on a parallel-plate structure using the following equations [30]-[31]:
2 (F)po s t
v C N w
1 (F) 2sub subaC l w C= (3.29)
where Nt is the number of crossovers in winding a coil, εpo is the polymer permittivity,
dv is the height of a via between metal 1 and metal 2, tpo is the polymer dielectric
thickness, and Csuba is the substrate capacitance per unit area.
Some resistances are included in the equivalent lumped models to account for the
frequency-dependent losses, as shown in Figure 3.4. The series resistance Rs is used to
model the conductor loss dominant at lower frequencies, whereas Rsub is used to
model the substrate loss dominant at higher frequencies. The estimate for the
conductor loss resistance Rs which is based on [62], uses the following expression
considering the skin depth
= Ω −
(3.30)
49
where σc and δ denote the metal conductivity and skin depth, respectively. Rsub can be
determined using the formula addressed in [32]:
( ) 61 ln 2 coth
πσ
+ + = ⋅ Ω
(3.31)
where lmp is the mean perimeter of the primary turns, hpo is the distance between the
strip and the substrate, σsub and hsub are the conductivity and thickness of the
substrate, respectively.
3.2 Design Optimization and Results
On the basis of (3.10) and (3.15), the designed optimizations of high-performance
Marchand baluns with different combinations of the geometric conductor line width w
and line spacing s of a transformer are listed in Tables 3.1 and 3.2 for an IPD process
on a silicon substrate and glass substrate, respectively. These tables summarize the
extracted results of a transformer-type Marchand balun design with central frequency
of 2.45 GHz. The geometric parameters w and s can be properly selected on the basis
of the limitations of the fabrication process. The conductor width w ranges from 10 to
40 μm and the spacing s of the coupled line ranges from 10 to 30 μm. It is seen that
the even-mode characteristic impedance value can be decreased, the odd-mode
characteristic impedance value can be increased, and the bandwidth can be reduced by
increasing the metal mutual spacing, because of weakened coupling. In addition, the
odd-mode characteristic impedance value is more sensitive to changes in s between
the lines than the even-mode value is. The minimum values of w and s, which are both
equal to 10 μm, are defined by the foundry rules, highlighting the process limits on
performance syntheses of transformer-type Marchand baluns. Table 3.1 and 3.2 show
that the most sensitive physical parameters of line width w and line spacing s impact
the electrical characteristics and performances of the designed Marchand balun.
Moreover, the interesting observation from Table 3.1 and 3.2 is that the
transformer-type Marchand balun launch the sensitive physical parameter, namely s,
do not have very significant impact on minimum insertion loss, but have significant
impact on well-matched return loss.
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TABLE 3.1 Summary of Even- and Odd-Mode Parameters and Balun Performance at Different
Widths and Spacing of a Transformer in Silicon-Based IPD Technology
(w,s) (μm,μm)
Z0e ()
Z0o ()
R. L. (dB)
CMRR (dB)
(10,10) 445.4 41.9 2.6 4.4 2.8 13.6 159 28.9 (10,20) 441.9 64.6 2.7 5.9 3.4 5.1 63 25.7 (10,30) 440.2 82.2 2.8 6.5 5 3.2 44 22.2 (20,10) 347.6 40.7 3.2 7.3 2 13.9 133 29.4 (20,20) 343.6 59.5 3.4 8.2 3.4 5.9 60 22.4 (20,30) 340.2 73.8 3.4 8.3 4.9 4 38 18.7 (30,10) 282.9 38.8 4.9 9.6 1.5 14.4 112 27.7 (30,20) 281.6 56.2 5.3 11 3 5.9 52 22.3 (30,30) 280 64.4 5.5 11.4 3.9 4.3 37 18.5 (40,10) 241.4 41.2 5.6 10.8 1.7 11.4 110 20.5 (40,20) 239.9 55.6 6 11.1 3.4 5.6 42 18.6 (40,30) 238.1 65.9 6.3 12 4.4 3.8 26 15.6
TABLE 3.2 Summary of Even- and Odd-Mode Parameters and Balun Performance at Different
Widths and Spacing of a Transformer in Glass-Based IPD Technology
(w,s) (μm,μm)
Z0e ()
Z0o ()
R. L. (dB)
CMRR (dB)
(10,10) 525.8 40 48.9 7.7 1.5 15.5 122 29.4 (10,20) 517.5 63.1 48.8 12.2 2.7 5.1 47 25.2 (10,30) 511.2 81.6 48.8 15.5 4.3 2.8 28 22.1 (20,10) 369.6 38.3 48.8 11.8 1 15.8 114 32.5 (20,20) 364.8 57.3 49.1 17.3 2.3 5.4 41 23.9 (20,30) 359.8 71.5 49.2 21 3.6 3.2 21 20.8 (30,10) 302.4 37.4 35.6 11 1.2 15.9 108 25.7 (30,20) 298.8 54.5 36.3 18.5 2.1 5.8 38 20.4 (30,30) 296.2 65.7 36.8 21.8 3.3 3.6 12 17.7 (40,10) 268.9 35.9 22 10 1.3 13.1 106 20.8 (40,20) 264.1 52.4 23 10.2 2.5 6.4 48 18.1 (40,30) 262 62.3 26 12 3.5 4.2 25 16.6
From these tables, we can also see that the return loss is relatively independent of
substrate materials for a given structure. The return loss is mainly determined by the
effective characteristic impedance of the coupled-line structure. The return loss at the
center frequency was found to be between 11 and 16 dB for the minimum spacing of
10 μm, as can be observed from the tables. Interestingly, it is noted that the
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transformer-type Marchand balun designs on silicon and glass substrates can yield a
wider bandwidth, significantly larger than 100 % of bandwidth, and a high CMRR
(>20 dB) with good matching when s is chosen as 10 μm and w is in the range of 10
to 40 μm. The bandwidth of the balun is primarily determined by s and is relatively
sensitive to the mutual coupling of the coupled line. Increasing line spacing is
equivalent to decreasing the mutual coupling, which determines the bandwidth of the
balun. With combinations of s = 10 μm and w = 30 μm for the silicon substrate and s
= 10 μm and w = 20 μm for the glass substrate, the desired designs can yield
well-matched high performances, including the lowest insertion loss with good
impedance matching and high CMRR over a wide bandwidth. The lowest insertion
loss of the baluns on the silicon and glass substrates is 1.5 dB and 1 dB, respectively.
To validate the optimized designs and their performance, Marchand baluns with
the above-specified line width and spacing were implemented using IPD technology
on silicon and glass substrates. Measurements were carried out on an Agilent RF
four-port electrical network analyzer (ENA, E5071B), and a Cascade on-wafer RF
probe station using a probe tip pitch of 150 μm, with
short-open-load-through/reciprocal (SOLT/SOLR) probe-tip calibrations performed
beforehand. Figures 3.7(a) and 3.7(b) show photographs of Marchand baluns
fabricated by IPD technology on silicon and glass substrates, where the chip
dimensions of the baluns were 1.7 × 0.8 mm2 and 1.8 × 0.7 mm2, respectively.
Port 1
(a) (b)
Figure 3.7 Chip photographs of Marchand baluns fabricated by (a) silicon IPD and (b) glass IPD technologies.
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3.2.1 Marchand Balun in Silicon IPD Technology
The S-parameters of the Marchand balun that was fabricated in the silicon IPD
process were measured by an on-wafer measurement technique. Furthermore, the
balun was modeled using the above-mentioned analysis and the measured results were
compared. Figure 3.8 shows comparisons of the modeled and measured results for the
magnitude and phase responses of the proposed silicon-substrate-based IPD Marchand
balun. Obviously, good agreement was achieved between the measurement and
modeling results. As shown in Figure 3.8(a), the measured return loss was found to be
better than 10 dB in the frequency band of 1.5–4.2 GHz; the measured transmission
loss was approximately 4.5 dB around the designed 2.45 GHz. The insertion loss
deviated from the ideal value by only 1.5 dB.
Figures 3.8(c)–3.8(f) shows the results of the balun’s transmission magnitude and
phase responses S21 and S31. The magnitude imbalance and phase imbalance are
calculated as 20 log10(| S21/S31 |) and 180°–|∠(S21)–∠(S31)|, respectively. From the
above measured results, the magnitude and phase imbalance are 0.3 dB and 2.5°,
respectively, at the designed center frequency of 2.45 GHz. Figure 3.9(a) shows the
frequency dependence of the measured CMRR of 27 dB at 2.45 GHz. The insertion
loss is discussed later and shown in Figure 3.9(b). The minimum insertion loss
achieved at 2.45 GHz. was about 1.5 dB, almost the same as that predicted by the
proposed transformer model.
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0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-25
-20
-15
-10
-5
0
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
54
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-45 -40 -35 -30 -25 -20 -15 -10
-5 0
M ag
ni tu
de o
(c)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
55
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-45 -40 -35 -30 -25 -20 -15 -10
-5 0
M ag
ni tu
de o
(e)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
(f)
Figure 3.8 Comparisons of modeled and measured S-parameters of the Marchand balun in silicon IPD technology: (a) magnitude of S11, (b) phase of S11, (c) magnitude of S21, (d) phase of S21, (e) magnitude of S31, and (f) phase of S31.
56
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-5 0 5
C M
R R
(d B
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
0 5
In se
rt io
n Lo
ss (d
(b)
Figure 3.9 Modeled and measured results of the Marchand balun in silicon IPD technology: (a) CMRR and (b) insertion loss.
57
The modeled and measured S-parameters of a glass-substrate-based IPD
Marchand balun are shown in Figure 3.10. It can be observed from this figure that the
modeled results are in good agreement with the measured results. Figure 3.10(a) also
shows that the measured return loss is well matched and equal to 20 dB at about 2.45
GHz and found to be better than 15 dB in the frequency band of 1.8–3.4 GHz. Figures
3.10(c)–3.10(f) shows the results of the balun’s transmission magnitude and phase
responses S21 and S31. As was calculated from the measured results, the magnitude and
phase imbalance at the designed center frequency of 2.45 GHz are 0.45 dB and 2.8°,
respectively. Figures 3.11(a) and 3.11(b) show plots of the CMRR performance and
insertion loss, respectively, of the glass-substrate-based IPD Marchand balun. At 2.45
GHz, the measured CMRR is 29 dB. The measured minimum insertion loss is around
1 dB better than that in the case of the silicon-substrate-based IPD Marchand balun
design at the designed 2.45 GHz.
Table 3.3 presents a comparison of the 10-dB return loss (R. L.) bandwidth,
occupied size, in-band magnitude, phase imbalance, and CMRR of the
transformer-type Marchand baluns to those of the previously reported ones [63]-[65]
implemented using various fabrication technologies. Notably, the ratio of the
frequency range with more than 10-dB return loss to the nominal center frequency is
referred to as the in-band bandwidth in percent. In addition to the in-band bandwidth,
the in-band insertion loss, magnitude imbalance, phase imbalance, and CMRR of the
proposed balun are also compared to those reported in the previous works, as seen in
Table III. The in-band CMRR of the proposed baluns is higher than that in the
previous works because of the excellent performance of the former in terms of
magnitude and phase imbalance. Although the reference designs [63] and [64] have
in-band bandwidths of 116% and 136%, respectively, the measured minimum
insertion loss and in-band CMRR are relatively higher than 1 dB and lower than 20
dB. As shown in Table III, the proposed balun implemented on the IPD glass substrate
has the lowest insertion loss with a comparable in-band bandwidth exceeding 100%
and an excellent CMRR over the in-band frequency range. Overall, the baluns
developed in this work yield minimum insertion loss with excellent CMRR
performance within a small chip area. Notably, the chip area is an essential
consideration during the integration of an on-chip passive device into an RF circuit,
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especially when implemented in IPD technology. These performance characteristics
are good enough to be directly applied to wireless LAN and Bluetooth products.
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-25
-20
-15
-10
-5
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
59
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-45 -40 -35 -30 -25 -20 -15 -10
-5 0
M ag
ni tu
de o
(c)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
60
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-45 -40 -35 -30 -25 -20 -15 -10
-5 0
M ag
ni tu
de o
(e)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-200 -150 -100
(f)
Figure 3.10 Comparisons of modeled and measured S-parameters of the Marchand balun in glass IPD technology: (a) magnitude of S11, (b) phase of S11, (c) magnitude of S21, (d) phase of S21, (e) magnitude of S31, and (f) phase of S31.
61
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
-5 0 5
C M
R R
(d B
(a)
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
0 5
In se
rt io
n Lo
ss (d
(b)
Figure 3.11 Modeled and measured results of the Marchand balun in glass IPD technology: (a) CMRR and (b) insertion loss.
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Ref. Center Freq. (GHz)
10-dB R. L. BW (%)
In-band I. L. (dB)
Process
[63] 3 116 < 1.3 < 0.5 < 15 > 17 1.2×2.3 Silicon IPD
[64] 3 136 < 2 < 0.5 < 14 > 18 1.1×2.1 Silicon IPD
[65] 2.4 83 < 2 < 1.5 < 6 > 19 7×4 Organic IPD
This work
2.45 106 < 1.5 < 0.4 < 7 > 24 1.7×0.8 Silicon IPD
This work
2.45 110 < 1 < 1 < 2 > 24 1.8×0.7 Glass IPD
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Chapter 4 Design and Analysis of Compact Bandpass Filter Using Transformer-Based Coupled Resonators on Integrated Passive Device Glass Substrate
The progress in wireless and mobile communication technology has expanded
rapidly in recent years, as evidenced by the increasing demand for high performance,
low cost, and compact size. A bandpass filter is commonly used in a wireless
front-end to prevent the interference of RF signals. In the past, much research work
was conducted, and various design approaches were proposed. Among them, two
kinds of methods are popular. One of the methods to achieve bandpass operation is to
employ transmission-line structure, and another method to the lumped LC-type
structures adopting to filter design. Most miniaturized bandpass filters extensively
reported in the literature to date are based primarily on the transmission-line structure
[66]-[69]. Filters based on the transmission line element have encountered the
difficulty on size-reduction due to the fact that their sizes are in multiples of
quarter-wavelength. Some other studies propose novel structures to reduce filter size,
including stepped impedance resonator (SIR) [70]-[71], defected ground structure
(DGS) resonator [72], dual-mode ring resonator [73]-[74], and spiral-like resonators
[75]-[77]. However, the resulting designs are complex and not flexible to design. On
the other hand, the experimental responses of lumped LC-type bandpass filters cannot
CHAPTER 4. DESIGN AND ANALYSIS OF COMPACT BANDPASS FILTER USING TRANSFORMER- BASED COUPLED RESONATORS ON INTEGRATED PASSIVE DEVICE SUBSTRATE
64
match the desired prototype responses due to distributed parasitic and coupling effects,
deviating from their ideal behavior [78]. Furthermore, parasitic effects that are
negligible at lower frequencies may significantly alter the characteristics of lumped
components at GHz frequencies. In addition, the kind of LC-type bandpass filter has
difficulty in further reducing its size because of too many element requirements.
In this chapter, a novel compact bandpass filter design using the transformer-based
coupled resonator technique, which is compatible with direct feeding structures in I/O
ports, is proposed and investigated. The bandpass filter features coupled resonators
with a magnetic-dominant coupling coefficients. The proposed design technique can
realize a compact size bandpass filter by precisely calculating the required mutual
inductance to couple the primary and secondary co

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