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Registration Details: (Individual registration)By fax: + 33 1 39 02 71 93 - By email: imaps.france@imapsfrance.orgBy Mail: IMAPS/INTERCONEX, 49 rue Lamartine 78035 Versailles, FranceBy Internet: www.interconex.frAn attendee certificate is provided on request

Tutorials: m 300 e (EACH) VAT excl.

Students (Universities, Laboratories):m 80 e conferences attendance, proceedings, without lunch and social event

FEES: Speakers / Chairs / Technical Committee:m 320 e VAT excl. Social Event Included

IMAPS Member (A020………………) IMAPS 2017 Membership updatedm 360 e VAT excl. (till April 14)

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Non-Member.m 450 e VAT excl. (till April 14)

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INTERCONEX BANK REFERENCESBNP PARIBAS VERSAILLES ETATS GENERAUX, 36 rue des Etats Généraux 78002 Versailles - France. Bank code 30004 Account number n°00010022786 Key Rib 63, Agency 00859 IBAN FR 76 3000 4008 0 0100 2278663 BIC BNPAFRPPVRS

Training agreement: N° 11780608378 French Auditors OnlyTraining “formulaire” on request, tick box m

2017 CONFERENCE PROGRAM - EXHIBITION English Speaking for all PresentationsGENERAL CHAIR : J.L DIOT, NOVAPACK - VICE TECHNICAL CHAIRS: M. GARNIER, ST MICROELECTRONICS & G. POUPON, CEA - LETI,

TUESDAY MAY 16TH

14h00/16h30 Lecture Mervi Paulasto (Aalto University, Makalu Room) Design For Reliability for Multi-Materials AssembliesWEDNESDAY MAY 17TH

9h00 Welcome to MINaPAD9h15 Opening by Jean-Luc Diot (Auditorium)9h30 Keynote 1: Mervi Paulasto (Aalto University): New Materials Entering MEMS (Auditorium)

10h15 Exhibition Opening (Exhibition Hall)Session A: Emerging Applications Session B: Flip-Chip Processes

10h45 High Power, PCB-Embedded Inductors Based on Ferrite Powder ( C. Buttay – INSA) Advanced Packaging for Future Demands (S. Lohse, FINETECH)11h10 Parylene Nanostructures and Coatings for Electronics Applications (R. Kumar, SPECIALTY COATING SYSTEMS) Comparison of Low Pitch Screen Printed SAC Bumps Versus ECD Manufacturing Techniques for Power 3D Integrated Flip Chip Devices (A. Plihon, CEA-LETI)11h35 A Highly Sensitive Humidity Sensor Integrated to a Flip-Chip Package for Moisture Detection in Electronics Package (A. Quelennec, Bordeaux University) Qualification of electroless UBM and Wafer Level Solder Bumping for Flip Chip and WLCSP (D. Lieske, AEMtec)

12h00/13h15 - Lunch & Exhibition (Exhibition Hall)Session C: Fan-Out & 3D Packaging Session D: Wafer Level Process

13h15 3D and 2.5D technology: Current Adoption, Market Trends & Future Challenges (E. Jolivet, YOLE Développement) Novel Method for High-Volume Via Formation in Solid-Core Glass for IC Substrates (R. Ostholt, LPKF)13h40 A Wafer Level Packaging Approach for Power LEDs (M. Volpert, CEA-LETI) Alternative Deposition Solution or Cost Reduction of TSV Integration (J. Vitiello, KOBUS)14h05 Application of 3D PLUS WDoD™ Technology for the Manufacturing of Electronic Modules in Implantable Products (P. Couderc, 3D Plus) Substrate-Less Approach by Single Layer Transfer for RFSOI Performance (A.Vinci, CEA-LETI) 14h30 Optimization of Assembly for Fan Out Packaging (B. Chylak, KULICKE and SOFFA) TSV with 40µm Diameter Replacing Wiring Pads (G. Pardeder, AMS)

14h55-15h30 - Exhibition/coffee breakSession E: Embedded Applications/UNSETH Project Session F: Advanced Singulation

15h30 Technical Agenda and Building Blocks in Electronic Assembly and Packaging for Secure IoT Solutions (B. Candaele, THALES) V-DOE Laser Full Cut Dicing of Thin Si IC Wafer (J. Van Borkulo, ASMPT)15h55 Tamper Respondent Envelope Solutions Realized by Additive Manufacturing-Smart Packaging Solutions for Secure Applications (F. Roscher, ENAS Fraunhofer) Solutions for Thin and Tiny Dies With High Die Strenght and for Thinning WLCSP and eWLB Wafers (G. Klug, DISCO HI-TEC)16h10 Development of High Density Thin Wafer-level SiP for Wafer-Level 3D Packaging and System Integration Secure Solutions in FOWLP (A. Cardoso, NANIUM) Plasma Dicing; Reducing the Cost of Singulating Thinner, Smaller Die (R. Barnett, SPTS Technologies)16h35 New Generation of Component Embedding Technology for High End Applications (T. Schwartz, ATS) Plasma Dicing on Tape (M. Notarianni, PLASMA-THERM)17h00 Reliability Characterization of Advanced Technological Bricks for Secure Smart Systems : HDI Embedded PCB & Anti-Tamper Solutions (A. Lecavelier, THALES) Exhibition

17h30/18h00 Exhibition19h30 Social event « Les Jardins de Sainte Cecile » Restaurant

THURSDAY MAY 18TH

9h00 Keynote 2: Christophe Zinck (ASE): Fan-In WLCSP a mature technology? What’s next? (Auditorium)

Session G: Design Session H: Advanced FC Process9h45 BGA Package Design Techniques for Electrical Performance Awareness (G. Graziosi, STMicroelectronics) 10nm CPI Study for Fine Flip Chip Attach Process and Substrate (MC. Hsieh, STATS ChipPAC)10h10 Design and Verification Methodology of Heterogeneous Chips and Assemblies for Flip-Chip and 2.5D/3D Applications (O. Guillier, CMP) Study of High UPH TCB Process with high throughput NCP (H. Myodo, NAMICS)

10h35 LGA/BGA Substrate Package Design Productivity Enhancement with Cadence Ravel: DRC checks, Layout Generation & Optimization (L. Schwarz, STMicroelectronics) Advanced Underfill Solutions Tailored for Next Generation Flip Chip Devices (R. Guino, HENKEL)

11h00 -11h35 Exhibition/coffee break Session I: High-Rel Packaging Session J: STD Assembly Process

11h35 Solder Paste Deposition: New Challenges for Fine Pitch Assemblies in Military Applications (A. Chaillot, A. Mauret, MBDA) Large Format Packaging for IoT (N.Fan, ASM)12h00 Packaging of Micro-Module Dedicated to Power Amplifier HF Application for Avionic Communication (S. Bellenger, EOLANE Angers) Copper Wire in Automotive : Key Challenges and Robust Validation (S. Quercia, STMicroelectronics)12h25 Hermetic Package Design and Optimization for Encapsulation of an X-Band 50 W GaN High Power Amplifier (L. Marechal, UMS) Controlling Die Attach Flow –Film and Liquid Solutions (T. Winster, HENKEL)

12h50/14h00 - Lunch & Exhibition (Exhibition Hall)Session K: Power Applications Session L: Advanced Process & Characterization

14h00 Development, Characterization and Optimization of Copper Clip Package for Power MOSFETs (K.K Lwin, UTAC) 3D Defect Localization Technique Using Lock-in Thermography Coupled to an Automatic Test Equipment (F.Infante, INSTRASPEC Technologies)

14h25 Second Level Reliability of QFN Cavity Packages Based on Liquid Crystal Polymer Thermoplastics-Experimental Results and Finite Elements Analysis Comparison(B. Levrier, BRUNO LEVRIER EXPERTISES) Cost Effective Integration of Optical Waveguides on Thin Film Interposer (E. Dubois, IEMN Lille)

14h50 Keynote 3: Seung Wook Yoon, (STATS-ChipPAC): FO-WLP: The third Wave of Fan-Out Packaging with Scalability (Auditorium)15h35 Best Paper Award16h00 End of MiNaPAD 2017

TUESDAY 16TH

Professional Development Courses

9h00/12h00

Tutorial 1 Optical Interconnects Integration, Packaging and Reliability - (S.BERNABE and L. MENDIZABAL – CEA-LETI)

Tutorial 2 Tutorial Introduction to MEMS Packaging - (JP. POLIZZI – CEA-LETI)

Tutorial 3 Reliability Analysis for Advanced Packages - (Y. Ousten, IMS Bordeaux)

Tutorial 4 Thermal Management in Microelectronics - (JL. DIOT – AssemblinoV)Lecturer 14h00/16h30 Lecture Mervi Paulasto (Aalto University , Makalu Room) Design for Reliability for Multi-Materials Assemblies

FRENCH CHAPTER

FRENCH CHAPTER

FREE EXHIBITION PASS (Pick up your badge at Information Desk)

m Mrs, m M.

Name: .................................................................... Firstname: ...................................................................

Job Title: .........................................................................................................................................................

Company: .......................................................................................................................................................

Zip: ..................................... City ..................................... Country ...............................................................

Email: ...............................................................................................................................................................

Registration Details: (Individual registration)By fax: + 33 1 39 02 71 93 - By email: imaps.france@imapsfrance.orgBy Mail: IMAPS/INTERCONEX, 49 rue Lamartine 78035 Versailles, FranceBy Internet: www.interconex.frAn attendee certificate is provided on request

EXHIBITING COMPANIES (updated March 20)

MiNaPAD FORUM 2017 WTC Grenoble 5-7 Place Robert Schuman www.congres-wtcgrenoble.comOPENING HOURS:May 16: 9h00 – 12h00 – 14h00 – 16h30 May 17: 9h00 – 18h00 May 18: 9h00 – 16h00

PUBLIC TRANSPORTATION:• BY CAR

from Geneva and Chambery on the A41 motorway take the rocade sud (ring road) follow signs to Lyon by motorway, take the Europole exit and follow signs to Europole. From Lyon on the A48 motorway: take the Europole-Gares and follow signs to Europole

• RAILWAY STATIONS STOP Line A : Railway Stations Stop Line B: “Palais de Justice” Stop

Event MINAPAD FORUM 2017 Event ID: 30187 AF Valid for travel from 11/05/2017 to 23/05/2017Event location: Grenoble, FranceAttractive discounts on a wide range of public fares on all Air France and KLM flights worldwide**..

• AIRPORT SHUTTLE BUSES Lyon Saint Exupéry: 17 rounds trips days per week Geneva Cointrin: 3 round trips 7 days per week

SNCF pass for 20% discount on return tickets for participants attending the exhibition are available on request from INTERCONEX organization.Arrival by train use the underpass between the railway station and Europole.

• ACCOMMODATION:Contact IMAPS/INTERCONEX Organization: by Phone + 33 1 39 67 17 73By fax +33 1 39 02 71 93 or by email: imaps.france@imapsfrance.org

n ACCELONIXn ASEn BT ELECTRONICSn CDS NAMICSn CSTn DISCO HI-TECn EGIDEn ELEMCAn ELECTRON MECn HCM Systrel SERMA GROUPn HYBRIDn HENKELn INSIDIXn INSTRASPECn ISP SYSTEMS

n JFP MICROTECHNICn KYOCERA FINECERAMICSn METRONELECn MICROSS COMPONENTS n MICROTEST n MSEn NTK TECHNICAL CERAMICSn PLASMA –THERMn PREDICTIVE IMAGEn PROTAVICn PTSn SAES GETTERSn SPECIALTY COATING SYSTEMSn TAIPRO Engineeringn YOLE DEVELOPPEMENT

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5th Micro/Nano-ElectronicsMiNaPAD Forum 2017MiNaPAD Forum 2017

Packagingand Assembly

May 17-182017May 17-18

GRENOBLEFrance

GRENOBLEFrance

WTCWTC2017

IMAPS - International Microelectronics Assembly and Packaging Society49 rue Lamartine 78035 Versailles

France Tel: +33 (0) 1 39 67 17 73 Fax: +33 (0) 39 02 71 93Imaps.france@imapsfrance.org www.france.imapseurope.org

5th Micro/Nano-ElectronicsMiNaPAD Forum 2017MiNaPAD Forum 2017

Packagingand Assembly

May 17-182017May 17-18

GRENOBLEFrance

GRENOBLEFrance

WTCWTC2017

IMAPS - International Microelectronics Assembly and Packaging Society49 rue Lamartine 78035 Versailles

France Tel: +33 (0) 1 39 67 17 73 Fax: +33 (0) 39 02 71 93Imaps.france@imapsfrance.org www.france.imapseurope.org

5th Micro/Nano-ElectronicsMiNaPAD Forum 2017MiNaPAD Forum 2017

Packagingand Assembly

May 17-182017May 17-18

GRENOBLEFrance

GRENOBLEFrance

WTCWTC2017

IMAPS - International Microelectronics Assembly and Packaging Society49 rue Lamartine 78035 Versailles

France Tel: +33 (0) 1 39 67 17 73 Fax: +33 (0) 39 02 71 93Imaps.france@imapsfrance.org www.france.imapseurope.org

AFKLM Official carriersNº dossier : 2008140E

Date : 03/06/08

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AIR FRANCE & KLM GLOBAL MEETINGS

NEXT IMAPS EVENTS CALENDAR• September 2017 - 10 - 13 EMPC 2017 - 21st European Microelectro-nics and Packa-ging Conference Warsaw University of Technology, Poland

• October 2017 - 11 - 12 8th From Nano to Macro Power Electronics and Packaging International workshop, Tours, France

• November 2017 - 22 - 23 5th ATW On Microelectronics and Packaging for Medical Applications, Lyon, France

• January 2018 - 30 - 31 13rd ATW on Micropackaging and Thermal Management, La Rochelle France

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• Lecture: Design for Reliability for Multi-Materials Systems (Mervi Paulasto-Kröckel, Aalto University, Finland)

Components and assemblies of micro- and nanoelectronics are complex multi-material systems. They are typically composed of alternating thin layers of metals, ceramics, polymers and semiconductors with numerous interfaces. The trends in demanding applications of ubiquitous electronics lead to increasing those discontinuity areas with smaller dimensions and more severe loading conditions. With all potential interactions in multi-material systems, reliability performance is ever more difficult to control. Yet, the de-velopment methods are often immature from materials science and engineering perspectives. Much of the hardware development across the value chain is still purely experimental. Such “trial and error” methods will be too slow and costly in the development of future integrated micro- and nano-systems.This lecture presents an alternative route for materials and process development, introducing a combined me-thodology based on thermodynamics, reaction kinetics, theory of microstructures and stress/strain analysis in reliability design. An introduction is given to phase diagrams calculation (Calphad) approach, as an efficient method of accurately modelling thermodynamic properties and phase diagrams of multicomponent systems. The method is demonstrated with several examples including SnCu/Ni solder joint, wafer level hermetic SnAu/X (X=Cu,Ni,Pt) interconnections for MEMS and Au-Cu-Al for wire bonding. Performances of an interconnection sys-tem, metallization schema or another multi-material structure are understood with this combined methodology. This will reduce the number of experiments in the development phase and in the clarification of potential quality issues in volume manufacturing.

• Tutorial 1: Optical Interconnects Integration, Packaging and ReliabilityStéphane BERNABE and Laurent MENDIZABAL – CEA-LETIThis short course will present an overview of the past, present and future of optoelec-tronic packaging, through case studies dealing with a selection of today’s applications of optoelectronics. We will particularly focus on optical interconnections between laser sources and optical waveguides by detailing the underlying theory used by packaging engineers and by benchmarking several legacy and emerging assembly technologies. Evo-lution of optoelectronic modules and package will also be described and convergence between photonic modules and semiconductor modules will be discussed, especially from the point of view of Photonics & 3D packaging convergence. Finally, the speci-ficities of optoelectronic modules in term of characterization methods and reliability testing will be reviewed.

• Tutorial 2: Introduction to MEMS PackagingJean-Philippe POLIZZI – CEA-LETIThis short course will review common MEMS packaging techniques based on wafer bonding technologies. That includes polymer bonding, anodic bonding, eutectic and thermo-com-pression bonding as well as Transient Liquid Phase bonding. The Pros and Cons of these various wafer bonding processes will be compared. Thin film packaging techniques, and their potential for microsystems applications will also be presented. The presentation will end with a review of reliability aspects and the methods used for testing bonding quality and hermeticity, a critical aspect when packaging resonating structures.

• Tutorial 3: Reliability Analysis for Advanced PackagesYves OUSTEN – IMS BORDEAUXA large number of industrial actors and university researchers perform reliability. Only, it is very often complicated to know on which level of integration or maturation this reliability was analyzed. In our professional course, we will break up the various ways to approach the reliability of the electronic components as well as systems. We will see that reliability is often connected with robustness. First of all, we will explain the differences between safety, the security, reliability and quality. Then, we will try to carry out “synchronization” between the concept of TRL (Technology Readiness Level) and the analysis of reliability. Lastly, we will show the interest of the intelligent recycling of cards and electronic components by integrating the concept of circular economy.

• Tutorial 4: Thermal Management in Microelectronics Jean-Luc DIOT – ASSEMBLINNOVThis tutorial reviews package thermal management, to help engineers in packaging architecture choices. A simple model, network of elementary thermal resistances, will be assessed for all power packages. This model will help to understand dissipa-tion in power modules and coupling resistances. Optimization of heat extraction of surface mounted power packages on various boards will be discussed. Common metal based signal packages will be reviewed with a focus on enhanced thermal dissipation: exposed-pad and QFN. Thermal dissipation of organic based packages –mainly BGA- will be addressed, including Flip-Chip assembly. Guide-lines for evaluation of BGA thermal resistance will be discussed. Li-mits of the analogy with electricity are reached in transient conditions. Evaluation of transient thermal impedance will be discussed through some examples. During the course, simple Excel files will be given to support initial package choices (power packages and exposed-pad packages).