2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using...

9
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems April 8–10, 2013 Karlovy Vary, Czech Republic Symposium Programme Co-sponsored by IEEE Computer Society Test Technology Technical Council and Faculty of Information Technology Brno University of Technology

Transcript of 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using...

Page 1: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

2013 IEEE 16th International

Symposium on

Design and Diagnostics of

Electronic Circuits & Systems

April 8–10, 2013 Karlovy Vary, Czech Republic

Symposium Programme

Co-sponsored by

IEEE Computer Society

Test Technology Technical Council

and

Faculty of Information Technology

Brno University of Technology

Page 2: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

MONDAY A PRIL 8, 2013

9:00 – 9:20 OPENING SESSION Room A Chair: Lukáš Sekanina, Brno University of Technology (CZ)

9:20 – 10:20 KEYNOTE PRESENTATION I Room A Chair: Görschwin Fey, University of Bremen (DE)

Hardware-Software Co-Visualization - Developing Systems in the Holodeck Rolf Drechsler University of Bremen/DFKI, Germany

10:20 – 10:50 COFFEE BREAK

10:50 – 11:50 SESSION 1A Room A

Architecture Chair: Zoran Stamenković, IHP (DE)

Exploring Processor Parallelism: Estimation Methods and Optimization Strategies Roel Jordans, Rosilde Corvino, Lech Jozwiak, Henk Corporaal Eindhoven University of Technology, The Netherlands

On Design of Priority-Driven Load-Adaptive Monitoring-B ased Hardware for Managing Interrupts in Embedded Event-Triggered Systems Josef Strnadel Brno University of Technology, Czech Republic

Area-Speed Efficient Architecture for GF(2m) Multipliers Dedicated for Cryptographic Applications Danuta Pamula, Edward Hrynkiewicz Silesian University of Technology, Poland

10:50 – 11:50 SESSION 1B Room B

Advanced Testing Chair: Elena Gramatová, Slovak Univ. of Technology (SK)

On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors Stefano Di Carlo, Ernesto Sanchez, Matteo Sonza Reorda Politecnico di Torino, Italy

Fault Collapsing of Multi-Conditional Faults René Krenz-Bååth1, Andreas Glowatz2, Friedrich Hapke2 1: Hochschule Hamm-Lippstadt, Germany; 2: Mentor Graphics, Germany

Efficient Automated Speedpath Debugging Mehdi Dehbashi1, Görschwin Fey1,2 1: University of Bremen, Germany; 2: German Aerospace Center, Bremen, Germany

11:50 – 12:50 EMBEDDED TUTORIAL I Room A

Chair: Jaan Raik, Tallinn University of Technology (EE)

Interpolation-Based Model Checking for Efficient Incremental Analysis of Software Grigory Fedyukovich, Antti E. J. Hyvärinen, Natasha Sharygina University of Lugano, Switzerland

12:50 – 14:00 LUNCH Restaurant Charleston

Page 3: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

MONDAY A PRIL 8, 2013

14:00 – 15:00 SESSION 2A Room A System-Level Design

Chair: Sebastian Sattler, U. of Erlangen-Nuremberg (DE) A Static Analysis Approach to Data Race Detection in SystemC

Designs Mikhail Moiseev1, Mikhail Glukhikh1, Alexey Zakharov2, Harald Richter3 1: St. Petersburg State Polytechnical University, Russia; 2: Yandex, Russia; 3: Clausthal University of Technology, Germany

Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications Alexander Finder1, Jan-Philipp Witte1, Görschwin Fey1,2 1: University of Bremen, Germany; 2: German Aerospace Center, Germany

Design of Stochastic Viterbi Decoders for Convolutional Codes Te-Hsuan Chen, John P. Hayes University of Michigan, USA

14:00 – 15:00 SESSION 2B Room B High Frequency Design

Chair: Witold Pleskacz, Warsaw U. of Technology (PL) 10Gb/s Inverter Based Cascode Transimpedance Amplifier in

40nm CMOS Technology Mohamed Atef, Hong Chen, Horst Zimmermann Vienna Univesity of Technology, Austria

Ultra-High Bandwidth Fully-Differential Three-Stage Operational Amplifiers in 40nm Digital CMOS Hong Chen1, Vladimir Milovanović1, Dario Giotta2, Horst Zimmermann1 1: Vienna University of Technology, Austria; 2: Lantiq A GmbH, Villach, Austria

A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved Yu-Lung Lo1, Jhih-Wei Tsai1, Han-Ying Liu1, Wei-Bin Yang2 1: National Kaohsiung Normal University, Taiwan, Republic of China; 2: Tamkang University, Taiwan, Republic of China

15:00 – 16:40 POSTER SESSION & COFFEE & WINE

Atrium

Chair: Richard Růžička, Brno University of Technology (CZ) Composing Data-driven Circuits Using Handshake in the Clock-

Synchronous Domain Jaroslav Sýkora Academy of Sciences of the Czech Republic, UTIA, Czech Republic

A Don't Care Identification Method for Test Compaction Hiroshi Yamazaki1, Motohiro Wakazono1, Toshinori Hosokawa1, Masayoshi Yoshimura2 1: Nihon University, Japan; 2: Kyushu University, Japan

Test Pattern Decompression in Parallel Scan Chain Architecture Martin Chloupek1, Jiří Jeníček2, Ondřej Novák2, Martin Rozkovec2 1: Czech Technical University in Prague, Czech Republic; 2: Technical University in Liberec, Czech Republic

Indoor Energy Harvesting Using Photovoltaic Cell for Battery Recharging Hong-Yi Huang1, Chinet Otic Mocorro1, Julyver Pinaso1, Kuo-Hsing Cheng2 1: National Taipei University, Taiwan, Republic of China; 2: National Central University, Taiwan, Republic of China

Page 4: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

MONDAY A PRIL 8, 2013

Noise and Linearity Analysis of a Frequency to Voltage Converter Jørgen Andreas Michaelsen, Dag T. Wisland University of Oslo, Norway

Energy-Aware Software Development for Embedded Systems in HW/SW Co-Design Paul Ehrlich, Stephan Radke Fraunhofer IIS, Germany

A New Method for Correcting Time and Soft Errors in Combinational Circuits Egor S. Sogomonyan, Stefan Weidling, Michael Goessel University Potsdam, Germany

External Capacitorless Low Dropout Linear Regulator using Cascode Structure Hong-Yi Huang1, Cheng-Yu Chen1, Kuo-Hsing Cheng2 1: National Taipei University, Taiwan, Republic of China; 2: National Central University, Taiwan, Republic of China

FPGA Based Time-of-Flight 3D Camera Characterization System Johannes Seiter1, Michael Hofbauer1, Milos Davidovic2, Horst Zimmermann1 1: Vienna University of Technology, Austria; 2: Avago Technologies Fiber Austria

Error Resilient OBDDs Anna Bernasconi2, Valentina Ciriani1, Lorenzo Lago1 1: Università degli Studi di Milano, Italy; 2: Università di Pisa, Italy

Design of an S-band 0.35 µm AlGaN/GaN LNA using Cascode Topology H. L. Kao, C. S. Yeh, C. L. Cho, B. W. Wang, P. C. Lee, B. H. Wei, H. C. Chiu Chang Gung University, Taiwan

Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of Science and Technology, Norway

Reliability-aware Cross-Layer Custom Instruction Screening Bahareh J. Farahani, Ali Azarpeyvand, Saeed Safari, Seid Mehdi Fakhraie University of Tehran, Iran

Efficiency of Oscillation-based BIST in 90nm CMOS Active Analog Filters Daniel Arbet, Gabriel Nagy, Viera Stopjaková, Gábor Gyepes Slovak University of Technology, Slovak Republic

FPGA Architecture for Fast Floating Point Matrix Invers ion Using Uni-dimensional Systolic Array Based Structure Ondřej Hnilička Technical University of Liberec, Czech Republic

Redundancy Algorithm for Embedded Memories with Block-Based Architecture Štefan Krištofík, Elena Gramatová Slovak University of Technology, Slovak Republic

Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability Marcela Šimková1, Zdeněk Kotásek1, Cristiana Bolchini2 1: Brno University of Technology, Czech Republic; 2: Politecnico di Milano, Italy

Fault-Tolerant Reconfigurable Low-Power Pseudorandom Number Generator Vladimir Petrović1, Zoran Stamenković1, Mile Stojčev2, Tatjana Nikolić2, Goran Jovanović2 1: IHP, Germany; 2: University of Niš, Serbia

Industrial Presentation: Multicore Platforms for Image Processing

Otto Fučík CAMEA, spol. s r.o.

Page 5: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

MONDAY A PRIL 8, 2013

STUDENT POSTERS MBIST for LEON3 Processor Core Cache

Andrej Kincel, Marcel Baláž Institute of Informatics, Slovak Academy of Sciences, Slovak Republic

Fault Tolerant CAN Bus Control System Implemented into FPGA Karel Szurman, Jan Kaštil, Martin Straka, Zdeněk Kotásek Brno University of Technology, Czech Republic

Improved Design of the Uninterruptable Power Supply Unit for Powering of Network Devices Martin Pospíšilík, Petr Neumann Tomáš Baťa University in Zlín, Czech Republic

Hybrid Mesh-Ring Wireless NoC for Multi-Core System Mohamed A. Wanas1, Mohamed Abd El Ghany1,2, Klaus Hofmann2 1: German University in Cairo, Egypt; 2: TU Darmstadt, Germany

Novel Model Calibration Method Based on Differential Evolution Used for SCR Model Fitting Tomáš Nápravník1, Přemysl Žiška2, Jiří Jakovenko1 1: Czech Technical University in Prague, Czech Republic; 2: ASICentrum s.r.o., Czech Republic

16:40 – 17:20 SESSION 3A Room A Image Processing

Chair: Karel Vlček, Tomáš Baťa University in Zlín (CZ) An Efficient Hardware Architecture Design for H.264/AVC Intra

Prediction Reconstruction Path Milica Orlandić, Kjetil Svarstad Norwegian University of Science and Technology, Norway

Automatic Synthesis of Small AdaBoost Classifier in FPGA Filip Kadlček, Otto Fučík Brno University of Technology, Czech Republic

16:40 – 17:20 SESSION 3B Room B Robust Circuits

Chair: Andreas Steininger, Vienna Univ. of Technology (AT) A Low Jitter Delay-Locked-Loop Applied for DDR4*

Yo-Hao Tu1, Kuo-Hsing Cheng1, Hsiang-Yun Wei1, Hong-Yi Huang2 1: National Central University, Taiwan, Republic of China; 2: National Taipei University, Taiwan, Republic of China

Power Analysis Methodology for Secure Circuits Kamil Gomina1,2, Jean-Baptiste Rigaud2, Philippe Gendrier1, Philippe Candelier1, Assia Tria2 1: STMicroelectronics, France; 2: Ecole Nationale Supérieure des Mines de Saint-Etienne, France

17:20 – 18:20 EMBEDDED TUTORIAL II Room A Chair: Manfred Dietrich, Fraunhofer IIS/EAS (DE)

Cross-layer Resilient System Design Mehdi Tahoori Karlsruhe Institute of Technology, Germany

19:00 – 20:00 DINNER Restaurant Melody II

20:00 – 22:00 WELCOME DRINK Atrium

* Student paper

Page 6: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

TUESDAY APRIL 9, 2013

9:00 – 10:00 KEYNOTE PRESENTATION II Room A Chair: Lukáš Sekanina, Brno University of Technology (CZ)

Approximate Computing for Energy-efficient Error-resilient Multimedia Systems Kaushik Roy Purdue University, USA

10:00 – 11:00 SESSION 4A Room A Student Papers: RTL Design

Chair: Katarína Jelemenská, Slovak Univ. of Tech. (SK) Towards Hardware Architecture for Memory Efficient IPv4/IP v6

Lookup in 100 Gbps Networks Jiří Matoušek, Martin Skačan, Jan Kořenek Brno University of Technology, Czech Republic

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC Saif Abrar Syed1,2, Maksim Jenihhin2, Jaan Raik2 1: IBM, Bangalore, India; 2: Tallinn University of Technology, Estonia

Multiobjective Evolution of Approximate Multiple Constant Multipliers Jiří Petrlík, Lukáš Sekanina Brno University of Technology, Czech Republic

Hardware Architecture for the Fast Pattern Matching Jan Kaštil, Vlastimil Košař, Jan Kořenek Brno University of Technology, Czech Republic

10:00 – 11:00 SESSION 4B Room B Student Papers: Robust Design

Chair: Péter Földesy, Peter Pazmany Catholic Univ. (HU) Digital Methods of Offset Compensation in 90nm CMOS

Operational Amplifiers Gabriel Nagy, Daniel Arbet, Viera Stopjaková Slovak University of Technology, Slovak Republic

Frequency Injection Attack on a Random Number Generator Simona Buchovecká, Josef Hlaváč Czech Technical University in Prague, Czech Republic

Embedded Microcontroller System for PilsenCUBE Picosatellite Pavel Fiala, Aleš Voborník University of West Bohemia, Czech Republic

Proton Beam Characterization at Oslo Cyclotron Laboratory for Radiation Testing of Electronic Devices Amir Hasanbegovic1, Snorre Aunet2 1: University of Oslo, Norway; 2: Norwegian University of Science and Technology, Norway

11:00 – 11:30 COFFEE BREAK

11:30 – 12:30 EMBEDDED TUTORIAL III Room A Chair: Ondřej Novák, Technical University of Liberec (CZ)

Hardware Acceleration in Computer Networks Jan Kořenek CESNET, z.s.p.o., Czech Republic

12:30– 14:00 LUNCH Restaurant Charleston

14:00 – 23:00 SOCIAL EVENT Meeting point: Hotel Lobby

Page 7: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

WEDNESDAY APRIL 10, 2013

9:00 – 10:00 KEYNOTE PRESENTATION III Room A Chair: Zdeněk Kotásek, Brno University of Technology (CZ)

Creating Options for 3D-SIC Testing Erik Jan Marinissen IMEC, Belgium

10:00 – 11:00 SESSION 5A Room A Advanced Network and Bus Subsystems

Chair: Zdeněk Plíva, Technical University of Liberec (CZ) Enhanced Fault-Tolerant Network-on-Chip Architecture Using

Hierarchical Agents Mojtaba Valinataj1, Pasi Liljeberg2, Juha Plosila2 1: Babol University of Technology, Iran; 2: University of Turku, Finland

A System-Level Overview and Comparison of Three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0† Julien Saadé1,3, Frédéric Petrot3, André Picco2, Joel Huloux2, Abdelaziz Goulahsen2 1: ST-Ericsson, Grenoble, France; 2: STMicroelectronics, Grenoble, France; 3: TIMA Laboratory, Grenoble, France

A Multi-Credit Flow Control Scheme for Asynchronous NoCs Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger Vienna University of Technology, Vienna, Austria

10:00 – 11:00 SESSION 5B Room B Calibration, Reliability, and Simulation Techniques

Chair: Snorre Aunet, NTNU Trondheim (NO) An Indirect Technique for Estimating Reliability of Anal og and

Mixed-Signal Systems during Operational Life Muhammad Aamir Khan, Hans G. Kerkhoff University of Twente, The Netherlands

Intermediate Frequency Filter Calibration Method for Radio Frequency Receivers in Modern CMOS Technologies Krzysztof Siwiec, Aleksander Koter, Witold Pleskacz Warsaw University of Technology, Poland

Numerical Method for DC Fault Analysis Simplification and Simulation Time Reduction Juraj Brenkuš, Viera Stopjaková, Gábor Gyepes Slovak University of Technology, Slovak Republic

11:00 – 11:30 COFFEE BREAK

11:30 – 12:30 SESSION 6A Room A Reconfiguration

Chair: Antonín Pleštil, ASICentrum s.r.o. (CZ) Relocation of Reconfigurable Modules on Xilinx FPGA

Tomáš Drahoňovský, Martin Rozkovec, Ondřej Novák Technical University of Liberec, Czech Republic

On Performance Estimation of a Scalable VLIW Soft-Core in XILINX FPGAs Petr Pfeifer1, Zdeněk Plíva1, Mario Schölzel2, Tobias Koal2, Heinrich T. Vierhaus2 1: Technical University of Liberec, Czech Republic; 2: Brandenburg University of Technology, Cottbus, Germany

On the Feasibility of Combining On-Line-Test and Self Repair for Logic Circuits Tobias Koa1l, Markus Ulbricht1, Piet Engelke2, Heinrich. T. Vierhaus1 1: Brandenburg University of Technology, Cottbus, Germany; 2: Infineon Technologies AG, Neubiberg, Germany

† Industrial paper

Page 8: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

WEDNESDAY APRIL 10, 2013

11:30 – 12:30 SESSION 6B Room B Emerging Technologies

Chair: Viera Stopjaková, Slovak Univ. of Technology (SK) Yield-Oriented Energy and Performance Model for Subthreshold

Circuits with V th Variations Hans Kristian Otnes Berge1, Snorre Aunet2 1: University of Oslo, Norway; 2: Norwegian University of Science and Technology, Norway

VeSFET as an Analog-Circuit Component Dominik Kasprowicz, Bartosz Swacha Warsaw University of Technology, Poland

Efficient Mixture Preparation on Digital Microfluidic Bio chips Srijan Kumar1, Sudip Roy1, Partha P. Chakrabarti1, Bhargab B. Bhattacharya2, Krishnendu Chakrabarty3 1: Indian Institute of Technology Kharagpur, India; 2: Indian Statistical Institute Kolkata, India; 3: Duke University, Durham, USA

12:30 – 13:30 EMBEDDED TUTORIAL IV Room A Chair: Heinrich T. Vierhaus, Brandenburg Univ. (DE)

Fault-based Attacks on Cryptographic Hardware Ilia Polian, Martin Kreuzer University of Passau, Germany

13:30 – 13:45 CLOSING SESSION Room A Chair: Lukáš Sekanina, Brno University of Technology (CZ)

13:45– 14:30 LUNCH Restaurant Charleston

Page 9: 2013 IEEE 16th International Symposium on Design and ... · Assertion Based Verification Using PSL-like Properties In Haskell B. N.Uchevler, Kjetil Svarstad Norwegian University of

SOCIAL EVENT

MEETING POINT: Tuesday, April 9, 2013, Hotel Lobby, 14:00 We will start with a guided walking tour through the spa town of Karlovy Vary. Please do not forget comfortable shoes!

The social event continues with the Jan Becher Museum visit starting at 16:30 (first group) and 17:00 (second group). The Museum is located at Becherplatz, a recently renovated building complex of the former Becherovka factory. After the museum visit we will have the opportunity to explore the unique atmosphere of Becherplatz.

A four-course conference dinner will start at 19:00. It will be held in Restaurant Karel IV which belongs to the Becherplatz complex. For those who are not going to enjoy an evening walk back to the DDECS hotel, we recommend to use a public transport (bus 2, 7 or 52).

Address to remember: Becherplatz, T.G. Masaryka 57, Karlovy Vary