2010 CMOS Emerging Technology Workshop, Whistler,...
Transcript of 2010 CMOS Emerging Technology Workshop, Whistler,...
![Page 1: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/1.jpg)
Edward L. Ginzton Lab, Stanford University, CA
www-kyg.stanford.edu
© M. Kupnik 21 May 2010
Mario Kupnik and Butrus T. Khuri-Yakub
2010 CMOS Emerging
Technology Workshop,
Whistler, Canada
![Page 2: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/2.jpg)
© M. Kupnik 2
Outline
Capacitive Micromachined Ultrasonic Transducers
o Background, how it works, how it’s made, and for what it can be used.
o What was done for CMOS integration so far.
Latest 2D array fabrication process (THICK-BOX)
o Research towards high-reliability CMUTS with high performance.
Integration to CMOS via low-temperature bonding.
“Substrate-less” CMUT fabrication – CMOS will help.
Conclusions and Outlook
![Page 3: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/3.jpg)
© M. Kupnik 3
The singing condensor – Historical Perspective
“After a month of careful study, during which both magnetostriction and piezoelectricity were considered and then rejected, Langevin decided that it would be safer to fall back on the “singing condenser”… (March 1915). Numerical estimates indicated that, if electric field strengths of the order of a million volts per centimeter (108 Volt per meter or 100 V per micron) could be maintained, electrostatic forces as large as a kilogram per square centimeter would (theoretically) come into play…”
![Page 4: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/4.jpg)
© M. Kupnik 4
Capacitive Transducer – The basic idea is simple
![Page 5: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/5.jpg)
© M. Kupnik 5
Capacitive Transducer – Why we need a DC bias voltage
![Page 6: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/6.jpg)
© M. Kupnik 6
The first CMUT was an air transducer (Haller, Khuri-Yakub, 1994)
The complete transducer is micromachined, i.e. also the moving part (“membrane”).
Gold Nitride
Oxide
Si
1 venting channel per
cell
Frequency range: 1.8 MHz … 4.6 MHz
3 dB fractional bandwidth: 20 %
![Page 7: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/7.jpg)
© M. Kupnik 7
CMUTs can be used for both airborne ultrasound and immersion
Equivalent Circuit Model:
Plat
e Im
peda
nce
(MR
ayl)
Frequency (MHz)
Zplate
![Page 8: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/8.jpg)
© M. Kupnik 8
Microelectronics industry gave us all tools that we needed
![Page 9: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/9.jpg)
© M. Kupnik 9
Using this technology, various devices were fabricated …
Circular cells Hexagons Tents
100 nm-thick plate 200 nm-thick plate 300 nm-thick plate Devices fabrication and photos by Prof. Arif Sanli Ergun.
![Page 10: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/10.jpg)
© M. Kupnik 10
Monolithically integrated CMUTS so far
However, CMUTs fabricated with sacrificial release process suffer from several drawbacks, in particular when low temperature processes are used.
E.g.: Non-uniformities, low reproducibility, intrinsic stress, gap height limits due to roughness, etc.
Chip-bonding after CMUT is finished is a good approach, but there are still weak points present related to sacrificial release process.
![Page 11: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/11.jpg)
© M. Kupnik 11
Let’s get the best out of the CMUT first before we think CMOS
Grow thermal oxidize on silicon wafer
Pattern oxide, this step defines cell diameter
Grow thin oxide at bottom of cavity
Perform fusion Bonding step to SOI wafer
Remove handle wafer and BOX layer
Huang, Ergun, Haeggstrom, Khuri-Yakub, Proc. of the MEMS Conference, pp.:522-525, 2003
![Page 12: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/12.jpg)
© M. Kupnik 12
Wafer-bonded CMUTs and electronics integration so far
Steve Zhuang, et al, 2009Robert Wodnicki, et al, 2009
Elvis Lin, et al, 2009
Trench-frame 2D CMUT arraysolder bumped to IC
Trench-frame CMUTssolder bumped to interposer
solder bumped to IC
This way, many arrays can form a large imaging device
![Page 13: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/13.jpg)
© M. Kupnik 13
However, this is problematic for thin-gap devices
Electrical breakdown and high parasitic capacitance
10 nm average displacement at 10 MHz in immersion translates
into 1 MPa acoustic pressure
Kupnik, Ergun, Huang, Khuri-Yakub, Proc. of the IEEE Ultras. Symp, pp.: 511-514, 2007
![Page 14: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/14.jpg)
© M. Kupnik 14
This fabrication process solves the issue and features many advantages
Kupnik and Khuri-Yakub, “A direct wafer bonded 2-D CMUT array“, US patent pending, 2008.
SOI substrate Etch horizontal gap
Etch vertical trenches
Oxidize
Bonding to SOI Thin down substrate (optional)
Etch via hole to each cell Fill via hole with
conductive material
Prepare backside for trench etch for
CMOS integration step
Etch (define) elements of 2D array
Bond to CMOS IC or PCB & remove handle
Ground connection for plate at the edge of the array
![Page 15: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/15.jpg)
© M. Kupnik 15
One of the main advantages is a high electrical breakdown voltage
CMOS IC
![Page 16: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/16.jpg)
© M. Kupnik 16
Several options how to merge CMUT wafer and CMOS wafer
?
- Under bump metallization for chip bonding (die or wafer level)
- Metal layers for eutectic bonding (Au-Si, 365°C) [13], [14]
- Metal layers for thermo compression bonding (Ti-Au, 300°C) [15]
- Low temperature fusion bonding, e.g. [16] (Mitsubishi and AML sell such tools, Ziptronix)
![Page 17: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/17.jpg)
© M. Kupnik 17
Low temperature fusion bonding is state-of-the-art:
For example: This fully-automated room-temperature bonding tool (8’’) from Mitsubishi Heavy Industries Ltd., Japan, features covalent bond strength at room temperature.
It uses ion beam surface activation technique under high vacuum condition.
![Page 18: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/18.jpg)
© M. Kupnik 18
We also pursue a second approach – substrateless CMUT, for example:
Kupnik and Khuri-Yakub, “Monolithic integrated CMUTs fabricated by low-temperature wafer bonding“, US patent pending, 2008.
![Page 19: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/19.jpg)
© M. Kupnik 19
Conclusions
Wafer-bonded CMUTs and CMOS are compatible!
Required to get the best from both worlds –
Wafer-bonded CMUTs monolithically integrated.
For large and medium size 2D arrays, this approach will allow to develop the next generation medical imaging probes and therapeutic transducers (HIFU) at low cost without expensive and complex interposer solutions.
At the moment we pursue research for direct monolithic CMUT integration on top of a CMOS-circuitry-containing substrate, i.e. CMOS wafer acts as substrate for a wafer-bonded CMUT fabrication process.
![Page 20: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/20.jpg)
© M. Kupnik 20
References [1] P.-C. Eccardt, et al, ”Surface micromachined ultrasound transducer in CMOS technology," Proc. Ultrason. Symp., pp.: 959-962,
1996. [2] P.-C. Eccardt and K. Niederer, ”Micromachined ultrasound transducers with improved coupling factors from a CMOS compatible
process," Ultrasonics, vol. 38, pp.: 774-780, 2000. [3] R. A. Noble, et al, ”A cost-effective and manufacturable route to the fabrication of high-density 2D micromachined ultrasonic
transducer arrays and (CMOS) signal conditioning electronics on the same silicon substrate,” Proc. Ultrason. Symp., pp.: 941-945, 2001.
[4] R. A. Noble, et al, ”Low-temperature micromachined CMUTs with fully-integrated analogue front-end electronics," Proc. Ultrason. Symp., pp.: 1045-1050, 2002.
[5] C. Daft, et al, ”Microfabricated ultrasonic transducers monolithically integrated with high voltage electronics," Proc. Ultrason. Symp., pp.: 493-496, 2004.
[6] G. Gurun, et al, ”Front-end CMOS electronics for monolithic integration with CMUT arrays: circuit design and initial experimental results," Proc. Ultrason. Symp., pp.: 390-393, 2008.
[7] J. Zahorian, et al, ”Single chip CMUT arrays with integrated CMOS electronics: fabrication process development and experimental results," Proc. Ultrason. Symp., pp.: 386-389, 2008.
[8] M. Kupnik and B. T. Khuri-Yakub, "A direct wafer bonded 2-D CMUT array," US patent pending. [9] M. Kupnik and B. T. Khuri-Yakub, "High-temperature electrostatic transducer and fabrication method," US patent pend. [10] M. Kupnik, et al, ”CMUT fabrication based on a thick buried oxide layer," submitted to Proc. Ultrason. Symp., San Diego, 2010. [11] M. Kupnik and B. T. Khuri-Yakub, "Monolithic integrated CMUTs fabricated by low-temperature wafer bonding," US patent pend. [12] Y. Tsuji, et al, ”Low-temperature process for CMUT fabrication with wafer bonding technique," submitted to Proc. Ultrason. Symp.,
San Diego, 2010. [13] R. F. Wolffenbuttel and K. D. Wise, "Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature," Sensors
and Actuators A, vol. 43,pp.: 223-229, 1994. [14] J. A. Dziuban, "Bonding in microsystem technology," Springer, 2006 [15] C. H. Tsau, et al, "Fabrication of waver-level thermocompression bonds," Journal of Microelectromechanical Systems,vol. 11, no.
6, pp.: 641-647, 2002. [16] T. Rogers and N. Aitken, "Low temperature bonding using in-situ radical activation," available online at http://www.aml.co.uk/
publications.htm. [17] Q.-Y. Tong, "Method of room temperature covalent bonding," US patent10440.099, 2004. [18] G. Kovacs, et al, "Bulk micromachining of silicon," Proc. of the IEEE, vol. 86, no. 8, 1998. [19] L. A. Donahue, et al, "Development in Si and SiO2 etching for MEMS-based optical applications,” Proc. of SPIE, vol. 5347, pp.:
44-53. [20] R. Wodnicki, et al, ”Multi-Row Linear CMUT Array Using CMUTs and Multiplexing Electronics," Proc. Ultrason. Symp., pp.:
2696-2699, 2009. [21] X. Zhuang, et al, ” Wafer-Bonded 2-D CMUT Arrays Incorporating Through-Wafer Trench-Isolated Interconnects with a
Supporting Frame," TUFFC, pp.: 182-192, 2009. [22] E. Lin, et al, ” PACKAGING OF LARGE AND LOW-PITCH SIZE 2D ULTRASONIC TRANSDUCER ARRAYS," MEMS conference, pp.:
508-511, 2010.
![Page 21: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/21.jpg)
© M. Kupnik 21
Acknowledgements
Srikant Vaithilingam, Stanford University
Kazutoshi Torashima, Canon Inc.
Ira O. Wygant, National Semiconductor
Yukihide Tsuji, NEC Inc.
Michael Cernusca, AVL List GmbH
Kudlaty Katarzyna, AVL List GmbH
Steve Vargo, SPP Process Technology Systems, Inc.
This reserch was funded by following research partners:
(in alphabetical order)
AVL List GmbH, Graz, Austria
Canon Inc., Tokyo, Japan
![Page 22: 2010 CMOS Emerging Technology Workshop, Whistler, Canadastanford.edu/group/khuri-yakub/publications/10_kupnik.pdf · 2010 CMOS Emerging Technology Workshop, Whistler, Canada © M.](https://reader031.fdocuments.us/reader031/viewer/2022013014/5ae7a0937f8b9a6d4f8e6235/html5/thumbnails/22.jpg)
© M. Kupnik 22
Thank you and for more information feel free to contact us
Visit: www-kyg.stanford.edu
Butrus (Pierre) T. Khuri-Yakub Professor
E. L. Ginzton Laboratory, room 11 Stanford University Stanford, CA 94305-4088 Office: +1-650-723-0718 [email protected]
Mario Kupnik Senior Research Scientist
E. L. Ginzton Laboratory, room 49 Stanford University Stanford, CA 94305-4088 Office: +1-650-725-4942 [email protected]