2007 Sept. 18SYSC 2001* - Fall 2007. SYSC2001-Ch2and3.ppt1 ITBB – Structure...

2007 Sept. 18 SYSC 2001* - Fall 2007. SYSC2001-Ch2and3.ppt 1

ITBB – Structure

Processor Memory Input/Output

Bus

device

device

.

.

.

Processor executes instructions

Memory stores information (data & instructions)

I/O moves data in/out of computer

Bus interconnects other components and supports interactions between them


ITBB: Fundamental Binary Assumption

all information is binary encoded

• result of transistor technology

• one bit = one binary digit value either 0 or 1

• one Byte = 8 bits grouped together b7b6b5b4b3b2b1b0

e.g. 100111012 vs. 1001110110

• one word = machine dependent number of bits

information includes data and instructions!

indicates base of number lsbmsb

case!


Encoding (Representing) Data Using Binary Values

counting numbers see Assignment 1

integers (format defacto standard)

floating point (IEEE standard)

characters (ASCII, Unicode)

boolean

days of the week

colours

other ???

later – Ch. 9

later – assembly language

application / implementation dependent ( SYSC 2003 )


use some bits to encode operation opcode

use some bits to encode operands (if present)

for now, assume fixed number of bits ( w ) per instruction

• fixed number of bits ( i ) used for opcode

• fixed number of bits ( j ) used for operand(s)

Encoding (Representing) Instructions Using Binary Values

opcode operands

i bits j bits

w bits


ITBB Function

Recall functions in a computer:

• Data PROCESSING

• Data STORAGE

• Data MOVEMENT

• CONTROL

now we consider each component in terms of these functions and the roles of the components in the structure

Functionlecture 2


Processor ( a.k.a. CPU)

PROCESSING arithmetic and logic unit ( ALU )

• manipulates/changes/combines/calculates data values

STORAGE registers hold values in CPU

• each register has a unique name

CONTROL control unit

• built-in instruction cycle engine that drives machine

• instruction cycle drives control to memory and I/O components when appropriate !

CPU = Central Processing Unit


Processor Structure

MOVEMENT

• internal connections (control unit, ALU and registers)

• external Bus connections to other components

ALU RegistersControl

Unit

internal connections

CPU

external Bus connections


Processor Instruction Cycle

START

fetch instruction( from memory )

execute the instruction

HALT

cycle

may cause more memory

accesses (for operands)


Memory ( 1 )

STORAGE

• fixed width locations (or cells)

• each location contains information

– contents: the value stored in the location

– address: unique “name” for each location

MOVEMENT

• internal connections

• external bus connections

memory does not differentiate contents as instructions vs. data

( its all just binary values )

IMPORTANT SLIDE !

e.g. house numbers


Memory ( 2 ) PROCESSING (limited processing compared to CPU)

• refresh? transistor technology

• bit-level error checking? error correction ?

CONTROL (of memory actions)

• write – copy input value as new contents of a location

• read – output (but do not modify) contents of a location

• write / read driven from “outside” (e.g. processor, other ?)

• may provide external control error condition?

Ch. 5

later


Memory Structure

memory processor

locationsControl

Unit


Memory



Input Output ( 1 )

function depends on connected devices

STORAGE fixed width registers (or ports)

• each register contains information

– contents: the value stored in the register

– address: unique “name” for each register

MOVEMENT

• internal connections

• external bus connections


Input Output ( 2 )

PROCESSING

• device dependent ! specialized hardware

CONTROL (of device-related processing)

• write – copy input value as new contents of a port

• read – output contents of a port

• not always the case that can read & write a port !

• write / read driven from “outside” (e.g. processor, other)

• may drive external control interrupts !

Ch. 7


Input Output Structure

N. B. I/O component = Memory !

device processor

registers( ports )

Control Unit


I/O


device


Bus

pathway for interactions among components

standard signaling protocols for using the Bus

• specified using timing diagrams

MOVEMENT YES!

CONTROL arbitration (traffic cop)

• resolve concurrent requests to use the Bus

STORAGE not usually

PROCESSING not usually

Appendix 3A

sometimes … arbiter


Putting ITBB Together - A “Simplified IAS-like” Example ( sIAS )

Want an example to show simple instruction execution

need details for:

• sIAS memory: locations

• sIAS processor: instructions, registers, instruction cycle

further simplification: assume decimal (instead of binary or hexadecimal) values

this example ignores: bus protocols, I/O, control details

See IAS Ch. 2.1, IAS-like, “Hypothetical” Ch 3.1, 3.2


sIAS Memory

location

contents: store 4-digit decimal values

address: a 3-digit decimal value

• since each address is unique

total address space = 1000

Memory

address contents

000 1234 001 9075 002 6386

. . . . . .

997 3180 998 6724 999 9932

largest possible number of locations


sIAS Processor – Registers ALL reg’s hold 4 digit decimal

values

PC: address of next instruction to fetch

IR: holding register for instruction after fetch

AC: data register “accumulator”

MAR: memory address register

MBR: memory buffer register

CPU Registers

825

2001

0000

0024

2001

PC

IR

AC

MAR

MBR


1. Fetch Instruction

MAR PC // set up address for fetch

MBR Mem[ MAR ] // fetch instruction

IR MBR // save instruction

PC PC + 1 // set up for next fetch

2. Execute instruction in IR may involve memory access

sIAS Instruction Cycle

means “gets loaded with”

built-in sequential execution of instructions!!


4-digit Encodings Operation

1xxx Load AC value from memory address xxx

2xxx Store AC value to memory address xxx

3xxx Add contents of memory address xxx to AC

= opcode encoding

= operand encoding

Example instructions: 1376 2378 3379

• if executed, what effect would these have on the CPU and memory?

sIAS Processor – Instructions


Memoryaddress contents

224 1826 225 1827 226 3828 227 2828

826 9999 827 0001 828 0009 829 0000

Consider Example sIAS State

CPU Registers

0225

1826

9999

0826

2001

PC

IR

AC

MAR

MBR

. . . . . .

. . . . . .

. . . . . .


1st Instruction Cycle Iteration – Fetch

1. Fetch

a) MAR 0225 PC

b) MBR 1827 Mem[ 0225 ]

c) IR 1827 MBR

d) PC 0226 PC + 1

instruction fetched: 1827

Load AC value from memory address 827


1st Instruction Cycle Iteration – Execute

execute instruction in IR: 1827

Load AC value from memory address 827

a) MAR 0827 from IR

b) MBR 0001 Mem[ 827 ]

c) AC 0001 from MBR


2nd Instruction Cycle Iteration – Fetch

1. Fetch

a) MAR 0226 PC

b) MBR 3828 Mem[0226]

c) IR 3828 MBR

d) PC 0227 PC + 1


Add contents from memory address 828 to AC

Memoryaddress contents

224 1826 225 1827 226 3828 227 2828

826 9999 827 0001 828 0009 829 0000


2nd Instruction Cycle Iteration – Execute


Add value from memory address 828 to AC

a) MAR 0828 from IR

b) MBR 0009 Mem[ 828 ]

c) AC 0010 AC + MBR


3rd Instruction Cycle Iteration – Fetch

1. Fetch

a) MAR 0227 PC

b) MBR 2828 Mem[ 0227 ]

c) IR 2828 MBR

d) PC 0228 PC + 1


Store AC value to memory address 828


3rd Instruction Cycle Iteration – Execute


Store AC value into location at address 828

a) MAR 0828 from IR

b) MBR 0010 AC

c) Mem[ 828 ] 0010 MBR


Instruction Cycle - State Diagram

access

to

memory

no operands


Interrupts Mechanism to interrupt normal sequence of processing

Why?

• I/O events: e.g. mouse click, network data arrives

• timer: e.g. animation

• program exception: e.g. overflow, division by zero

• hardware error: e.g. memory error

these are asynchronous events! require programmed service

events caused by hardware, not software instructions

Ch. 7.4

Unpredictable timing


An Interrupt Scenario

App. code

interrupthandler

(a.k.a. ISR)“driver”?independent

execution contexts“threads of control”

ISR = Interrupt Service Routine

performs s/w action appropriate to interrupt event

Suppose App. code executing:

• interrupt occurs

• want ISR to run

• then resume App. eg. editor

eg. audio

CD

want toshare processor between threads!


resume thread @ i+1hardware invokes interrupt handler

Transfer of Control via Interrupts

App. code

interrupthandler

suspend thread !

interrupt occursduring execution of

instruction at i1

2

3

4

5

6


after instruction execute phase of cycle – processor checks:

• exception occurred? e.g. divide by 0

• interrupt event signal input to processor?

If interrupt pending:

• Suspend and save context of current thread of execution

• Set PC to start address of ISR

• Continue Cycle fetch 1st instruction of ISR code

Eventually, ISR s/w restores context resume interrupted thread

If no interrupt pending: Continue Cycle fetch next instruction

Extending Instruction Cycle for Interrupts

done by processor h/w – no s/w !


Extending Processor Instruction Cycle

START

fetch instruction

execute instruction

HALT

cycle

interrupt pending

no

save context & set PC to start addressof interrupt

handler

yes

hmmmm….. last3 slides all say the same thing


Digital Signaling

signals are indicated as voltage levels

• use particular levels to represent binary values

– e.g. +5 volts 1

0 volts 0

• change values “quickly”

1

0time

want to avoid reading when

not stablesignals stable

Signals: “here is the data”, “read the contents of this

address”, “I want to use the bus”, etc.

Or could be –5V, 0V or…?


Signals and Timing Diagrams

often bundle groups of related signals as one in a timing diagram

e.g. 16-bit addresses 16 address signals one per bit

1

0

falling (trailing) edgerising (leading) edge

1

0address

signals may be stable, but do not represent a useful value

signals stable, represent a useful 16-bit address

App. 3A

~ ~

indefinite time elapsed


Bus

communication pathway connecting components

shared communications broadcast to all on bus

organize communicated information into 3 groups:

• address

• data

• control

of information being communicated

everything else


Bus Interconnection Scheme

memory I/O


Data Bus

carries data

• remember that there is no difference between “data” and “instruction” at this level

data bus width is a key determinant of performance

• 8, 16, 32, 64 bit


Address bus

identify the source or destination of data

• e.g. CPU needs to read an instruction (data) from a given location in memory

address bus width determines maximum memory capacity of system (address space)

• e.g. 8080 has 16 bit address bus giving 64k address space

216


Address and Data Groups

often bundle address and data signals separately and use different physical pathways

may multiplex using same physical pathway

1

0address

1

0data

1

0address data


Some Common Control Signals

reset – force all components to reset

clock(s) to synchronize communication

destination indicator – usually memory or I/O

acknowledgment from component – info received

interrupts

arbitration“hand shake”


Bus Protocols signaling and sequencing to permit interactions between

components

• processor puts address value on bus, and “memory read” control indication

• memory receives read signal, reads address, gets appropriate data, puts data on bus

• processor waits, then reads data from bus

May be

• Synchronous - synchronized by a clock – organize protocol by clock “ticks” Ti

• Asynchronous – no pacing by a shared clock

e.g. memory read


T1

stable data

E.G. Synchronous Memory Read

T2 T3

clock

addrs stable address

mem read

data

T1 initiate memory read (addrs, mem read)

T2 time for memory to do internal work

T3 data ready for reading from bus

Assumption:Sensing of bus signals done during clock trailing edge


E.G. Asynchronous Memory Write

no shared clock pacing the protocol mem write command

proc

esso

r

memory


Single Bus Problems

lots of devices on one bus leads to:

• propagation delays

– long data paths mean that co-ordination of bus use can adversely affect performance

– if aggregate data transfer approaches bus capacity

most systems use multiple buses to overcome these problems

evolution for performance!


Traditional bus (with cache)

I/O

Memory

Processor Cache: Remembers data from previous requests.

Can processor request be answered from cache?

If not pass request on via system bus

Ch. 4

•aka Front side bus


High Performance Bus

slowerdevices

fasterdevicesFireWire


PCI Bus

Peripheral Component Interconnection Bus

Intel released to public domain

32 or (optional) 64 bit address/data bus

49 mandatory lines

Note: 64 data lines @ 66 Mhz = 528 MBps = 4.2 Gbps

synchronous

• read bus on rising clock

• modify bus on falling clockrules for use !


PCI Bus Lines (required) System lines

• including clock and reset

Address & Data (AD)

• 32 lines each: multiplexed

• interrupt & validate lines

Interface Control

• C / BE – command / byte enable: multiplexed

Arbitration

Error lines more optional lines too!

text: table 3.3


PCI Commands

overview of a transaction between initiator (master) and target, e.g. CPU initiates a read from memory

1. master claims bus arbitration & wait for idle

2. specify type of transaction e.g. I/O read/write

3. address phase ( address & command )

4. one or more data phases ( data & byte enable)


PCI Read Timing Diagram

•read bus on rising clock

•modify bus on falling clock


Some(!) PCI Signals – refer to text pg 87-88

xxx# - signal's active state occurs at low voltage

Frame# - Driven by current master to indicate the start and duration of a transaction.

Devsel# - device select. Asserted by target when it has recognized its address

C/BE[3::0]# - Multiplexed bus command and byte enable signals. During the data phase the lines indicate which of the four byte lanes carry meaningful data.


Some(!) PCI Signals -- refer to text pg 82-3

IRDY# - Initiator Ready. Driven by the current bus master. During a read indicates that initiator is ready to accept data. During write, indicates that valid data are on AD.

TRDY# - Target Ready. Driven by target. During a read indicates that valid data are on AD. During write, indicates that target is ready to accept data


PCI Bus Arbitration

idle

2007 Sept. 18SYSC 2001* - Fall 2007. SYSC2001-Ch2and3.ppt1 ITBB – Structure...

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