2001 April Cmoc

8/3/2019 2001 April Cmoc

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Photobit

CMOS Image Sensors

Dr. Eric R. FossumPhotobit Technology Corporation

Pasadena, California

[email protected]

© 2001 Photobit Technology Corporation Rev 1

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Photobit

Timing &r ver

Circuits

DetectorPixelArray

Analog Signal ProcessorAnalog to Digital Converter

ASP

ADC

© 2001 Photobit Technology Corporation

Digital Signal Processor

DSP

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Photobit CMOS Image Sensor

- - -

CMOS Active Pixel Color Imaging ArrayDigital Logic for

• User Interface

• Sensor Setup

• Timing Generator• Digital Signal

– Color Processing

– White Balance – Image Enhancement

• Data OutputFormatting

na og gnaProcessing

• Data Sampling

• Noise Reduction


• Gain Analog-To-Digital Conversion

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Photobit CMOS Image Sensor

•On-chip timing and control circuits•On-chi analo si nal rocessin

•Correlated double sampling•Local neighborhood image processing••Compression preprocessing

•Pixel defect correction••Window readout for electronic pan/tilt•Skip-mode for low resolution readout

• - - -•High speed digital output•On-chip DSP and digital sensor control


, . , . …•Easier interface, easier board design

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Photobit

Vpd

Cpd

Ipd

Vssvoltage


time

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Photobit

• Each pixel gets covered by a colored filter

– e use re , green, ue - es ma c or

displays in “Bayer” pattern

– Could use complementary colors (cyan, yellow, magenta)

1

0.4

0.5

0.6

0.7

0.8

.

e r e s p o n s e

Silicon

0

0.1

0.20.3

400 500 600 700 800 900 1000 1100

R e l a t i


Wa velength (nm)

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Photobit

• A pixel is divided into a sensing portion and a readoutpor on

• Fill factor is the ratio of sensing area to total area and istypically about 20% for CCDs and CMOS APS

Total pixel area

Sensitive area


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Photobit

• Microlenses funnel li ht awa from non-sensitive ortions of

pixel

Color filter layerMetal opaque layer

Photodiode

Silicon substrate


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Photobit

• Ke to Inte rated Ima in S stem camera on a chi is

making a good pixel in a CMOS platform process.• Prior to CMOS active pixel was CMOS passive pixel.

• Simple and DRAM-like

• Not such a good pixelue o g rea no se

• Gets worse with smallixels lar e arra s and

M1RS

Vpd

CpdIpd

faster readoutVss


Vout

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Photobit

• Add an am lifier inside each ixel.

• Not so obvious: – Reduces fill factor due to 3 transistors

– Adds fixed pattern noise due to offset variations in

each amplifier’ –

CCDs were invented.

• Non-CMOS active ixel sensors were demonstrated b

Olympus, Toshiba, Texas Instruments and others butsuffer from requiring a unique semiconductor fabrication


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Photobit

• CMOS state of the art is ripe for image sensors

–

– Defects and contamination well controlled – Threshold voltages stable and fairly uniform

– And now foundries offer specialized image sensor modules

• Customers demand low power, miniaturized systems-on-a-chip

• Circuit techniques developed for high performance

– Active pixel provides gain in pixel and lower noise

– Use of double-correlated sampling and double-delta sampling on-chi removes tem oral & fixed attern noise

– Column parallel architecture permits low analog bandwidths toreduce noise and artifacts and maintain high frame rate.

–


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Photobit

100

10

Im age SensorPixel Size

CCD Invente d

S i z

e ( u m )

PracticalO tical Lim it

1CMOS

Feature Size

0.11970 1975 1980 1985 1990 1995 2000 2005

Year


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Photobit

20

14

16

18

Cheap Lens Resolution(30 lp/mm)

10

12

( m

i c r o n s )

Airy Disk Diameter=

4

6

8

S i z e

.

F/2.8

0

2

400 500 600 700 800 900 1000 1100

(120 lp/mm)

B G RB G R


Wavelength (nm)

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Photobit

Quantum Efficiency of PB-0100 Rev. C

20

Blue pixels

Green pixels

Red ixels

10

15

f i c i e n c y ,

%

5

Q u a n t u m

E

300 400 500 600 700 800 900 1000 1100

0


ave engt , nm

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Photobit

• PN junction photodiode (PD)

• RST switch M1 charges PD to

Vpix• Light-generated current Ipd M2

M1RST

ColBus

Vpix

• Voltage Vpd on PD is gatevoltage of in-pixel source-follower transistor M1.

Vpd

Cpd

• Row Select (RS) switch M3connects pixel transistor tocolumn bus and charges bus to

RSp

Vss

same vo tage as .• Voltage Vout picked off at

bottom of column.

Vout

IL


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Photobit Physical Layout of

PD V D D

L B U S

PHOTODIODE

PD

PD

PD

C O

P

D

P

D

P

D

RESET

M1 RST

ROW

M2 SF

SELECT M3 RS PD

PD

PD


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Photobit

“Correlated” Double Sam lin

Photodiode Voltage

integration starts pixel reset level sampled

2V

signal sampled

0V

1V

ms ms

Pixel sampled twice to remove variations inthreshold volta e of ixel source follower and


reset level.

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Photobit

VDDPIXEL

RST

COL BUS

RS

CS GLOBAL

SHS

SHR

SIG

HOR BUS

VLP

RSTVLN


PER COLUMN

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Photobit

ReadRead

ResetReset

Read

Reset

Row 1 Row 2 Row 3

2V

3V

1V


0V

33 ms 66 ms

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Photobit X-ray Sensor for Dental and

Osteo orosis A lications

• Total chi size: 37 x27 mm

• 900 (V) x 675 (H)elements

• μ • 2 μm CMOS process• Differential analog

output• On-chip timing and

control• Perhaps world’s

production


Xue 1998

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Photobit Mammography Sensor

(3-Sides Buttable)

• x e ements• 30 μm pixel pitch• 0.8 μm process

• 3-sides buttable• P-channel PD-type pixel• Differential analog output


• co umn oss

Xue 1997

• Some on-chip circuits

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Photobit

• Passive Pixel Sensor (PPS)

– o o o e

– Charge injection

– Photodiode (dates to 1968)

– Photo ate invented at JPL

– Pinned Photodiode (invented by JPL/Kodak)

– Floating gate (invented at JPL)

– Logarithmic (high dynamic range - low contrast) – Freeze-Frame (Photobit)


– More complex amplifiers (from DoD infrared imagers)

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Photobit

• 3 transistors per pixel

• Great QE• Logarithmic response -- good

VDD

range

• Poor contrast under flatg ng

• Log-response makes colorprocessing extremely

RS

comp ex• Susceptible to FPN• Slow response under low light COL BUS


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Photobit

• 4 transistor ixel VDD

• More complex fabrication• Susceptible to lag• Great QE

RST

• Low noise• Good scaling for large arrays•

TX

• First demonstrated by JPL/Kodak PPD

COL BUS


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Photobit

Photo ate Active Pixel


• Larger pixel• QE loss due to poly gate RST

• Lowest noise

– 5 e- rmsPG TX

• Good scaling for large arrays

• Good scaling for fast arrays

. , ,

COL BUS


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Photobit

-

•

• Permits on-chip DSP for camera control, colorinterpolation, etc.

• Suppresses noise pick up from EMI, crosstalk

• Simplifies interface• Permits faster readout

• Can reduce overall chip and/or system power


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Photobit

On-Chi ADC Choices

• One (or two or three) • Single-slope

– High data raterequirement (5-60

– slow

• Successiveapproximation

– Local high power

dissipation

– 8-10 b max

• Algorithmic

– needs ood o -am• ne per p xe

– Large pixels and low fillfactor

• Oversampled

– Filter takes lots of

• One ADC per column(column-parallel)

– Tall, skinny ADCs

• Flash and Folding

– More power


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Photobit

-

Digitizedin pixel Serial ADC(s)

at data rate Columnparallel

Columnparallel

ADCsMultiplexed

output

ADCsParallel

output ports


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Photobit

-

• Internet cameras, games

• 360x304 352x288 effective ixels

• 8b flash ADC

• 7.9 μm x 7.9 μm (1/5” optical format)

• Pro ressive scan window readout

• 15,000 gate on-chip logic

• >30 frames per sec (adj.)

• 3.3 V o eration

• <100 mW total power

• Built-in autoexposure control

• On-chi biasin

• On-chip CFA

• >20 dB SNR @ 1 lux, 30 fps


Van Blerkom, Huang, Chan 1999

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Photobit

-

• Dual mode cameras, internet cameras

• 640x487 640x480 effective ixels

• 320 column-parallel 8b ADCs

• 7.9 μm x 7.9 μm (1/3” optical format)

• Pro ressive scan window readout

• 15,000+ gate on-chip logic

• >30 frames per sec (adj.)

• 5 V o eration

• <300 mW total power

• Built-in autoexposure control

• On-chi biasin

• On-chip CFA

• >20 dB SNR @ 1 lux, 30 fps


Panicacci, Cho 1999

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Photobit Example:

• Digital stillcameras

• 2 Mpixels

• 3.9 um ixel pitch

• Microlenses


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Photobit Major Advantages of CMOS Image

• Lower power

– ower supp y vo ages , . , . , ….

– Integration reduces parasitics – Clever mixed si nal desi n and di ital si nal rocessin

• Increased functionality

– Increased integration on chip and smaller form factor – Higher dynamic range, better image quality

– Smart digital signal processing and local sensor control

•

– High throughput with on-chip ADC and digital output

• Lower system cost


– Fewer system components, lower wafer costs

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Photobit 3-Pin Self-Clocked Micropower

Camera on a Chi

• World’s lowest power camera- Timing andon-a-chip

• Portable electronics such asPDAs, cell phones, games

control logic8b ADC

• QCIF format

• 0.35 um process technology

•

176x144

5 um pixels

• 550 uW total power

• Watch battery operation

• n-c p c oc• On-chip 8b ADC

• 1.5 volt operation

Analog signalprocessor


• Serial digital data output30 fps output

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Photobit

• Pixel Format: 256 X 256

. .

• xe ze: µm µm

• Frame Rate: 2 fps

• ADC: On-Chip, 8 bits

View inside smallintestine


• ower upp y:2.8

• Power: 3 mW

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Photobit Ultra-High Intrascene Dynamic

Ran e Sensor for Automotive

High SensitivityAny one 8b image does not coverfull intrascene dynamic range:

Output 8b

ynam c mapp ngASPADCs

Logic

• Proprietary pixel design allows very high

• Preserves contrast unlike logarithmicsensors

• Low susce tibilit to FPN com ared to


logarithmic sensors

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Photobit High Speed Linear Sensor

• 4096 x 1 linear array

• 7 um pixel pitch (28 mm long)

-

• 4 analog output ports, each 40 MHz

• 160 Mpix/sec total output rate

• 35,000 lines/sec• 5 V operation

• Subwindowing allowed, from center


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Photobit

• 1000 dpi scan density

• > 9 V / lux-sec• 10b ADC

• <150 mW operation

• on-chi FIFO buffer

• 40 Mbytes/s readout rate• SPI compatible serial interface


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Photobit SmartBeamTM

• Pseudo-random accessreadout

• High sensitivity photogate

pixels• 8b ADC

• SPI interface


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Photobit

• x array

• Photodiode-type pixel withradiation tolerant readoutc rcu try

• 1 MHz analog output

• Individual pixel resetcircuitry for ultra highdynamic rangemanagement

• Initial results shows sensorstill working after 30Mrads


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Photobit 1024x1024 (1.0 Mpix), 500 fps ERS

• 1024x1024 elements

• 0.5 μm CMOS• 1024 on-chip 8b ADCs

• 8x8b digital output (64 pins)

• Open architecture

• 3.3 volt operation• Power: 95 mW @ 60 fps

• Power: 450 mW @ 500 fps

• -


Krymski, Van Blerkom, Bock, Anderson 1998

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Photobit PBMV40 (in development)2352x1728 4.1M ix 240f s ERS

• 4.1 Mpixel sensor• 7 μm x 7 μm pixel pitch• 16x10b digital output• 240 fps ERS• y es sec a z• 4000 bits/lx-sec• 3.3 volt operation


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Photobit Shuttered Node Active Pixel


• Larger pixel

• QE loss due to poly gateRST

across all pixels (freeze-motion)

• Shutter efficiency issue PG TXSH

COL BUS


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Photobit

Shutter closed Shutter open

1 frame period (Tperiod)

timeTopen

Ideal: Signal = Topen / Tperiod Signal0

= open per o0

-ε 0where ε is the shutter efficiency


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Photobit

• Proprietary Photobittechnology, 5-T pixel

• Normal photodiode

• Si nal transferred to

Col

storage node in N-well

• Stora e node read RSRGRP TXout in usual way

• Diffusinghotoelectrons do not -

n+

affect storage• Very high shutter

efficienc >99.9%


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Photobit 1280x1024 (1.3Mpix) 600fps

• 1.3 Mpixel sensor

•

• 0.35 μm CMOS

• High efficiency (>99.9%) freezeframe shutter

• Shutter speeds from 1/30th to1/100,000th sec

• 10x10b digital output (100 pins)

Color image withrotating fan

1/605 sec=1652 usecRolling shutter

• Open architecture

• 3.3 volt operation

• Power: <500 mW @500 fps

• 1000 bits/lx-s• Color or monochrome


1/33,000 sec = 30 usec

Freeze frame shutter

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Photobit Discussion

r m a n c

CCDs

s

t / P e r f

APS

s t e m

C

S


2001 April Cmoc

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