Chapter 4 Algorithmic State Machines and Finite State Machines
20 Basic Finite State Machines
-
Upload
ashish-kumar -
Category
Documents
-
view
227 -
download
0
Transcript of 20 Basic Finite State Machines
-
7/28/2019 20 Basic Finite State Machines
1/39
Basic Finite State Machines 1
Basic Finite State Machines
-
7/28/2019 20 Basic Finite State Machines
2/39
Basic Finite State Machines 2
Finite State Machines
Binary encoded state machines The number of flip-flops is the smallest number
m such that 2m n, where n is the number of
states in the machine.
Next state logic equations are dependent on all
of the flip-flops in the implementation. Natural
for CPLDs, where CPLDs have high fan-in
logic gates. There may be unused states.
-
7/28/2019 20 Basic Finite State Machines
3/39
Basic Finite State Machines 3
Finite State Machines
Gray encoded state machines Similar to binary encoded state machines.
State sequence has the property that only one
output changes when sequencing betweenstates.
Can have lower power
Can be asynchronously sampled in some
systems.
There may be unused states.
-
7/28/2019 20 Basic Finite State Machines
4/39
Basic Finite State Machines 4
Finite State Machines
One-Hot Finite State Machines One flip-flop for each state in the machine
Normal operation has exactly one flip-flop set;
all other flip-flops reset.
Next state logic equations for each flip-flop
depend solely on a single state (flip-flop) and
external inputs.
Natural for FPGAs, which dont have high fan-in logic gates and an abundance of flip-flops.]
There will be unused states
-
7/28/2019 20 Basic Finite State Machines
5/39
Basic Finite State Machines 5
Finite State Machines
Modified One-Hot Finite State Machines n-1 flip-flops for an n-state machine
Normal operation has zero or one flip-flop set
The all zeros state is a legitimate state There will be unused states
-
7/28/2019 20 Basic Finite State Machines
6/39
Basic Finite State Machines 6
Finite State Machines
Linear Feedback Shift Register (LFSR) The number of flip-flops is the smallest number
m such that 2m n, where n is the number of
states in the machine.
Shift register with XOR feedback
Maximal length shift registers can have 2m-1
states.
Can modify the circuit to support 2m states.
-
7/28/2019 20 Basic Finite State Machines
7/39Basic Finite State Machines 7
Finite State Machines
Example Linear Feedback Shift Register
Two or four taps
-
7/28/2019 20 Basic Finite State Machines
8/39Basic Finite State Machines 8
Finite State Machines
Johnson Ring Counter Also called twisted-ring or Mobius counter
For n flip-flops, it will have 2n states.
Shift register with inverted feedback Unmodified, it will have unused states
Can modify the circuit to support 2n-1 states.
-
7/28/2019 20 Basic Finite State Machines
9/39Basic Finite State Machines 9
Number of States
0 10 20 30 40 50
NumberofFlip-F
lops
0
10
20
30
40
50
Binary of Gray Code
One Hot Coding
Modified One Hot Coding
EncodingEfficiency:
Binary vs. One Hot
-
7/28/2019 20 Basic Finite State Machines
10/39Basic Finite State Machines 10
Finite State Machines
CAE Tools - Synthesizers
Generates logic to implement a function,
guided by the user.
Typically does not generate logic for eitherfault detection or correction, important for
military and aerospace applications.
-
7/28/2019 20 Basic Finite State Machines
11/39Basic Finite State Machines 11
Finite State Machines
Lockup State
A state or sequence of states outside the normal
flow of the FSM that do not lead back to a legalstate.
-
7/28/2019 20 Basic Finite State Machines
12/39Basic Finite State Machines 12
Lockup StatesSample State Machine
HomePing
One
Two
Three
Reset
-
7/28/2019 20 Basic Finite State Machines
13/39Basic Finite State Machines 13
Library IEEE; Use IEEE.Std_Logic_1164.All;
Entity Onehot_Simple_Act Is
Port ( Clk : In Std_Logic;
Reset : In Std_Logic;
Ping : Out Std_Logic );
End Onehot_Simple_Act;
Library IEEE; Use IEEE.Std_Logic_1164.All;Architecture Onehot_Simple_Act of Onehot_Simple_Act Is
Type StateType Is ( Home, One, Two, Three );
Signal State : Statetype;
Begin
M: Process ( Clk, Reset )
Begin
If ( Reset = '1' )
Then State State State State State
-
7/28/2019 20 Basic Finite State Machines
14/39
Basic Finite State Machines 14
Lockup StatesA Synthesized One-Hot Implementation
Typical ring counter with lockup states was synthesized.
-
7/28/2019 20 Basic Finite State Machines
15/39
Basic Finite State Machines 15
Lockup StatesAnother Synthesized One-Hot
Implementation
Note: Results depend on version of synthesis software.
This circuit was synthesized with the same product used in
the previous slide. Note this is a modified one-hot FSM.
-
7/28/2019 20 Basic Finite State Machines
16/39
Basic Finite State Machines 16
Modified one-hot state machine (reset logic omitted) for a 4-state, two-
phase, non-overlapping clock generator. A NOR of all flip-flop
outputs and the home state being encoded as the zero vector adds
robustness. Standard one-hot state machines [Q3 would be tied to the
input of the first flip] have 1 flip-flop per state, with exactly one flip-
flop set per state, presenting a non-recoverable SEU hazard.
Lockup StatesYet Another Synthesized One-Hot
Implementation (free product)
-
7/28/2019 20 Basic Finite State Machines
17/39
Basic Finite State Machines 17
Lockup StatesA Safe One-Hot Implementation
(Synthesized)
Reset flip-flops. Note second one is on falling edge
of the clock. This implementation uses 6 flip-flops.
-
7/28/2019 20 Basic Finite State Machines
18/39
Basic Finite State Machines 18
Lockup StatesA Safe One-Hot Implementation
(Synthesized)
Reset flip-flops. Note second one is on falling edge
of the clock. This implementation uses 6 flip-flops.
-
7/28/2019 20 Basic Finite State Machines
19/39
Basic Finite State Machines 19
Lockup States - Binary Encoding
Home
Ping
One
Two Three
Four
Three unused states.
(Five, Six, Seven)
-
7/28/2019 20 Basic Finite State Machines
20/39
Basic Finite State Machines 20
Lockup StatesBinary Encoding
Type StateType Is ( Home, One, Two, Three , Four);
Signal State : Statetype;
Case State Is
When Others => State
-
7/28/2019 20 Basic Finite State Machines
21/39
Basic Finite State Machines 21
Two Most Common Finite State
Machine (FSM) Types Binary: Smallest m (flip-flop count) with
2m n (state count), highest encoding
efficiency. Or Gray Coded, a re-mapping of a binary FSM
One Hot: m = n, i.e., one flip-flop per state,
lowest encoding efficiency. Or Modified One Hot: m = n-1 (one state
represented by 0 vector).
-
7/28/2019 20 Basic Finite State Machines
22/39
Basic Finite State Machines 22
Issue: How To Protect FSMs
Against Transient Errors (SEUs and
MEUs):
Illegal State Detection
Adding Error Detection and Correction (EDAC)Circuitry
-
7/28/2019 20 Basic Finite State Machines
23/39
Basic Finite State Machines 23
Binary and Gray CodesFSM State Sequences
0 0 0
0 0 1
0 1 1
0 1 01 1 0
1 1 1
1 0 1
1 0 0
3-bit Reflected
Gray Code
0 0 0
0 0 1
0 1 0
0 1 11 0 0
1 0 1
1 1 0
1 1 1
Binary Code
Binary sequence can have 0
(hold), 1, 2, ..., n bits
changing from state to state.
Gray code structure ensures
that either 0 (hold) or 1 bit
changes from state to state.
Illegal states in either type
are detected in the sameway, i.e., by explicit
decoding.
-
7/28/2019 20 Basic Finite State Machines
24/39
Basic Finite State Machines 24
Gray CodeIllegal Transition Detection
Next State
Logic
State Bit
Register
Last State
Register
>1
logic 1
Bit-wise
XOR
inputsoutputs
illegal
transition
False illegal transition indications can also be triggered by
errors in the Last State Register, and doubling the number of
bits doubles the probability of an SEU.
-
7/28/2019 20 Basic Finite State Machines
25/39
Basic Finite State Machines 25
One Hot FSM Coding
Many (2n-n)unused states - not
"reachable" from
VHDL2.
Illegal state
detection circuitry
complex
Parity (odd) willdetect all SEUs,
not MEUs
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 00 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 01 0 1
1 1 0
1 1 1
Binary CodeOne HotCoding
2"The Impact of Software and CAE Tools on SEU in Field
Programmable Gate Arrays," R. Katz, et. al., IEEE Transactions on
Nuclear Science, December, 1999.
-
7/28/2019 20 Basic Finite State Machines
26/39
Basic Finite State Machines 26
One Hot FSM Coding
Example of Lockup7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 00 0 0 1 0 0 1 0
0 0 0 0 1 0 0 1
1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 00 0 1 0 0 0 0 1
One Hot FSM
without protection.
SEU
FSM is locked up.
-
7/28/2019 20 Basic Finite State Machines
27/39
Basic Finite State Machines 27
Modified One Hot FSM Coding7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 00 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
One Hot
Coding
6 5 4 3 2 1 0
0 0 0 0 0 0 0
1 0 0 0 0 0 0
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 00 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
Modified One Hot
Coding
Note: Sometimes used by synthesis when one hot FSM
specified. Modified one hot codings use one less flip-flop.
-
7/28/2019 20 Basic Finite State Machines
28/39
Basic Finite State Machines 28
Modified One Hot FSMIllegal State Detection
Error detection more difficult than for one hot
1 0 upsets result in a legal state.
Parity will not detect all SEUs.
If an SEU occurs, most likely the upset will bedetectable
Recovery from lockup sequence simple
If all 0's (NOR of state bits), then generate a 1 to first
stage.
If multiple 1's (more difficult to detect), then will wait
until all 1's are "shifted out."
-
7/28/2019 20 Basic Finite State Machines
29/39
Basic Finite State Machines 29
Discuss Hamming Codes
(to be included)
-
7/28/2019 20 Basic Finite State Machines
30/39
Basic Finite State Machines 30
Is There a Best FSM Type, and Is It Best
Protected Against Transient Errors By
Circuit-Level or System-Level EDAC?
Circuit-level EDAC
Expensive in power and mass if used to protect all
circuits
Can be defeated by multiple-bit transient errors
Can be defeated by clock upset
System-level EDAC
Required for hard-failure handling
Relies on inherent redundancy in system, high-level
error checking, and some EDAC hardware
-
7/28/2019 20 Basic Finite State Machines
31/39
Basic Finite State Machines 31
But It Gets Worse Some synthesizers may replicate flip-flops.
Block A
Block B
Block C
Block D
Block B
Block C
Block D
Block A
-
7/28/2019 20 Basic Finite State Machines
32/39
Basic Finite State Machines 32
And Worse ...
Backend software may also replicate flip-flops
This can be bad if the flip-flop is used to
synchronize an asynchronous signal.
-
7/28/2019 20 Basic Finite State Machines
33/39
Basic Finite State Machines 33
And Yet Worse ...Logic Translation/Optimization
Original
Optimized
Yes, the designer used this point to
synchronize signals and drive a
motor. The short circuit was bad.
-
7/28/2019 20 Basic Finite State Machines
34/39
Basic Finite State Machines 34
What Can You Do?Some Helpful Hints and Points for
Discussion
CONTROL Your Design
Schematic vs. HDL
Constant encodings vs. enumeration
Manual State Assignment
Dont leave unused states - add Dummy States
Add logic to trick the synthesizer to think they are usedas otherwise they may be optimized out. This may
include adding a test signal to sequence through
unused states as well as bringing out dummy outputs.
-
7/28/2019 20 Basic Finite State Machines
35/39
Basic Finite State Machines 35
What Can You Do?More Helpful Hints and Points for
Discussion
Ban All FPGAs
-
7/28/2019 20 Basic Finite State Machines
36/39
Basic Finite State Machines 36
What Can You Do?More Helpful Hints and Points for
Discussion
Monitor Your Design
Check The Synthesizer Listings Number of flip-flops
Too many flip-flops; replication?
Too few flip-flops; eliminated your TMR or parity?
Reports of replication Is the state assignment one that you asked for?
Sometimes the synthesizer thinks it knows best.
-
7/28/2019 20 Basic Finite State Machines
37/39
Basic Finite State Machines 37
What Can You Do?More Helpful Hints and Points for
Discussion
Monitor Your Design (continued)
Check Flip-Flop Reports Has it moved flip-flops into the I/O cells with perhaps
poor SEU performance?
Substituted an S-Module based flip-flop for your C-
Module based one?
Did the synthesizer generate TMR the way you asked
for it or just ignore you?
-
7/28/2019 20 Basic Finite State Machines
38/39
Basic Finite State Machines 38
What Can You Do?More Helpful Hints and Points for
Discussion
Monitor Your Design (continued)
Check Auxiliary Files Check list of cells that the optimizer deleted
Generate Schematics for Critical Areas of
Synthesized Logic
This may uncover some rather interesting surprises.
Send them to me for the next seminar; win a free Diet
Coke.
-
7/28/2019 20 Basic Finite State Machines
39/39
What Can You Do?More Helpful Hints and Points for
Discussion
Verify your design thoroughly
Do not rely solely on simulation!!!!!
Look and think. Do not rely on these tools to
do your thinking for you.