2. PROPOSED LOSS MODEL

6

2. PROPOSED LOSS MODEL

In this chapter, loss models for a power switching transistor and power diode are

proposed. Section 2.1 describes the development of the proposed conduction loss model.

The construction of an existing waveform based switching loss model is set forth in

Section 2.2. The approach of Section 2.2 was set forth in [10] and is discussed herein

since it is the closest existing approach to the proposed approach. In Section 2.3, a

proposed passive based switching loss model is described. Finally, in Section 2.4, a

comparison of the numerical switching loss models is presented. The proposed approach

will lead to a model that incorporates conduction and switching losses as a function of

temperature in a computationally efficient manner.

2.1 Conduction Loss Model

Figure 2.1 depicts the circuit implementation of the conduction loss model.

Conduction losses are represented by a current dependent voltage drop. Due to the fact

that conduction losses are only a function of current through the device and temperature,

no transients faster than the device current are introduced by this representation.

Fig. 2.1 – Conduction Loss Circuit Implementation

7

In Figure 2.1, the conduction loss voltage drop of the transistor and diode are

denoted tcdv and dcdv respectively. In particular, the voltage drops are expressed

),( xjxxcdxcd Tifv = (2.1)

where ''x is ''t for transistor or ''d for diode, and xjT represents the junction temperature

of the device.

2.2 Waveform Based Switching Loss Model

One of the main performance features of any semiconductor switching device is

its switching characteristics. Understanding the device switching characteristics and

associated losses can lead to superior designs.

One method to include switching losses would be to attempt to model the

transient behavior of the switch with either a physics-based model [3] or a waveform

level behavioral model [6-8]. Such an approach necessarily results in the introduction of

very high frequency dynamics which greatly increases computation time.

One way to avoid this problem is to use the approach set forth in [10]. Therein,

switching losses were represented by introducing an artificial square wave switching

transient that results in the same loss as the actual switching transient but using a

simplified transient waveform. The idealized waveforms were not representative of the

actual device voltage and current but yielded the same loss. This method was shown to be

straightforward and did not involve introducing either additional states or artificial

control loops into the system such as in [15]. Switching losses were integrated without

introducing high frequency transients. This method was shown to predict switching losses

accurately.

Three canonical cells are considered herein to explain the method [10]. These

cells are the basic building blocks of most power electronic based converters and are

shown below in Figure 2.2, Figure 2.3, and Figure 2.4. The cell in Figure 2.2 is a buck

converter cell, the cell in Figure 2.3 is a boost converter cell, and the cell in Figure 2.4 is

a phase leg cell. Details on how to model each cell will be discussed in the sections to

follow.

8

Fig. 2.2 – Buck Converter Cell

Fig. 2.3 – Boost Converter Cell

Fig. 2.4 – Phase Leg Cell

2.2.1 Buck Converter Cell

In this cell, sv denotes the dc source voltage, si is the source current, lrv is the line-

to-bottom rail voltage, Li denotes the load current, and s is the switch signal. Depending

upon whether the switch is on or off, two possible switching event scenarios need to be

considered when using the buck converter cell in Figure 2.2. Case 1 is shown in Figure

2.5 and represents the situation when the inductor current is positive and there is a

9

transition between the transistor conducting and the diode conducting. The waveforms

therein are divided into four intervals: an Initial Conduction Interval in which the

waveforms are in the quasi steady state, Switching Interval 1 which corresponds to logic

propagation delay, Switching Interval 2 in which losses are represented, and a Final

Conduction Interval which is the next quasi steady state condition. The time (denoted by

the dotted line) between Initial Conduction Interval and Switching Interval 1 corresponds

to the change in switching command (s being turned off). After a logic propagation

delay of ldofft (Switching Interval 1), the assumed switching transient begins. During

Switching Interval 2, the line-to-bottom rail voltage lrv is low but the current si is still

positive so the leg dissipates a powersLvi . Observe that the total energy dissipated by the

leg during Switching Interval 2 is

etdsL tviE = (2.2)

where etdt is the effective transistor to diode switching time. The losses incurred during

etdt consist of the sum of the transistor turn-off losses and the diode turn on losses.

10

Fig. 2.5. – Case 1: Transistor to Diode

Case 2 is shown in Figure 2.6 and represents the situation when the load (typically

inductor) current is positive and there is a transition between the diode conducting and

the transistor conducting. The time (denoted by the dotted line) between Initial

Conduction Interval and Switching Interval 1 corresponds to the change in switching

command (s being turned on). After a logic propagation delay of ldont (Switching

Interval 1), the assumed switching transient begins. During Switching Interval 2, the

line-to-bottom rail voltage lrv is low but the current si is still positive so the leg

dissipates a power sLvi . Observe that the total energy dissipated by the leg during

Switching Interval 2 is

edtsL tviE = (2.3)

where edtt is the effective diode to transistor switching time. The losses incurred during

edtt include the sum of the diode turn off losses and the transistor turn on losses.

11

Fig. 2.6. – Case 2: Diode to Transistor

Table 2.1 summarizes the assumed waveforms by specifying the line-to-ground

voltage and source current for each interval of each case. In this table, tcdv is the

transistor conduction loss voltage drop, dcdv is the diode conduction loss voltage drop,

Li is the load current, and sv is the source voltage. The next conduction interval is not

represented in the table because the next conduction interval in one case is the initial

conduction interval in another case. Both tcdv and dcdv are functions of current and

temperature as described in (2.1).

12

Table 2.1 Model Summary for Buck Converter

Time Period Duration lrv si

Conduction Interval

1=s 0≥Li - tcds vv − Li

0=s 0≥Li - dcdv− 0

Switching Interval 1

1=s 0≥Li ldofft tcds vv − Li

0=s 0≥Li ldont dcdv− 0


Case 1 etdt 0 Li

Case 2 edtt 0 Li

2.2.2 Boost Converter Cell

The next cell considered is the boost converter cell. In this cell, si is the source

current, lrv is the line-to-bottom rail voltage, Lv denotes the load voltage, Li denotes the

load current, and s is the switch signal. Depending upon whether the switch is on or off,

two possible switching event scenarios need to be considered. Case 1 is shown in Figure

2.7 and represents the situation when the source current is positive and there is a

transition between the diode conducting and the transistor conducting. The time

(denoted by the dotted line) between Initial Conduction Interval and Switching Interval 1

corresponds to the change in switching command (s being turned on). After a logic

propagation delay ofldont (Switching Interval 1), the assumed switching transient begins.

During Switching Interval 2, the load current Li is low, but the line-to-bottom rail voltage

lrv is still positive so the phase leg dissipates a power )( dcdLs vvi + . Because the diode

voltage dcdv is small compared to load voltageLv , the diode voltagedcdv can be neglected.

So, the expression for the power loss during Switching Interval 2 reduces to sLiv .

Observe that the total energy dissipated by the leg during Switching Interval 2 is

edtLs tviE = (2.4)

13


edtt consist of the sum of the transistor turn-on losses and the diode turn off losses.

Fig. 2.7 – Case 1: Diode to Transistor

Case 2 is shown in Figure 2.8 and represents the situation when the source current

is positive and there is a transition between the transistor conducting and the diode

conducting. The time (denoted by the dotted line) between Initial Conduction Interval

and Switching Interval 1 corresponds to the change in switching command (s being

turned off). After a logic propagation delay ofldofft (Switching Interval 1), the assumed

switching transient begins. During Switching Interval 2, the load current Li is low, but

the line-to-bottom rail voltage lrv is still positive so the phase leg dissipates a power

)( dcdLs vvi + . Because the diode voltagedcdv is small compared to the load voltageLv , the

diode voltage dcdv can be neglected. So, the expression for the power loss during

14

Switching Interval 2 reduces to sLiv . Observe that the total energy dissipated by the leg

during Switching Interval 2 is

etdLs tviE = (2.5)


etdt include the sum of the diode turn on losses and the transistor turn off losses.

Fig. 2.8 – Case 2: Transistor to Diode


voltage and load current for each interval of each case. In this table, tcdv is the transistor

conduction loss voltage drop, dcdv is the diode conduction loss voltage drop, si is the

source current, and Lv is the load voltage. The next conduction interval is not



temperature as described in (2.1).

15

Table 2.2 Model Summary for Boost Converter

Time Period Duration lrv Li

Conduction Interval

1=s 0≥si - tcdv 0

0=s 0≥si - dcdL vv + si


1=s 0≥si ldont tcdv si

0=s 0≥si ldofft dcdL vv + 0


Case 1 edtt dcdL vv + 0

Case 2 etdt dcdL vv + 0

2.2.3 Phase Leg Cell

In this cell, sv denotes the source voltage, si is the source current, lrv is the line-to-

bottom rail voltage, Li denotes the load current, us is the upper switch signal, and ls is

the lower switch signal. Depending upon whether the switch is on or off, four possible

switching event scenarios need to be considered Case 1 is shown in Figure 2.9 and

represents the situation when the load (typically inductor) current is positive and there is

a transition between the upper transistor conducting and the lower diode conducting.

The time (denoted by the dotted line) between Initial Conduction Interval and Switching

Interval 1 corresponds to the change in switching command ( us being turned off). After

a logic propagation delay ofldofft (Switching Interval 1), the assumed switching transient

begins. During Switching Interval 2, the line-to-bottom rail voltage lrv is low but the

current si is still positive so the leg dissipates a powersLvi . Observe that the total energy

dissipated by the leg during Switching Interval 2 is

etdsL tviE = (2.6)


etdt consist of the sum of the transistor turn-off losses and the diode turn on losses.

16

Fig. 2.9 – Case 1: Upper Transistor to Lower Diode

Case 2 is shown in Figure 2.10 and represents the situation when the load current

is positive and there is a transition between the lower diode conducting and the upper

transistor conducting. The time (denoted by the dotted line) between Initial Conduction

Interval and Switching Interval 1 corresponds to the change in switching command (us

being turned on). After a logic propagation delay of ldont (Switching Interval 1), the

assumed switching transient begins. During Switching Interval 2, the line-to-bottom rail

voltage lrv is low but the current si is still positive so the leg dissipates a powersLvi .

Observe that the total energy dissipated by the leg during Switching Interval 2 is

edtsL tviE = (2.7)


edtt include the sum of the diode turn off losses and the transistor turn on losses.

17

Fig. 2.10 – Case 2: Lower Diode to Upper Transistor

Case 3 is shown in Figure 2.11 and represents the situation when the inductor

current is negative and there is a transition between the upper diode conducting and the

lower transistor conducting. The time (denoted by the dotted line) between Initial


command ( us being turned on). After a logic propagation delay of ldont (Switching


source current si is low, but the line-to-bottom rail voltage lrv is still positive so the

phase leg dissipates a power )( dcdsL vvi +− . Because the diode voltagedcdv is small

compared to source voltagesv , the diode voltagedcdv can be neglected. So, the expression

for the power loss during Switching Interval 2 reduces to Ls iv− . Observe that the total

energy dissipated by the leg during Switching Interval 2 is

edtsL tviE −= (2.8)

18


edtt consist of the sum of the transistor turn-on losses and the diode turn off losses.

Fig. 2.11 – Case 3: Upper Diode to Lower Transistor

Case 4 is shown in Figure 2.12 and represents the situation when the inductor

current is negative and there is a transition between the lower transistor conducting and

the upper diode conducting. The time (denoted by the dotted line) between Initial


command ( us being turned off). After a logic propagation delay of ldofft (Switching


source current si is low, but the line-to-bottom rail voltage lrv is still positive so the

phase leg dissipates a power of approximatelyLs iv− . Observe that the total energy

dissipated by the leg during Switching Interval 2 is

etdsL tviE −= (2.9)

19


etdt include the sum of the diode turn on losses and the transistor turn off losses. Table

2.3 summarizes the assumed waveforms for a phase leg.

Fig. 2.12 – Case 4: Lower Transistor to Upper Diode


voltage and source current for each interval of each case. In this table, tcdv is the

transistor conduction loss voltage drop, dcdv is the diode conduction loss voltage drop,

Li is the load current, and sv is the source voltage. The next conduction interval is not



temperature as described in (2.1). The time edtt and etdt are calculated from energy loss

measurements on the power semiconductors as set forth in [10]. In [10], these times are a

20

function of the dc voltage and current. Although not considered in [10], they are a

function of temperature as well.

Table 2.3 – Model Summary for Phase Leg

Time Period Duration lrv si

Conduction Interval

1=us

0≥Li - tcds vv − Li

0<Li - dcds vv + Li

0=us

0≥Li - dcdv− 0

0<Li - tcdv 0 Switching Interval 1

1=us

0≥Li ldofft tcds vv − Li

0<Li ldont dcds vv + Li

0=us

0≥Li ldont dcdv− 0

0<Li ldofft tcdv 0

Switching Interval 2 Case 1 etdt 0 Li

Case 2 edtt 0 Li

Case 3 edtt dcds vv + 0

Case 4 etdt dcds vv + 0

2.3 Passive Based Switching Loss Model

In this section, a new approach to the modeling of switching losses is set forth.

This approach is considerably simpler than the approach previously discussed. In this

approach, the energy stored in passive circuit elements is reduced during each switching

event. In doing so, the energy loss due to switching events can be represented.

To explain this approach, consider the three canonical cells that were discussed

previously. However, in this case, the passive circuit elements are explicitly considered.

In particular, a capacitor with an effective series resistance is added to the buck canonical

cell shown in Figure 2.13, an inductor with an effective series resistance is added to the

boost canonical cell shown in Figure 2.14, and a capacitor with an effective series

21

resistance is added to the phase leg cell shown in Figure 2.15. Note here that an inductor

with an effective series resistor could have been added to the phase leg cell; however the

modeling implementation of a capacitor with an effective series resistor is simpler.

Fig. 2.13 – Buck Converter Cell with Capacitor

Fig. 2.14 – Boost Converter Cell with Inductor

Fig. 2.15 – Phase Leg Cell with Capacitor

Each of the three modified canonical cells will now be considered.

22

2.3.1 Buck Converter Cell with Capacitor

In this cell, sv denotes the dc voltage, si is the source current, lrv is the line-to-

bottom rail voltage,Li denotes the load current, cv is the capacitor voltage, ci is the

capacitor current, ini is the switch current, cr is the effective series resistance of the

capacitor, C is the capacitance, and s is the switch signal. The energy stored in the

capacitor can be computed as

2

2

1cc CvE = (2.10)

where cv denotes the voltage across the capacitor. Solving for the capacitor voltage yields

C

Ev c

c

2= (2.11)

Now consider a switching event, either a diode to transistor transition with energy

loss dtE or a transistor to diode transition with energy loss tdE . To model switching

losses using the proposed approach, the energy losses are subtracted from the energy

stored in the capacitor at each switching event. In particular, recomputing the capacitor

voltage yields

( )

C

EEv

xoldc

newc

−=

2 (2.12)

where x is ''dt for diode to transistor transition or ''td for transistor to diode transition

and ‘old’ and ‘new’ refer to the instant just prior to and just after the switching event.

2.3.2 Boost Converter Cell with Inductor

In this cell, Lv denotes the load voltage, Li denotes the load current, lrv is the line-

to-bottom rail voltage, si is the source current, Lr is the effective series resistance of the

inductor, L is the inductance, and s is the switch signal. The energy stored in the

inductor can be computed as

2

2

1sL LiE = (2.13)

23

Solving for the inductor current yields

L

Ei L

s

2= (2.14)

Now consider a switching event. To model switching losses, the energy losses in

the transistor and diode (dtE or tdE , depending on the event) are subtracted from the

energy stored in the inductor at each switching event. Recomputing the inductor current

yields

( )

L

EEi

xoldL

news

−=

2 (2.15)

where x is ''dt for diode to transistor or ''td for transistor to diode, and ‘old’ and ‘new’

refer to the instant just prior to and just after the switching event.

2.3.3 Phase Leg Cell with Capacitor

In this cell, sv denotes the dc voltage, si is the source current, lrv is the line-to-

bottom rail voltage, Li denotes the load current, cv is the capacitor voltage, ci is the

capacitor current, ini is the switch current, cr is the effective series resistance of the

capacitor, C is the capacitance, us is the upper switch signal, and ls is the lower switch

signal. The energy stored in the capacitor can be computed as

2

2

1cc CvE = (2.16)

where cv denotes the voltage across the capacitor. Solving for the capacitor voltage yields

C

Ev c

c

2= (2.17)

To model switching losses, the energy losses in the transistor and diode (dtE or tdE ) are

subtracted from the energy stored in the capacitor at each switching event. Recomputing

the capacitor voltage yields

24

( )

C

EEv xoldc

newc

−=

2 (2.18)

where x is ''dt for diode to transistor or ''td for transistor to diode, and ‘old’ and ‘new’

refer to the instant just prior to and just after the switching event.

2.4 Numerical Comparison of Models

In this section, the waveform based switching loss model approach is compared to

the proposed passive based switching loss model approach for each cell. In addition,

both models are compared to a ‘standard’ model which does not include switching losses.

To compare the different models, a study is conducted where waveforms from the

different models are plotted for each respective cell. The waveforms and average value

of various variables are computed and compared. In addition, the simulation speeds for

each model of each respective cell were also compared. All studies were conducted in

ACSL 11.8 [17] and utilized a fourth order Runge-Kutta integration algorithm with a

100µs communication interval, a 100µs time step, and an event accuracy of 1µs. These

studies were run on a 3.40 GHz Pentium 4 processor running the Windows XP operating

system.

The first cell considered here is the buck converter cell. To conduct this study, a

buck converter is simulated wherein the dc voltagesv is 100V, the load resistanceLR is

21.8Ω , the input capacitanceinC and output capacitanceoutC is 500uF, the effective

series resistances of the input and output capacitor, cinr and coutr , are 0.2Ω and 0.1Ω

respectively, the source inductancesL is 0.1mH, the source resistancesr is 0.1Ω, the

effective series resistance of the inductorLr is 0.1Ω, and the inductanceL is 2mH. The

transistor and diode voltage drops along with energy losses ( dtE and tdE ) were computed

based on the models set forth in Appendix A. Parameters for these models are included in

Appendix A as well. The switching signal for the transistor had a duty cycle of 0.5 and a

switching frequency of 30 kHz. A buck converter schematic is shown in Figure 2.16.

25

Figure 2.16 – Buck Converter

Waveforms depicting the capacitor voltage, capacitor current, source current, line-

to-bottom rail voltage, and switch current are displayed in Figure 2.17, Figure 2.18,

Figure 2.19, Figure 2.20, and Figure 2.21 respectively.

0.1001 0.100299.82

99.84

99.86

99.88

99.9

99.92

99.94

16.5µs

Time (s)

Cap

acito

r V

olta

ge (

V)

Passive Based Model

Standard Model

Waveform Based Model

Figure 2.17 – Capacitor Voltage

26

0.1001 0.1002

-1.5

-1

-0.5

0

0.5

1

16.5µs

Time (s)

Cap

acito

r C

urre

nt (

A)

Passive Based Model

Standard Model


Fig. 2.18 – Capacitor Current

0.1001 0.10021.02

1.04

1.06

1.08

1.1

1.12

1.14

1.16

1.18

1.2

16.5µs

Time (s)

Sou

rce

Cur

rent

(A

)

Passive Based Model

Standard Model


Fig. 2.19 – Source Current

27

0.1001 0.1002

0

20

40

60

80

100

16.5µs

Time (s)

Line

-To-

Bot

tom

Rai

l Vol

tage

(V

)

Passive Based Model

Standard Model


Figure 2.20 – Line-To-Bottom Rail Voltage

0.1001 0.10020

0.5

1

1.5

2

2.5

3

16.5µs

Time (s)

Sw

itch

Cur

rent

(A

)

Passive Based Model

Standard Model


Figure 2.21 – Switch Current

In Figure 2.17, it can be shown that the capacitor voltage for the passive based

model is slightly less than the capacitor voltage in the other two models. This is because

28

the capacitor voltage during each switching event is reduced via the passive based model.

The reduction in capacitor voltage, in turn, causes the source current and capacitor

current to increase. The increase in capacitor current and source current is depicted in

Figure 2.18 and Figure 2.19 respectively. Note the offset in the switching time in the

line-to-bottom rail voltage predicted by the waveform based model in Figure 2.20. This

offset is due to the effective switching time in the waveform based model.

The input power, input current, output power, output voltage, output current, and

efficiency were computed for the buck converter cell and are displayed in Table 2.4. The

absolute value of all variables is portrayed in the table. As can be seen, the efficiency

predicted by the standard model is higher than the efficiency predicted by the passive

based and waveform based models. This is not surprisingly since the standard model has

no switching losses. In addition, the efficiency predicted by the passive based model was

approximately equal to the efficiency predicted by the waveform based model.

Table 2.4 – Average Quantities for Buck Converter Cell

Cell Variables Passive Based Waveform Based Standard

Buck Converter

Input Power (W) 112.96 109.71 110.4 Input Current (A) 1.131 1.098 1.105 Output Power (W) 106.5 103.38 106.5 Output Voltage (V) 48.18 47.47 48.19 Output Current (A) 2.210 2.178 2.210

Efficiency 0.943 0.942 0.965

The simulation speed of the different switching loss models was also compared.

These studies were conducted in ACSL 11.8 [17] and utilized a fourth order Runge-Kutta

integration algorithm with a 100µs communication interval, a 100µs time step, and an

event accuracy of 1µs. These studies were run on a 3.40 GHz Pentium 4 processor

running the Windows XP operating system. The length of time required to simulate

0.25s using the passive based model was 0.187 second. The length of time it took the

standard model to run was 0.156 second. A time of 0.235 second was required for the

waveform based model.

The next cell considered is the boost converter cell. To conduct this study, a

boost converter is simulated wherein the dc voltagesv is 100V, the load resistanceLR is

29

21.8Ω , the input capacitanceinC and output capacitanceoutC is 500uF, the effective

series resistances of the input and output capacitor, cinr and coutr , are 0.2Ω and 0.1Ω

respectively, the source inductancesL is 0.1mH, the source resistancesr is 0.1Ω, the

effective series resistance of the inductorLr is 0.1Ω, and the inductanceL is 2mH. The

transistor and diode voltage drops along with energy losses ( dtE and tdE ) were computed

using mathematical models set forth in Appendix A. Parameters for these models are

included in Appendix A as well. To generate the switching signal for the transistor, a

pulse width modulator with a duty cycle of 0.5 and a switching frequency of 30 kHz is

used. A schematic of the boost converter is shown in Figure 2.22.

Figure 2.22 – Boost Converter

Waveforms depicting the inductor current, source current, line-to-bottom rail

voltage, and switch current are displayed in Figure 2.23, Figure 2.24, Figure 2.25 and

Figure 2.26 respectively.

30

0.1001 0.100215.5

16

16.5

17

17.5

18

18.5

16.5µs

Time (s)

Indu

ctor

Cur

rent

(A

)

Passive Based Model

Standard Model


Figure 2.23 – Inductor Current

0.1001 0.100216.5

16.6

16.7

16.8

16.9

17

17.1

17.2

17.3

17.4

17.5

16.5µs

Time (s)

Sou

rce

Cur

rent

(A

)

Passive Based Model

Standard Model


Figure 2.24 – Source Current

31

0.1001 0.10020

20

40

60

80

100

120

140

160

180

200

16.5µs

Time (s)

Line

-to-

Bot

tom

Rai

l Vol

tage

(V

)

Passive Based Model

Standard Model


Fig. 2.25- Line-To-Bottom Rail Voltage

0.1001 0.10020

2

4

6

8

10

12

14

16

18

16.5µs

Time (s)

Sw

itch

Cur

rent

(A

)

Passive Based Model

Standard Model


Figure 2.26 – Switch Current

In Figure 2.23, it can be shown that the inductor current predicted by the passive

based model is less than that predicted by the other two models. This is because the

32

inductor current is reduced at each switching event in the passive based model. The

reduction in inductor current, in turn, causes the source current to decrease in the passive

based model. The decrease in source current is depicted in Figure 2.24. Once again,

there is an offset in the switching time in the line-to-bottom rail voltage calculated by the

waveform based model in Figure 2.25. This offset is due to the effective switching time

in the waveform based model.

In Table 2.5, the input power, input current, output power, output voltage, output

current, and efficiency are listed for the boost converter cell. As was the case for the

buck converter cell, the absolute value of all variables is shown. Not surprisingly, the

efficiency predicted by the standard model is higher than the efficiency predicted by the

passive based and waveform based models. This is not surprisingly since the standard

model has no switching losses. The efficiency predicted by the passive based model was

approximately equal to the efficiency predicted by the waveform based model.

Table 2.5 – Average Quantities for Boost Converter Cell

Cell Variables Passive Based Waveform Based Standard

Boost Converter

Input Power (W) 1640 1664 1692 Input Current (A) 16.68 16.93 17.22 Output Power (W) 1517 1540 1616 Output Voltage (V) 181.9 183.2 187.7 Output Current (A) 8.342 8.405 8.609

Efficiency 0.925 0.926 0.955

The simulation speed of the different switching loss models was also compared.

These studies were conducted in ACSL 11.8 [17] and utilized a fourth order Runge-Kutta



running the Windows XP operating system. The length of time required to simulate

0.25s using the passive based model was 0.172 second. The length of time required by

the standard model was 0.140 second. The waveform based model required 0.234 second.

The final cell considered is the phase leg cell. To conduct this study, an inverter

comprised of three phase legs is simulated wherein the dc voltagesv is 200V, the input

33

capacitance inC is 500uF, the effective series resistance of the input capacitancecinr is

0.2Ω, the source inductancesL is 0.1mH, and the source resistancesr is 0.1Ω. The

inverter supplies three-phase current to a four–pole permanent magnet synchronous

machine. The stator resistance is 2.6Ω, the q-axis and d-axis inductance is 12.4mH, and

the peak flux linkage due to the permanent magnet is 0.286Vs. The mechanical speed of

the machine is regulated at 1700 rpm. To generate the switching signals for the transistors,

a delta modulator with a switching frequency of 200 kHz is utilized. A synchronous

current regulator [16] with a time constant 0.01s is used to generate the current

commands for the modulator. A q-axis current command of 1.748A with a d-axis current

command of 0A was utilized in the synchronous current regulator. The transistor and

diode voltage drops along with energy losses (dtE and tdE ) were computed using

mathematical models set forth in Appendix A. Parameters for these models are included

in Appendix A as well. A figure depicting the inverter is shown in Figure 2.27.

Figure 2.27 - Inverter

The a-phase current waveform predicted by the standard model over one

fundamental cycle is depicted in Figure 2.28. Unlike the buck and boost converter, it is

34

difficult to compare waveforms because of the wide range of frequency content and

amplitudes in the variables of the inverter.

0.068 0.07 0.072 0.074 0.076 0.078 0.08 0.082 0.084-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

A-p

hase

Cur

rent

Time (s)

Fig. 2.28 – A-phase Current

For the phase leg cell, the average of the input power, output power, efficiency,

torque, q-axis and d-axis current, and q-axis and d-axis voltage were calculated and are

displayed in Table 2.6. As was the case for the buck and boost converter, the efficiency

predicted by the standard model is higher than the efficiency predicted by the passive

based and waveform based models. This is not unexpected since the standard model has

no switching losses.

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Table 2.6 – Average Quantities for Phase Leg Cell

Cell Variables Passive-Based Waveform-Based Standard

Phase Leg

Input Power (W) 285.2 285.1 284.2 Output Power (W) 279 278.9 279

Efficiency 0.978 0.978 0.981 Torque (Nm) 1.500 1.500 1.500

Q-axis Current (A) 1.748 1.748 1.748 D-axis Current (A) 0.000 0.000 0.000 Q-axis Voltage (V) 106.4 106.4 106.4 D-axis Voltage (V) 7.710 7.708 7.710

The simulation speed of the different switching loss models was compared. These

studies were conducted in ACSL 11.8 [17] and utilized a fourth order Runge-Kutta



running the Windows XP operating system. The length of time it took the passive based

model to simulate 0.25s was 0.391 second. The length of time required by the standard

model was 0.360 second. The waveform based model required 0.563 second.

2. PROPOSED LOSS MODEL

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