2 Marks Ques Ans. of VLSI

8/13/2019 2 Marks Ques Ans. of VLSI

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IV YEAR ELECTRONICS AND INSTRUMENTATION

ENGINEERINGEC1461-VLSI Design

(2mark questions and answers)

Unit I

1. Define Thresh !" # !t$geThe threshold voltage VT for a MOS transistor can be defined as the

voltage between the gate and the source terminals below which the drainto source current effectively dro s to !ero"

Define % "& effe't r s(%str$te %i$s effe't.The threshold voltage VT is not a constant with res ect to the voltagedifference between the substrate and the source of the MOS transistor"This effect is called the body effect or substrate bias effect"

). Gi#e the "ifferent * "es f +er$ti n f MOS tr$nsist r#ut off mode$inear modeSaturation mode

,. h$t $re the "ifferent regi ns f +er$ti n f $ MOS tr$nsist r$. C(t ff regi n

%ere the current flow is essentially !ero (accumulation mode)%. Line$r regi n&t is also called weak inversion region where the drain current isde endent on the gate and the drain voltage w" r" to the substrate"'. S$t(r$ti n regi n#hannel is strongly inverted and the drain current flow is ideallyinde endent of the drain'source voltage (strong'inversion region)"

4. Gi#e the e/+ressi ns f r "r$in '(rrent f r "ifferent * "es f+er$ti n f

MOS tr$nsist r.a" #ut off region

& * b" $inear region


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structures" Triggering these thyristor like devices leads to a shorting of V1 VSS lines0 usually resulting in a destruction of the chi "The re*e"ies f r the !$t'h-(+ +r %!e* in'!("e

(i) an increase in substrate do ing levels with a consequent dro in thevalue of subs"

(ii) reducing nwell by control of fabrication arameters and ensuringa low contact resistance to V "

(iii) by introducing guard rings"

7. h$t $re the "ifferent f$%ri'$ti n +r 'esses $#$i!$%!e t CMOSte'hn ! g&

a" 'well rocess b" n'well rocessc" Twin'tub rocess

d" Silicon On &nsulator (SO&) . Silicon On Sa hire (SOS) rocess

18. h$t is intrinsi' $n" e/trinsi' se*i' n"('t rThe ure silicon is known as &ntrinsic Semiconductor" 3hen im urity

is added with ure silicon0 it is electrical ro erties are varied" This is knownas 45trinsic semiconductor"

1). h$t $re the ste+s in# !#e" in *$n(f$'t(ring f IC66 i" wafer re aration

ii" 4 ita5ial growthiii" O5idationiv" hoto lithogra hyv" iffusion and &on &m lantationvi" &solationvii" Metalli!ation

1,. h$t is *e$nt %& 9 e+it$/& : 4 ita5y means arranging atoms in single crystal fashion u on a single

crystal substrate"

14. 5h$t $re the +r 'ess in# !#e" in +h t !ith gr$+h&i" making rocessii" hoto etching rocess

these are im ortant rocess involved in hotolithogra hy"


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10. 5h$t is the +(r+ se f *$s;ing in f$%ri'$ti n f ICMasking is used to identify the lace in which &on &m lantion should

not be occurred"

16. 5h$t $re the *$teri$!s (se" f r *$s;ing7hoto resist0 Sio20 Si80 oly Silicon"

12.5h$t $re the t&+es f et'hing 3et etching and dry etching are the ty es of hoto etching"

13. 5h$t is "iff(si n +r 'ess 5h$t $re " +ing i*+(ritiesiffusion is a rocess in which im urities are diffused in to the silicon

chi at 9*** *# tem erature" : 2O ; and 7 2O< are used as im urities"

17. 5h$t is is !$ti n&t is a rocess used to rovide electrical isolation between different

com onents and interconnections"

)8. 5h$t $re the #$ri (s CMOS te'hn ! giesVarious #MOS technologies are

i" n'well rocess or n'tub rocessii" 'well rocess or 'tub rocessiii" twin'tub rocess

iv" Silicon on &nsulator (SO&) rocess"

)1. 5h$t is 'h$nne! st + i*+!$nt$ti n&n n'well fabrication0 n'well is rotected with resist material" :ecause0

it should not be affected by :oron im lantation" The boron is im lane5ce tn'well" &t is done using hotoresist mask" This ty e of im lantation is knownas channel im lantation"

)). 5h$t is LOCS

$O#OS means $ocal O5idation Of Silicon" This is one ty e of o5ideconstruction"

),. 5h$t is S AMIS3=M& means Side 3all Masked &solation" &t is used to reduce

bird>s beak effect"


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)4. 5h$t is LDD$ means $ight o ed rain Structures" &t is used for im lantation

of n' in n'well rocess"

)0. 5h$t is t5in-t(% +r 'ess h& it is '$!!e" sTwin'tub rocess is one of the #MOS technology" There are two

wells are available in this rocess" The other name of well is tub" So0 because of these two tubs0 this rocess is known as twin'tub rocess"

Unit II

1. Dr$5 the 'ir'(it f $ nMOS in#erter.

"

). Gi#e the e/+ressi n f r +(!!-(+ t +(!!-" 5n r$ti < Zpu/Zpd = f r $nnMOSin#erter "ri#en %& $n ther nMOS in#erter.

""


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,. Dr$5 the 'ir'(it f $ CMOS in#erter.

4. h$t $re the $"#$nt$ges f CMOS in#erter #er the ther in#erter' nfig(r$ti ns

a" The steady state ower dissi ation of the #MOS inverter circuit isnegligible"

%. The voltage transfer characteristic (VT#) e5hibits a full out utvoltage wing between *V and V " This results in high noise margin"

0. h$t $re sti'; "i$gr$*sStick diagrams are used to convey layer information through the

use of a color code" = stick diagram is a cartoon of a chi layout" They

are not e5act models of layout" The stick diagram re resents therectangles with lines which re resent wires and com onent symbols"

6. h$t $re the "ifferent ' ! r ' "es (se" f r sing!e + !& si!i' n nMOSte'hn ! g&

n'diffusion (n'diff") and other thino5ide regions 'green7olysilicon ( oly") ' redMetal 9 (metal) ' blue&m lant ' yellow#ontacts ' black or brown (buried)

2. h$t $re "esign r(!esesign rules are the communication link between the designer

s ecifying requirements and the fabricator who materiali!es them" esignrules are used to roduce workable mask layouts from which the variouslayers in silicon will be formed or atterned"


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3. Define $ s(+er%(ffer.= su erbuffer is a symmetric inverting or noninverting gate that cansu ly or remove large currents and switch large ca acitive loads faster than a standard inverter"

7. h$t $re >iCMOS G$tes3hen bi olar and MOS technology are merged0 the resulting circuits

are referred to as bi#MOS circuits" %igh gain vertical n n transistors withtheir collectors tied to the ositive rail0 and medium'gain lateral n ntransistors are both com atible with conventional #MOS rocessing":i#MOS gates can be used to im rove the erformance of line drivers andsense am lifiers"

18. 5h$t is the s+e'i$! fe$t(re f t5in-t(% +r 'ess&n twin'tub rocess0 threshold voltage0 body effect n and devices are

inde endently o timi!ed"

11. 5h$t $re the $"#$nt$ge f t5in-t(% +r 'ess=dvantages of twin'tub rocess are

i" Se arate o timi!ed wells are available"ii" :alance erformance is obtained for n and transistors"

1). 5h$t is SOI h$t is the *$teri$! (se" $s Ins(!$t rSO& means Silicon'on'&nsulator" &n this rocess0 Sa hire or SiO 2 is

used as insulator"

1,. 5h$t $re the #$ri (s et'hing +r 'ess (se" in SOI +r 'essVarious etching rocess used in SO& are

i" &sotro ic etching rocess"ii" =nisotro ic etching rocess"iii" 7referential etching rocess"

14. 5h$t $re the $"#$nt$ges $n" "is$"#$nt$ges 8f SOI +r 'essA"#$nt$ges f SOI +r 'ess

i" There is no well formation in this rocess"ii" There is no field'&nversion roblem"


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iii" There is no body effect roblem"Dis$"#$nt$ges f SOI +r 'ess

i" &t is very difficult to rotect in uts in this rocess"ii" evice gain is low"

iii" The cou ling ca acitance between wires always e5ist"

10. 5h$t $re the + ssi%!e * "es in nMOS enh$n'e*ent tr$nsist ri" accumulation modeii" de letion modeii" &nversion mode

16. In s$t(r$ti n regi n? 5h$t $re the f$'t rs th$t $ffe't I "si" distancebetween source and drain"

ii" channel widthiii"Threshold oltageiv"thickness of o5ide layer v" dielectric constant of gate insulator vi" #arrier mobility"

12. h$t is > "& effe'tThe threshold voltage VT is not a constant w" r" to the voltage difference

between the substrate and the source of MOS transistor" This effect is called

substrate'bias effect or body effect"

13. h$t is Ch$nne!-!ength * "(!$ti n

The current between drain and source terminals is constant and

inde endent of the a lied voltage over the terminals" This is not entirely

correct" The effective length of the conductive channel is actually modulated

by the a lied V S0 increasing V S causes the de letion region at the drain

?unction to grow0 reducing the length of the effective channel"

17.Define Thresh !" # !t$ge in CMOS The Threshold voltage0 V T for a MOS transistor can be defined as thevoltage a lied between the gate and the source of the MOS transistor below


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which the drain to source current0 & S effectively dro s to !ero"

)8. Define Rise ti*eise time0 tr is the time taken for a waveform to rise from 9*@ to A*@ of its

steady'state value"

)1. Define @$!! ti*e@all time0 tf is the time taken for a waveform to fall from A*@ to 9*@ of itssteady'state value"

)). Define De!$& ti*eelay time0 td is the time difference between in ut transition (


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Unit III

1. h$t $re the st$ti' +r +erties f ' *+!e*ent$r& CMOS G$tesa" They e5hibit rails'to'rail swing with VO% V and VO$

,8 " b" The circuits have no static ower dissi ation0 since the circuits are

designed such that the ull'down and ull'u networks are mutuallye5clusive"

c" The analysis of the # voltage transfer characteristics and the noisemargins is more com licated than for the inverter0 as these arametersde end u on the data in ut atterns a lied to the gate"

). Dr$5 the e (i#$!ent RC * "e! f r $ t5 -in+(t NAND g$te.

,. h$t $re the *$B r !i*it$ti ns $ss 'i$te" 5ith ' *+!e*ent$r&CMOS g$te

a" The number of transistors required to im lement an 8 fan'in gate is28" This can result in a significantly large im lementation area"

b" The ro agation delay of a com lementary #MOS gate deterioratesra idly as a function of the fan'in"


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4. h$t is *e$nt %& r$ti e" ! gi'&n ratioed logic0 a gate consists of an nMOS ull'down network that

reali!es the logic function and a sim le load device0 which re lace the entire ull'u network" = ratioed logic which uses a grounded MOS load isreferred to as a seudo'nMOS gate

0. h$t is tr(e sing!e +h$se '! ';e" registerThe True single' hase clocked register (TS7# ) uses a single clock0

#$C" Dor the ositive latch0 when #$C is high0 the latch is in thetrans arent mode and corres onds to two cascaded invertersE the latch isnon'inverting0 and ro agates the in ut to the out ut" On the other hand0when #$C *0 both inverters are disabled0 and the latch is in the hold mode"

6. Define $ t$!!& 'ir'(it.

= tally circuit counts the number of in uts that are high and out uts theanswer" &f there are 8 in uts there are 8 F9 ossible out uts0 corres ondingto *0 90 20 G" 8 in uts that are high"

2. Gi#e the NAND-1 1 L SO F D LRF RI H


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3. UD J 6 D L@ )? H8)6 KD V R U DOL H


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A"Dr$5 the CMOS i*+!e*ent$ti n f 4-t -1 MU (sing tr$ns*issi ng$tes "

18. h$t $re the #$ri (s * "e!ing (se" in Veri! g9" ,ate'level modeling2" ata'flow modeling;" Switch'level modelingH" :ehavioral modeling

11. h$t is the str('t(r$! g$te-!e#e! * "e!ingStructural modeling describes a digital logic networks in terms of thecom onents that make u the system" ,ate'level modeling is based on using

rimitive logic gates and s ecifying how they are wired together"

1). h$t is S5it'h-!e#e! * "e!ing

Verilog allows switch'level modeling that is based on the behavior ofMOSD4Ts" igital circuits at the MOS'transistor level are described usingthe MOSD4T switches"


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1,. h$t $re the t&+es f +r gr$**$%!e "e#i'e7rogrammable logic structure7rogrammable &nterconnect

e rogrammable gate arry

14. h$t is CL>#$: means #onfigurable $ogic :lock"

10. h$t $re the t5 t&+es f MOS@ETTwo ty es of MOS4T are n'channel MOS4T and 'channel MOSD4T"These are known as n'MOS and 'MOS"

16.5hi'h MOS '$n +$ss ! gi' 1 $n" ! gi' 8 str ng!& 'MOS can ass strong logic 9n'MOS can ass strong logic *

12. h$t is AOI ! gi' f(n'ti n=8 O &nvert logic function (=O&) im lements o eration in the order of=8 0 O 0 8OT o erations" So this logic function is known as =O& logicfunction"

13. h$t is %(%%!e +(shing=ccording to e Morgan>s laws0

FF

So 8=8 gate may be drawn as bubbled O gate" :ubbles are introducedin the in ut side" This conce t is known as bubble ushing"

17. I*+!e*ent & (sing %(%%!e +(shing ' n'e+tI can be im lemented using bubbled =8 gate" F

)8. h$t is OAI ))1 G$teO=& 2290 here 229 refers to number of in uts in each section"

)1. rite the fe$t(res f CMOS D *in L gi'These structures occu y small area com ared with conventional logicstructure"


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7arasitic ca acitance is to be small to increase the s eed"4ach gate can make one Jlogic 9> to Jlogic *> transition"

)). h$t $re the t$!!& 'ir'(its

Tally circuits one of the a lications of the ass transistor logic"&t is used to count the number of in uts which are high and the out utis roduced"

),. h$t $re the #$ri (s f r*s f in#erter %$se" CMOS ! gi'i" 7seudo 8'MOS logic

ii" ynamic #'MOS logiciii" #locked #'MOS logic

iv" #'MOS domino logicv" n' #'MOS logic

)4. h$t is I in ILINI7&7 means 7rogrammable &nterconnect 7oint in K&$&8&K"

)0. h$t $re the $"#$nt$ges $n" "is$"#$nt$ges f LAA"#$nt$ges f LA

Sim licity

Small si!eDis$"#$nt$ges f LA

S eed roblem occur ( ull'u s may become slow on large terms )


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Unit IV

1. Gi#e the %$si' nMOS LA str('t(re.

The basic 7$= structure consists of an =8 lane driving an O lane" The terminology corres onds to a sum of roducts (SO7) reali!ationof the desired function" The SO7 reali!ation converts directly into a 8=8 '

8=8 im lementation" 3hen a roduct of sums (7OS) reali!ation isdesired0 it can be im lemented in O '=8 or 8O '8O logic" &n eithercase0 the first array is referred to as the =8 lane0 and the second array asthe O lane" The line connecting the =8 lane to the O lane are calledthe roduct lines"

). h$t " & ( *e$n %& CMOS LA.

The basic #MOS 7$= is obtained by roviding a well and re lacingthe ull'u devices in the 8=8 '8=8 array or in the 8O ' 8O array

with enhancement mode MOS devices" The #MOS array can be recharged or not0 and can be clocked 2 =8 lane O lane egisteregister &n uts Out uts 9 with the same two' hase clocking scheme as used

for the MOS 7$=" #MOS 7$= design offers many more varieties of layoutthan does nMOS"

,. Define finite st$te *$'hine.


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3hen feedback is added to the =8 O 7$= structure0 the 7$= becomes a finite state machine (DSM)" =n DSM can be designed as a MealyMachine or a Moore Machine" The Mealy machine has out uts0 which maychange with in ut changes in an asynchronous manner and cause erroneous

behavior" %ence0 the Mealy machine should be avoided whenever ossible"The Moore machine has out uts which de end u on and change only withstate changes0 since all the out uts of the :oolean'logic block go through astate register0 and are synchronously clocked"

4. h$t $re the i*+ rt$n'e f the LA @SM in VLSI(i) egularity B &t has a standard0 easily e5 andable layout"(ii) #onvenience B $ittle design effort is required"(iii) #om acted B &t is efficient for small circuits"(iv) Modularity B &t makes it ossible to design hierarchical 7$=s and

DSMs into large sequential systems"(v) Suitability to being com uter generated"

0. Gi#e the str('t(re f $ C LD.= #7$ com rises multi le circuit blocks on a single chi 0 with

internal wiring resources to connect the circuit blocks" 4ach circuit block issimilar to a 7$= or a 7=$"&t includes four 7=$ like blocks that areconnected to a set of interconnection wires" 4ach 7=$ like block is alsoconnected to a sub circuit labeled &.O block0 which is attached to a numberof the chi >s in ut and out ut ins"


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6. Gi#e the C LD +$';$ges $#$i!$%!e.$" LCC +$';$ge B The 7$## ackage has ins that Lwra around

the edges of the chi on all four of its sides" The socket that houses the7$## is attached by solder to the circuit board0 and the 7$## is held in thesocket by friction"

%. ($" f!$t +$'; +$';$ge The ND7 ackage has ins on all foursides0 and they e5tend outward from the ackage0 with a downward'wiringsha e" The ND7>s ins are much thinner than those on a 7$##0 whichmeans that the ackage can su ort a larger number of insE ND7s areavailable with more than 2** ins"

2. Gi#e the str('t(re f MA 2888 C LD.

3. h$t is *e$nt %& @ GA

= field rogrammable gate array (D7,=) is a rogrammable logicdevice that su orts im lementation of relatively large logic circuits" D7,=scan be used to im lement a logic circuit with more than 2*0*** gateswhereas a #7$ can im lement circuits of u to about 2*0*** equivalentgates" D7,=s are quite different from #7$ s because D7,=s do notcontain =8 or O lanes" &nstead0 they rovide logic blocks forim lementation of the required functions"


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A"Gi#e the gener$! str('t(re f @ GA "

18. h$t $re the "ifferent ' **er'i$! @ GA +r "('tsManufacturer D7,= roducts www $ocator =ctel =ct 902 and ;0MK0SK www"actel"com=ltera D$4K ***0P*** and 9*k =74K 2*k www"altera"com=tmel =T ***0 =TH*k www"ateml"com$ucent O #= 902 and ; www"lucent"comNuick$ogic =S 902 and ; www"quicklogic"comVantis VD& www"vantis"comKilin5 K#;***0K#H***0K#


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1,. h$t $re the $++!i'$ti ns f ALi" #ontrol logic a lication

ii" &n ut.Out utiii" ata' ath logic

10. h$t is finite st$te *$'hine #$: means #onfigurable $ogic :lock"

13. Define *e$!& *$'hine&n mealy machine0 out ut may change with the change in the in utasynchronously"

17. Define * re *$'hine&n moore machine0 out ut can be changed when state is changed"

)8. h$t is DLV%S %ardware descri tion $anguage"

)1. h$t is V SICVery %igh S ed &ntegrated #ircuits"

)). h$t $re the #$ri (s +er$t rs in V DLi" $ogical o erators

ii" elational o eratorsiii" Shift o eratorsiv" =dding o eratorsv" Multi lying o erators


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vi" Miscellaneous o erators

),. h$t $re the "$t$ t&+es $#$i!$%!e in V DLi" Scalar ty e

ii" #om osite ty eiii" =ccess ty eiv" Dile ty e

)4. h$t $re the t&+es f s(%+r gr$*sDunctions and 7rocedures are ty es of sub rograms"

)0. h$t is the (se f $'t($!=ctual in a sub rogram call is used to ass the values from and to a

sub rogram"


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UNIT 0V DL

1= rite the $'r n&* f r V DLV DL is an acronym for V SIC %ardware escri tion $anguage

(V%S is an acronym for Very %igh S eed &ntegrated #ircuits)"

)= h$t $re the "ifferent t&+es f * "e!ing V DL9) Structural modeling2) ata flow modeling;) behavioral modelingH) Mi5ed ty e of modeling

,= h$t is +$';$ges $n" 5h$t is the (se f these +$';$ges= ackage declaration is used to store a set of common declaration

such as com onents ty es rocedures and functions these declaration canthen be im orted into others design units using a use caluse"

4= h$t is #$ri$%!e '!$ss ?gi#e e/$*+!e f r #$ri$%!e=n ob?ect of variable class can also hold a single value of a given ty e

0 %owever in this case different values can be assigned to a variable atdifferent time"45Bvariable ssB integerE

0= N$*e t5 s(%+r gr$*s $n" gi#e the "ifferen'e %et5een these t5 .9) Dunction 2) rocedureOnly one out ut is ossible in function""Many out uts ossible using rocedure

6= h$t is s(%+r gr$* O#er! $"ing&f two or more sub rogram to be e5ecuted in a same name"

overloading of sub rogram should be erformed"

2= 5rite the V DL ' "ing f r $ se (enti$! st$te*ent


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architecture dff of dff is begin

rocess(clk0d) begin

if clk> event and clk > 9> thenqR dEend rocessE

endE

3= h$t $re the "ifferent ;in"s f The test %en'hStimulus onlyDull testbenchSimulator s ecific%ybrid testbench

Dast testbench

7= h$t is M re @SMThe out ut of a Moore finite state machine(DSM) de ends only on the

state and not on its in uts" This ty e of behaviour can be modeled using asingle rocess with the case statement that switches on the state value"

18= rite the test%en'h f r $n" g$teentity testand2 isend entityarchitecture io of testand2 issignal a0b0cBstdQlogicE

beging9Bentity work"and2(e52) ort ma (a0b0c)aR > *> 0> 9> after 9** nsE

bR > *> 0 J9> after 9


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1,. h$t $re the t5 *eth "s t gener$te sti*(!(s #$!(esi" To create waveforms and a ly stimulus at discrete time intervals"

ii" To generate stimulus based on the state of the entity or out ut of theentity"

14. Differenti$te %et5een 'h$nne!e" H 'h$nne! !ess g$te $rr$&.#hanneled ,ate =rray #hannel less ,ate =rray9" Only the interconnect is customi!ed only the to few mask layers arecustomi!ed"2" The interconnect uses redefined s aces between rows of base cells" 8o

redefined areas are set aside for routing between cells";" outing is done using the s aces outing is done using the area oftransistors unused"H" $ogic density is less $ogic density is higher"

10. h$t is $ @ GA= field rogrammable gate array (D7,=) is a rogrammable logic devicethat su orts im lementation of relatively large logic circuits" D7,=s can beused to im lement a logic circuit with more than 2*0*** gates whereas a#7$ can im lement circuits of u to about 2*0*** equivalent gates"

16. h$t $re the "ifferent *eth "s f +r gr$**ing f ALsThe rogramming of 7=$s is done in three main waysB

Dusible links V - erasable 47 OM 447 OM (427 OM) - 4lectrically 4rasable 7rogrammable OM

12. h$t is $n $ntif(se=n antifuse is normally high resistance (U9**M3)" On a lication ofa ro riate

rogramming voltages0 the antifuse is changed ermanently to a low'resistancestructure (2**'


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egister Transfer'level ( T$) $ogic level #ircuit level

17. h$t $re *$'r sThe logic cells in a gate'array library are often called macros"

)8. h$t $re r gr$**$%!e Inter' nne'ts&n a 7=$0 the device is rogrammed by changing the characteristics if theswitching element" =n alternative would be to rogram the routing"

)1. Gi#e the ste+s inASIC "esign f! 5.a" esign entry

b" $ogic synthesisSystem artitioning

c" 7relayout simulation"d" Dloor lanninge" 7lacementf" outingg" 45traction

)). rite n tes n f(n'ti n$!it& testsDunctionality tests verify that the chi erforms its intended function" Thesetests assert that all the gates in the chi 0 acting in concert0 achieve a desiredfunction" These tests are usually used early in the design cycle to verify thefunctionality of the circuit"

),. rite n tes n *$n(f$'t(ring testsManufacturing tests verify that every gate and register in the chi functionscorrectly" These tests are used after the chi is manufactured to verify thatthe silicon is intact"

)4. Menti n the "efe'ts th$t ''(r in $ 'hi+a) layer'to'layer shorts

b) discontinuous wiresc) thin'o5ide shorts to substrate or well

)0. Gi#e s *e 'ir'(it *$!$"ies t #er' *e the "efe'tsa" nodes shorted to ower or ground

b" nodes shorted to each other


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c" in uts floating.out uts disconnected

2 Marks Ques Ans. of VLSI

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