2 EFM32WG Reference Manual TM - Silicon Labs Reference Manual Energy Friendly Microcontrollers

EFM32WG Reference Manual

The EFM32 Wonder Gecko MCUs are the worlds most energy-friendly microcontrollers.The EFM32WG offers unmatched performance and ultra low power consumption in bothactive and sleep modes. EFM32WG devices consume as little as 0.65 A in Stop modeand 225 A/MHz in Run mode. It also features autonomous peripherals, high overall chipand analog integration, and the performance of the industry standard 32-bit ARM Cortex-M4 processor, making it perfect for battery-powered systems and systems with high-per-formance, low-energy requirements.

EFM32WG applications include the following:

KEY FEATURES

ARM Cortex-M4 at 48 MHz Ultra low power operation

0.65 A current in Stop (EM3), withCRYOTIMER and RAM retention

63 A/MHz in EM1 225 A/MHz in Run mode (EM0)

Fast wake-up time of 2 us Hardware cryptography (AES) Up to 256 kB of Flash and 32 kB of RAM Smart metering

Water metering Gas metering

Industrial and home automation Alarm and security systems Health and fitness applications

32-bit bus

Lowest power mode with peripheral operational:

EM2 Deep SleepEM1 - Sleep EM4S - ShutoffEM0 - Active EM3 - Stop

Core / Memory

Flash Program Memory

RAM Memory

ARM CortexTM M4 processor with FPU and

MPU

Debug Interface with ETM

DMA Controller

Memory Protection Unit

Other

Hardware AES

Energy Management

Brown-Out Detector

Voltage Regulator

Voltage Comparator

Power-On Reset

Clock Management

High FrequencyRC Oscillator

Ultra Low Freq. RC Oscillator

Low Frequency Crystal Oscillator

Low FrequencyRC Oscillator

Auxiliary High Freq. RC Osc.

High Frequency Crystal Oscillator

Analog Interfaces

LCD Controller

Operational Amplifier

ADC

DAC

Analog Comparator

Backup Domain

Peripheral Reflex System

Serial Interfaces

UART

I2C

USB

I/O Ports Timers and Triggers

LESENSETimer/Counter

Low Energy Timer

Watchdog Timer

Back-Up RTC

External Interrupts

Pin Reset

External Bus Interface

General Purpose I/O

Pin Wakeup

TFT Driver

Pulse Counter

Real Time Counter

USART

Low Energy UARTTM

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Table of Contents1. Energy Friendly Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . 24

1.1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.2 EFM32WG Development . . . . . . . . . . . . . . . . . . . . . . . . . .24

2. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . .26

3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.4 Energy Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.5 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

3.6 Device Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4. System Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .374.3.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . .38

5. Memory and Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . 405.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .425.2.1 Bit-Banding. . . . . . . . . . . . . . . . . . . . . . . . . . . . .435.2.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455.2.3 Bus Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475.2.4 Access to Low Energy Peripherals (Asynchronous Registers) . . . . . . . . . . . .485.2.5 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505.2.6 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515.2.7 Device Information (DI) Page. . . . . . . . . . . . . . . . . . . . . . .52

6. DBG - Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 546.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .546.3.1 Debug Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .556.3.2 Embedded Trace Macrocell v3.5 (ETM) . . . . . . . . . . . . . . . . . . .556.3.3 Debug and EM2/EM3 . . . . . . . . . . . . . . . . . . . . . . . . .556.3.4 Debug Lock and Device Erase . . . . . . . . . . . . . . . . . . . . . .56

6.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

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6.5.1 AAP_CMD - Command Register . . . . . . . . . . . . . . . . . . . . .586.5.2 AAP_CMDKEY - Command Key Register . . . . . . . . . . . . . . . . . .586.5.3 AAP_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . .596.5.4 AAP_IDR - AAP Identification Register . . . . . . . . . . . . . . . . . . .59

7. MSC - Memory System Controller. . . . . . . . . . . . . . . . . . . . . . . 607.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .617.3.1 User Data (UD) Page Description . . . . . . . . . . . . . . . . . . . . .627.3.2 Lock Bits (LB) Page Description. . . . . . . . . . . . . . . . . . . . . .627.3.3 Device Information (DI) Page. . . . . . . . . . . . . . . . . . . . . . .627.3.4 Post-Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . .627.3.5 Erase and Write Operations . . . . . . . . . . . . . . . . . . . . . . .65

7.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

7.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .677.5.1 MSC_CTRL - Memory System Control Register . . . . . . . . . . . . . . . .677.5.2 MSC_READCTRL - Read Control Register . . . . . . . . . . . . . . . . .687.5.3 MSC_WRITECTRL - Write Control Register . . . . . . . . . . . . . . . . .697.5.4 MSC_WRITECMD - Write Command Register . . . . . . . . . . . . . . . .707.5.5 MSC_ADDRB - Page Erase/Write Address Buffer . . . . . . . . . . . . . . .717.5.6 MSC_WDATA - Write Data Register . . . . . . . . . . . . . . . . . . . .717.5.7 MSC_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . .727.5.8 MSC_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . .737.5.9 MSC_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . .737.5.10 MSC_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . .747.5.11 MSC_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . .747.5.12 MSC_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . . .757.5.13 MSC_CMD - Command Register . . . . . . . . . . . . . . . . . . . .767.5.14 MSC_CACHEHITS - Cache Hits Performance Counter . . . . . . . . . . . . .767.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter . . . . . . . . . . .777.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase . . . . . . . . . . . . . .777.5.17 MSC_MASSLOCK - Mass Erase Lock Register . . . . . . . . . . . . . . .78

8. DMA - DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 798.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

8.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .828.4.1 Channel Select Configuration . . . . . . . . . . . . . . . . . . . . . .828.4.2 DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .838.4.3 Channel Control Data Structure . . . . . . . . . . . . . . . . . . . . . .968.4.4 Looped Transfers . . . . . . . . . . . . . . . . . . . . . . . . .1068.4.5 2D Copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078.4.6 Interaction with the EMU . . . . . . . . . . . . . . . . . . . . . . .1078.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .1088.4.8 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . .108


8.5 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108.6.1 DMA_STATUS - DMA Status Registers . . . . . . . . . . . . . . . . . . 1108.6.2 DMA_CONFIG - DMA Configuration Register . . . . . . . . . . . . . . . . 1118.6.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register . . . . . . . . . 1118.6.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register . . . .1128.6.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register . . . . . . . . 1138.6.6 DMA_CHSWREQ - Channel Software Request Register . . . . . . . . . . . . 1148.6.7 DMA_CHUSEBURSTS - Channel Useburst Set Register . . . . . . . . . . . . 1158.6.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register . . . . . . . . . . . 1178.6.9 DMA_CHREQMASKS - Channel Request Mask Set Register . . . . . . . . . .1188.6.10 DMA_CHREQMASKC - Channel Request Mask Clear Register . . . . . . . . .1198.6.11 DMA_CHENS - Channel Enable Set Register . . . . . . . . . . . . . . .1208.6.12 DMA_CHENC - Channel Enable Clear Register . . . . . . . . . . . . . .1218.6.13 DMA_CHALTS - Channel Alternate Set Register . . . . . . . . . . . . . .1228.6.14 DMA_CHALTC - Channel Alternate Clear Register . . . . . . . . . . . . .1238.6.15 DMA_CHPRIS - Channel Priority Set Register . . . . . . . . . . . . . . . 1248.6.16 DMA_CHPRIC - Channel Priority Clear Register . . . . . . . . . . . . . .1258.6.17 DMA_ERRORC - Bus Error Clear Register . . . . . . . . . . . . . . . .1268.6.18 DMA_CHREQSTATUS - Channel Request Status . . . . . . . . . . . . . . 1278.6.19 DMA_CHSREQSTATUS - Channel Single Request Status . . . . . . . . . . . 1298.6.20 DMA_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .1318.6.21 DMA_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . 1338.6.22 DMA_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 1348.6.23 DMA_IEN - Interrupt Enable register . . . . . . . . . . . . . . . . . .1358.6.24 DMA_CTRL - DMA Control Register . . . . . . . . . . . . . . . . . .1368.6.25 DMA_RDS - DMA Retain Descriptor State . . . . . . . . . . . . . . . .1378.6.26 DMA_LOOP0 - Channel 0 Loop Register . . . . . . . . . . . . . . . . . 1388.6.27 DMA_LOOP1 - Channel 1 Loop Register . . . . . . . . . . . . . . . . . 1398.6.28 DMA_RECT0 - Channel 0 Rectangle Register . . . . . . . . . . . . . . . 1398.6.29 DMA_CHx_CTRL - Channel Control Register . . . . . . . . . . . . . . .140

9. RMU - Reset Management Unit . . . . . . . . . . . . . . . . . . . . . . . . 1449.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1459.3.1 RMU_RSTCAUSE Register . . . . . . . . . . . . . . . . . . . . . .1469.3.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . .1479.3.3 Brown-Out Detector Reset (BOD) . . . . . . . . . . . . . . . . . . . .1479.3.4 RESETn Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . 1479.3.5 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 1489.3.6 Lockup Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489.3.7 System Reset Request . . . . . . . . . . . . . . . . . . . . . . . . 1489.3.8 EM4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489.3.9 EM4 Wakeup Reset . . . . . . . . . . . . . . . . . . . . . . . . . 148

9.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

9.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 149


9.5.1 RMU_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . . 1499.5.2 RMU_RSTCAUSE - Reset Cause Register . . . . . . . . . . . . . . . .1509.5.3 RMU_CMD - Command Register . . . . . . . . . . . . . . . . . . . . 151

10. EMU - Energy Management Unit . . . . . . . . . . . . . . . . . . . . . . . 15210.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .15310.3.1 Energy Modes . . . . . . . . . . . . . . . . . . . . . . . . . .15410.3.2 Entering a Low Energy Mode . . . . . . . . . . . . . . . . . . . . .15710.3.3 Leaving a Low Energy Mode . . . . . . . . . . . . . . . . . . . . .15810.3.4 Backup Power Domain . . . . . . . . . . . . . . . . . . . . . . .159

10.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

10.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .16410.5.1 EMU_CTRL - Control Register . . . . . . . . . . . . . . . . . . . .16410.5.2 EMU_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . .16510.5.3 EMU_AUXCTRL - Auxiliary Control Register . . . . . . . . . . . . . . .16510.5.4 EMU_EM4CONF - Energy Mode 4 Configuration Register . . . . . . . . . . . 16610.5.5 EMU_BUCTRL - Backup Power configuration register . . . . . . . . . . . .16710.5.6 EMU_PWRCONF - Power Connection Configuration Register . . . . . . . . . . 16810.5.7 EMU_BUINACT - Backup Mode Inactive Configuration Register . . . . . . . . . 16910.5.8 EMU_BUACT - Backup mode active configuration register . . . . . . . . . . . 17010.5.9 EMU_STATUS - Status register . . . . . . . . . . . . . . . . . . . . 17110.5.10 EMU_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . . 17110.5.11 EMU_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .17210.5.12 EMU_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .17210.5.13 EMU_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .17310.5.14 EMU_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .17310.5.15 EMU_BUBODBUVINCAL - BU_VIN Backup BOD calibration . . . . . . . . . . 17410.5.16 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration . . . . .174

11. CMU - Clock Management Unit . . . . . . . . . . . . . . . . . . . . . . .17511.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .17611.3.1 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 17711.3.2 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . .17911.3.3 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . .18111.3.4 Configuration For Operating Frequencies . . . . . . . . . . . . . . . . .18511.3.5 Output Clock on a Pin . . . . . . . . . . . . . . . . . . . . . . . . 18511.3.6 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

11.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

11.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .18711.5.1 CMU_CTRL - CMU Control Register . . . . . . . . . . . . . . . . . .18711.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register . . . . . .19011.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register . . . . . 191


11.5.4 CMU_HFRCOCTRL - HFRCO Control Register . . . . . . . . . . . . . .19211.5.5 CMU_LFRCOCTRL - LFRCO Control Register . . . . . . . . . . . . . . . 19311.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register . . . . . . . . . . .19411.5.7 CMU_CALCTRL - Calibration Control Register . . . . . . . . . . . . . . . 19511.5.8 CMU_CALCNT - Calibration Counter Register . . . . . . . . . . . . . . . 19611.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register . . . . . . . . 19711.5.10 CMU_CMD - Command Register . . . . . . . . . . . . . . . . . . . 19811.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register . . . . . . . . . . . 19911.5.12 CMU_STATUS - Status Register . . . . . . . . . . . . . . . . . . .20111.5.13 CMU_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . 20311.5.14 CMU_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .20411.5.15 CMU_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .20511.5.16 CMU_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .20611.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 . . . . .20711.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 . . . . 20811.5.19 CMU_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . . 21011.5.20 CMU_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . . . 21111.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) . . . . 21211.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) . . . . 21211.5.23 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) . . . . .21311.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) . . . . .21511.5.25 CMU_PCNTCTRL - PCNT Control Register . . . . . . . . . . . . . . .21611.5.26 CMU_LCDCTRL - LCD Control Register . . . . . . . . . . . . . . . .21711.5.27 CMU_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . . 21811.5.28 CMU_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . . 219

12. WDOG - Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . .22012.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .22012.3.1 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . .22112.3.2 Debug Functionality . . . . . . . . . . . . . . . . . . . . . . . .22112.3.3 Energy Mode Handling . . . . . . . . . . . . . . . . . . . . . . .22112.3.4 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . 221

12.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .22212.5.1 WDOG_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . . 22212.5.2 WDOG_CMD - Command Register (Async Reg) . . . . . . . . . . . . . .22412.5.3 WDOG_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . .225

13. PRS - Peripheral Reflex System . . . . . . . . . . . . . . . . . . . . . . . 22613.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .22613.3.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . .22713.3.2 Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . 22713.3.3 Producers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228


13.3.4 Consumers . . . . . . . . . . . . . . . . . . . . . . . . . . .23013.3.5 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

13.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

13.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .23213.5.1 PRS_SWPULSE - Software Pulse Register . . . . . . . . . . . . . . . . 23213.5.2 PRS_SWLEVEL - Software Level Register . . . . . . . . . . . . . . . .23313.5.3 PRS_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . .23413.5.4 PRS_CHx_CTRL - Channel Control Register . . . . . . . . . . . . . . .235

14. EBI - External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . .24014.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .24114.3.1 Non-Multiplexed 8-Bit Data, 8-Bit Address Mode . . . . . . . . . . . . . . . 24314.3.2 Multiplexed 16-bit Data, 16-bit Address Mode . . . . . . . . . . . . . . . . 24414.3.3 Multiplexed 8-Bit Data, 24-Bit Address Mode . . . . . . . . . . . . . . . . 24514.3.4 Non-Multiplexed 16-Bit Data, N-Bit Address Mode . . . . . . . . . . . . . .24614.3.5 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . .24714.3.6 Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . 25014.3.7 Prefetch Unit and Write Buffer . . . . . . . . . . . . . . . . . . . . . 25114.3.8 Strobe Length . . . . . . . . . . . . . . . . . . . . . . . . . .25214.3.9 Bus Turn-Around and Idle Cycles . . . . . . . . . . . . . . . . . . . . 25314.3.10 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25414.3.11 Data Access Width . . . . . . . . . . . . . . . . . . . . . . . .25514.3.12 Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . .25614.3.13 WAIT/ARDY . . . . . . . . . . . . . . . . . . . . . . . . . .25714.3.14 NAND Flash Support . . . . . . . . . . . . . . . . . . . . . . .25814.3.15 Error Correction Code . . . . . . . . . . . . . . . . . . . . . . .26414.3.16 TFT Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . 26714.3.17 Alpha Blending and Masking . . . . . . . . . . . . . . . . . . . . . 27114.3.18 Direct Drive Timing . . . . . . . . . . . . . . . . . . . . . . . .27414.3.19 Control Signal Polarity . . . . . . . . . . . . . . . . . . . . . . .27614.3.20 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 27614.3.21 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .27714.3.22 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . 277

14.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

14.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .28014.5.1 EBI_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . . 28014.5.2 EBI_ADDRTIMING - Address Timing Register . . . . . . . . . . . . . . . 28314.5.3 EBI_RDTIMING - Read Timing Register . . . . . . . . . . . . . . . . . 28414.5.4 EBI_WRTIMING - Write Timing Register . . . . . . . . . . . . . . . . . 28514.5.5 EBI_POLARITY - Polarity Register . . . . . . . . . . . . . . . . . . . 28614.5.6 EBI_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . . . 28814.5.7 EBI_ADDRTIMING1 - Address Timing Register 1 . . . . . . . . . . . . . . 29014.5.8 EBI_RDTIMING1 - Read Timing Register 1 . . . . . . . . . . . . . . . . 29114.5.9 EBI_WRTIMING1 - Write Timing Register 1 . . . . . . . . . . . . . . . . 29214.5.10 EBI_POLARITY1 - Polarity Register 1 . . . . . . . . . . . . . . . . .293


14.5.11 EBI_ADDRTIMING2 - Address Timing Register 2 . . . . . . . . . . . . .29414.5.12 EBI_RDTIMING2 - Read Timing Register 2 . . . . . . . . . . . . . . .29514.5.13 EBI_WRTIMING2 - Write Timing Register 2 . . . . . . . . . . . . . . .29614.5.14 EBI_POLARITY2 - Polarity Register 2 . . . . . . . . . . . . . . . . .29714.5.15 EBI_ADDRTIMING3 - Address Timing Register 3 . . . . . . . . . . . . .29814.5.16 EBI_RDTIMING3 - Read Timing Register 3 . . . . . . . . . . . . . . .29914.5.17 EBI_WRTIMING3 - Write Timing Register 3 . . . . . . . . . . . . . . .30014.5.18 EBI_POLARITY3 - Polarity Register 3 . . . . . . . . . . . . . . . . .30114.5.19 EBI_PAGECTRL - Page Control Register . . . . . . . . . . . . . . . .30314.5.20 EBI_NANDCTRL - NAND Control Register . . . . . . . . . . . . . . . . 30414.5.21 EBI_CMD - Command Register . . . . . . . . . . . . . . . . . . .30514.5.22 EBI_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . 30614.5.23 EBI_ECCPARITY - ECC Parity register . . . . . . . . . . . . . . . . . 30714.5.24 EBI_TFTCTRL - TFT Control Register . . . . . . . . . . . . . . . . .30814.5.25 EBI_TFTSTATUS - TFT Status Register . . . . . . . . . . . . . . . .31014.5.26 EBI_TFTFRAMEBASE - TFT Frame Base Register . . . . . . . . . . . . . 31014.5.27 EBI_TFTSTRIDE - TFT Stride Register . . . . . . . . . . . . . . . . . 31114.5.28 EBI_TFTSIZE - TFT Size Register . . . . . . . . . . . . . . . . . .31114.5.29 EBI_TFTHPORCH - TFT Horizontal Porch Register . . . . . . . . . . . . . 31214.5.30 EBI_TFTVPORCH - TFT Vertical Porch Register . . . . . . . . . . . . . . 31314.5.31 EBI_TFTTIMING - TFT Timing Register . . . . . . . . . . . . . . . . . 31414.5.32 EBI_TFTPOLARITY - TFT Polarity Register . . . . . . . . . . . . . . .31514.5.33 EBI_TFTDD - TFT Direct Drive Data Register . . . . . . . . . . . . . . . 31614.5.34 EBI_TFTALPHA - TFT Alpha Blending Register . . . . . . . . . . . . . . 31614.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register . . . . . . . . . . . . . . . . . 31714.5.36 EBI_TFTPIXEL1 - TFT Pixel 1 Register . . . . . . . . . . . . . . . . . 31714.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register . . . . . . . . . . 31814.5.38 EBI_TFTMASK - TFT Masking Register . . . . . . . . . . . . . . . . . 31814.5.39 EBI_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .31914.5.40 EBI_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . 32014.5.41 EBI_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 32114.5.42 EBI_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . 322

15. USB - Universal Serial Bus Controller. . . . . . . . . . . . . . . . . . . . . 32315.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

15.3 USB System Description . . . . . . . . . . . . . . . . . . . . . . . . . 32515.3.1 USB Initialization . . . . . . . . . . . . . . . . . . . . . . . . .32515.3.2 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . .32615.3.3 PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33115.3.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . 33115.3.5 Interrupts and PRS. . . . . . . . . . . . . . . . . . . . . . . . . 33115.3.6 USB in EM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

15.4 USB Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . 33215.4.1 Overview: Programming the Core . . . . . . . . . . . . . . . . . . . . 33215.4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . .33615.4.3 Host Programming Model . . . . . . . . . . . . . . . . . . . . . .34015.4.4 Device Programming Model. . . . . . . . . . . . . . . . . . . . . . 372


15.4.5 OTG Revision 1.3 Programming Model . . . . . . . . . . . . . . . . . . 41015.4.6 OTG Revision 2.0 Programming Model . . . . . . . . . . . . . . . . . . 41315.4.7 FIFO RAM Allocation . . . . . . . . . . . . . . . . . . . . . . . . 42015.4.8 Suspend/Resume and SRP . . . . . . . . . . . . . . . . . . . . . . 42915.4.9 Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . 438

15.5 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

15.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .44315.6.1 USB_CTRL - System Control Register . . . . . . . . . . . . . . . . . . 44315.6.2 USB_STATUS - System Status Register . . . . . . . . . . . . . . . . . 44415.6.3 USB_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . 44415.6.4 USB_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . 44515.6.5 USB_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 44515.6.6 USB_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . .44615.6.7 USB_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . .44615.6.8 USB_GOTGCTL - OTG Control and Status Register . . . . . . . . . . . . . 44715.6.9 USB_GOTGINT - OTG Interrupt Register . . . . . . . . . . . . . . . . . 44915.6.10 USB_GAHBCFG - AHB Configuration Register . . . . . . . . . . . . . .45115.6.11 USB_GUSBCFG - USB Configuration Register . . . . . . . . . . . . . .45315.6.12 USB_GRSTCTL - Reset Register . . . . . . . . . . . . . . . . . . . 45515.6.13 USB_GINTSTS - Interrupt Register . . . . . . . . . . . . . . . . . .45715.6.14 USB_GINTMSK - Interrupt Mask Register . . . . . . . . . . . . . . . . 46115.6.15 USB_GRXSTSR - Receive Status Debug Read Register . . . . . . . . . . . 46315.6.16 USB_GRXSTSP - Receive Status Read and Pop Register . . . . . . . . . .46515.6.17 USB_GRXFSIZ - Receive FIFO Size Register . . . . . . . . . . . . . . . 46715.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register . . . . . . . . . 46715.6.19 USB_GNPTXSTS - Non-periodic Transmit FIFO/Queue Status Register . . . . . . 46815.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register . . . . . . . . . .46915.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register . . . . . . . . .46915.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register . . . . . .47015.6.23 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register . . . . . .47115.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register . . . . . .47215.6.25 USB_DIEPTXF4 - Device IN Endpoint Transmit FIFO 4 Size Register . . . . . .47315.6.26 USB_DIEPTXF5 - Device IN Endpoint Transmit FIFO 5 Size Register . . . . . .47415.6.27 USB_DIEPTXF6 - Device IN Endpoint Transmit FIFO 6 Size Register . . . . . .47515.6.28 USB_HCFG - Host Configuration Register . . . . . . . . . . . . . . . . 47615.6.29 USB_HFIR - Host Frame Interval Register . . . . . . . . . . . . . . . . 47715.6.30 USB_HFNUM - Host Frame Number/Frame Time Remaining Register . . . . . .47815.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register . . . . . .47915.6.32 USB_HAINT - Host All Channels Interrupt Register . . . . . . . . . . . . . 48015.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register . . . . . . . . .48015.6.34 USB_HPRT - Host Port Control and Status Register . . . . . . . . . . . .48115.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register . . . . . . . . . . 48415.6.36 USB_HCx_INT - Host Channel x Interrupt Register . . . . . . . . . . . . . 48615.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register . . . . . . . . .48815.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register . . . . . . . . . . . 48915.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register . . . . . . . .49015.6.40 USB_DCFG - Device Configuration Register . . . . . . . . . . . . . . .49115.6.41 USB_DCTL - Device Control Register . . . . . . . . . . . . . . . . .493


15.6.42 USB_DSTS - Device Status Register . . . . . . . . . . . . . . . . . . 49515.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register . . . . . . 49615.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register . . . .49715.6.45 USB_DAINT - Device All Endpoints Interrupt Register . . . . . . . . . . . . 49815.6.46 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register . . . . . . . .50015.6.47 USB_DVBUSDIS - Device VBUS Discharge Time Register . . . . . . . . . .50115.6.48 USB_DVBUSPULSE - Device VBUS Pulsing Time Register . . . . . . . . . . 50215.6.49 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register . . .50215.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register . . . . . . . . . . . 50315.6.51 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register . . . . . . . . . . . 50515.6.52 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register . . . . . . . .50715.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register . . . . . . 50815.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register . . . .50815.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register . . . . . . . . .50915.6.56 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register . . . . . . . . .51115.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register . . . . . . .51315.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register . . . . . 51415.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register . . .51415.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register . . . . . . . . .51515.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register . . . . . . . . .51715.6.62 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register . . . . . . .51915.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register . . . . . 52015.6.64 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register . . . . . . . .52115.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register . . . . . . . .52315.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register . . . . . . 52515.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register . . .52615.6.68 USB_PCGCCTL - Power and Clock Gating Control Register . . . . . . . . . . 52715.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO . . . . . . . . . . . . . 52815.6.70 USB_FIFO1Dx - Device EP 1/Host Channel 1 FIFO . . . . . . . . . . . . . 52815.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO . . . . . . . . . . . . . 52915.6.72 USB_FIFO3Dx - Device EP 3/Host Channel 3 FIFO . . . . . . . . . . . . . 52915.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO . . . . . . . . . . . . . 53015.6.74 USB_FIFO5Dx - Device EP 5/Host Channel 5 FIFO . . . . . . . . . . . . . 53015.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO . . . . . . . . . . . . . 53115.6.76 USB_FIFO7Dx - Host Channel 7 FIFO . . . . . . . . . . . . . . . . .53115.6.77 USB_FIFO8Dx - Host Channel 8 FIFO . . . . . . . . . . . . . . . . .53215.6.78 USB_FIFO9Dx - Host Channel 9 FIFO . . . . . . . . . . . . . . . . .53215.6.79 USB_FIFO10Dx - Host Channel 10 FIFO . . . . . . . . . . . . . . . .53315.6.80 USB_FIFO11Dx - Host Channel 11 FIFO . . . . . . . . . . . . . . . .53315.6.81 USB_FIFO12Dx - Host Channel 12 FIFO . . . . . . . . . . . . . . . .53415.6.82 USB_FIFO13Dx - Host Channel 13 FIFO . . . . . . . . . . . . . . . .53415.6.83 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB) . . . . . 535

16. I2C - Inter-Integrated Circuit Interface . . . . . . . . . . . . . . . . . . . . . 53616.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536

16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536

16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .53716.3.1 I2C-Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . 538


16.3.2 Enable and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 54216.3.3 Safely Disabling and Changing Slave Configuration. . . . . . . . . . . . . . 54216.3.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . .54316.3.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54416.3.6 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54516.3.7 Master Operation . . . . . . . . . . . . . . . . . . . . . . . . .54516.3.8 Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . .55316.3.9 Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 55316.3.10 Transfer Automation . . . . . . . . . . . . . . . . . . . . . . . . 55716.3.11 Using 10-Bit Addresses . . . . . . . . . . . . . . . . . . . . . . . 55816.3.12 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 55816.3.13 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . .56016.3.14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .56016.3.15 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . .560

16.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

16.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .56116.5.1 I2Cn_CTRL - Control Register . . . . . . . . . . . . . . . . . . . .56116.5.2 I2Cn_CMD - Command Register . . . . . . . . . . . . . . . . . . .56416.5.3 I2Cn_STATE - State Register . . . . . . . . . . . . . . . . . . . . . 56516.5.4 I2Cn_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . 56616.5.5 I2Cn_CLKDIV - Clock Division Register . . . . . . . . . . . . . . . . .56716.5.6 I2Cn_SADDR - Slave Address Register . . . . . . . . . . . . . . . . .56716.5.7 I2Cn_SADDRMASK - Slave Address Mask Register . . . . . . . . . . . . . 56816.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) . . . . . . . . 56816.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register . . . . . . . . . . . .56916.5.10 I2Cn_TXDATA - Transmit Buffer Data Register . . . . . . . . . . . . . .56916.5.11 I2Cn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .57016.5.12 I2Cn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .57216.5.13 I2Cn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .57416.5.14 I2Cn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . 57616.5.15 I2Cn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . . 577

17. USART - Universal Synchronous Asynchronous Receiver/Transmitter . . . . . . . .57817.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578

17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579

17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .58017.3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . .58117.3.2 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . 58217.3.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . 59717.3.4 PRS-Triggered Transmissions . . . . . . . . . . . . . . . . . . . . . 60317.3.5 PRS RX Input . . . . . . . . . . . . . . . . . . . . . . . . . .60417.3.6 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . .60417.3.7 Transmission Delay . . . . . . . . . . . . . . . . . . . . . . . .60417.3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60517.3.9 IrDA Modulator/Demodulator . . . . . . . . . . . . . . . . . . . . .606

17.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

17.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .608


17.5.1 USARTn_CTRL - Control Register . . . . . . . . . . . . . . . . . . . 60817.5.2 USARTn_FRAME - USART Frame Format Register . . . . . . . . . . . . . 61317.5.3 USARTn_TRIGCTRL - USART Trigger Control register . . . . . . . . . . . . 61517.5.4 USARTn_CMD - Command Register . . . . . . . . . . . . . . . . . .61617.5.5 USARTn_STATUS - USART Status Register . . . . . . . . . . . . . . .61717.5.6 USARTn_CLKDIV - Clock Control Register . . . . . . . . . . . . . . . . 61817.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) . . . .61917.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) . . . . . . . .61917.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) 62017.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) . . . .62117.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register . . . . . . . .62117.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register . . . .62217.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register . . . . . . . . . . . 62317.5.14 USARTn_TXDATA - TX Buffer Data Register . . . . . . . . . . . . . . . 62417.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register . . . . . . . 62517.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register . . . . . . . . . . . 62617.5.17 USARTn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . 62717.5.18 USARTn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . 62817.5.19 USARTn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . .62917.5.20 USARTn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . .63017.5.21 USARTn_IRCTRL - IrDA Control Register . . . . . . . . . . . . . . . . 63117.5.22 USARTn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . .63317.5.23 USARTn_INPUT - USART Input Register . . . . . . . . . . . . . . . .63417.5.24 USARTn_I2SCTRL - I2S Control Register . . . . . . . . . . . . . . . . 635

18. UART - Universal Asynchronous Receiver/ Transmitter . . . . . . . . . . . . . . 63718.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637

18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638

18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .638


18.5 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter . . . . . . . .63919.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639

19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640

19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .64119.3.1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . .64219.3.2 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . .64219.3.3 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . .64319.3.4 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 64319.3.5 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . 64519.3.6 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64819.3.7 Half Duplex Communication . . . . . . . . . . . . . . . . . . . . .64819.3.8 Transmission Delay . . . . . . . . . . . . . . . . . . . . . . . .64919.3.9 PRS RX Input . . . . . . . . . . . . . . . . . . . . . . . . . .64919.3.10 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . .64919.3.11 Pulse Generator / Pulse Extender . . . . . . . . . . . . . . . . . . .650


19.3.12 Register Access . . . . . . . . . . . . . . . . . . . . . . . . .650

19.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

19.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .65219.5.1 LEUARTn_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . 65219.5.2 LEUARTn_CMD - Command Register (Async Reg) . . . . . . . . . . . . .65519.5.3 LEUARTn_STATUS - Status Register . . . . . . . . . . . . . . . . . . 65619.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) . . . . . . . . . . .65719.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) . . . . . . . . .65719.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) . . . . . . . . . . 65819.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) . .65819.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) . . . . . .65919.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register . . . . . .65919.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) . . . . 66019.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) . . . . . . . . 66119.5.12 LEUARTn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . .66219.5.13 LEUARTn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . .66319.5.14 LEUARTn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . 66419.5.15 LEUARTn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . 66519.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) . . . . . . . . . 66619.5.17 LEUARTn_FREEZE - Freeze Register . . . . . . . . . . . . . . . . .66719.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . 66819.5.19 LEUARTn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . 66919.5.20 LEUARTn_INPUT - LEUART Input Register . . . . . . . . . . . . . . .670

20. TIMER - Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . .67120.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .671

20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672

20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .67320.3.1 Counter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 67320.3.2 Compare/Capture Channels . . . . . . . . . . . . . . . . . . . . .67920.3.3 Dead-Time Insertion Unit (TIMER0 only) . . . . . . . . . . . . . . . . .68720.3.4 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69020.3.5 Interrupts, DMA and PRS Output . . . . . . . . . . . . . . . . . . . . 69120.3.6 GPIO Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . 691

20.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

20.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .69320.5.1 TIMERn_CTRL - Control Register . . . . . . . . . . . . . . . . . . .69320.5.2 TIMERn_CMD - Command Register . . . . . . . . . . . . . . . . . .69520.5.3 TIMERn_STATUS - Status Register . . . . . . . . . . . . . . . . . .69620.5.4 TIMERn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . 69920.5.5 TIMERn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . .70020.5.6 TIMERn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . .70120.5.7 TIMERn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . 70220.5.8 TIMERn_TOP - Counter Top Value Register . . . . . . . . . . . . . . .70320.5.9 TIMERn_TOPB - Counter Top Value Buffer Register . . . . . . . . . . . . . 70320.5.10 TIMERn_CNT - Counter Value Register . . . . . . . . . . . . . . . . . 70420.5.11 TIMERn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . 705


20.5.12 TIMERn_CCx_CTRL - CC Channel Control Register . . . . . . . . . . . .70620.5.13 TIMERn_CCx_CCV - CC Channel Value Register . . . . . . . . . . . . .70920.5.14 TIMERn_CCx_CCVP - CC Channel Value Peek Register . . . . . . . . . . . 70920.5.15 TIMERn_CCx_CCVB - CC Channel Buffer Register . . . . . . . . . . . . . 71020.5.16 TIMERn_DTCTRL - DTI Control Register . . . . . . . . . . . . . . . .71120.5.17 TIMERn_DTTIME - DTI Time Control Register . . . . . . . . . . . . . .71320.5.18 TIMERn_DTFC - DTI Fault Configuration Register . . . . . . . . . . . . .71520.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register . . . . . . . . .71720.5.20 TIMERn_DTFAULT - DTI Fault Register . . . . . . . . . . . . . . . .71820.5.21 TIMERn_DTFAULTC - DTI Fault Clear Register . . . . . . . . . . . . . . 71920.5.22 TIMERn_DTLOCK - DTI Configuration Lock Register . . . . . . . . . . . .720

21. RTC - Real Time Counter . . . . . . . . . . . . . . . . . . . . . . . . .72121.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .721

21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .721

21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .72221.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . .72221.3.2 Compare Channels . . . . . . . . . . . . . . . . . . . . . . . .72321.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72421.3.4 DEBUGRUN . . . . . . . . . . . . . . . . . . . . . . . . . . . 72421.3.5 Using the RTC in EM3 . . . . . . . . . . . . . . . . . . . . . . .72421.3.6 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . 724

21.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

21.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .72521.5.1 RTC_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . . . 72521.5.2 RTC_CNT - Counter Value Register . . . . . . . . . . . . . . . . . .72621.5.3 RTC_COMP0 - Compare Value Register 0 (Async Reg) . . . . . . . . . . . . 72621.5.4 RTC_COMP1 - Compare Value Register 1 (Async Reg) . . . . . . . . . . . . 72721.5.5 RTC_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . 72721.5.6 RTC_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . 72821.5.7 RTC_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 72821.5.8 RTC_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . .72921.5.9 RTC_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . . .72921.5.10 RTC_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . . 730

22. BURTC - Backup Real Time Counter . . . . . . . . . . . . . . . . . . . . .73122.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .731

22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .731

22.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .73222.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . .73222.3.2 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . .73222.3.3 Compare Channel . . . . . . . . . . . . . . . . . . . . . . . . . 73222.3.4 PRS Sources . . . . . . . . . . . . . . . . . . . . . . . . . .73222.3.5 Debug Run . . . . . . . . . . . . . . . . . . . . . . . . . . .73322.3.6 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . .73322.3.7 Retention Registers . . . . . . . . . . . . . . . . . . . . . . . .73322.3.8 Backup Operation . . . . . . . . . . . . . . . . . . . . . . . . . 733


22.3.9 Backup Mode Timestamp . . . . . . . . . . . . . . . . . . . . . .73422.3.10 LFXO Failure Detection . . . . . . . . . . . . . . . . . . . . . . . 73422.3.11 Register Access . . . . . . . . . . . . . . . . . . . . . . . . .734

22.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .73622.5.1 BURTC_CTRL - Control Register . . . . . . . . . . . . . . . . . . .73622.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg) . . . . . . . . . 73822.5.3 BURTC_CNT - Counter Value Register . . . . . . . . . . . . . . . . .73822.5.4 BURTC_COMP0 - Counter Compare Value (Async Reg) . . . . . . . . . . .73922.5.5 BURTC_TIMESTAMP - Backup mode timestamp . . . . . . . . . . . . . . 73922.5.6 BURTC_LFXOFDET - LFXO . . . . . . . . . . . . . . . . . . . . . 74022.5.7 BURTC_STATUS - Status Register . . . . . . . . . . . . . . . . . . . 74122.5.8 BURTC_CMD - Command Register . . . . . . . . . . . . . . . . . .74122.5.9 BURTC_POWERDOWN - Retention RAM power-down Register . . . . . . . . . 74222.5.10 BURTC_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . 74222.5.11 BURTC_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . .74322.5.12 BURTC_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . .74322.5.13 BURTC_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . .74422.5.14 BURTC_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . 74422.5.15 BURTC_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . . 74522.5.16 BURTC_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . 74522.5.17 RETx_REG - Retention Register . . . . . . . . . . . . . . . . . . .746

23. LETIMER - Low Energy Timer . . . . . . . . . . . . . . . . . . . . . . . . 74723.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .747

23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .747

23.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .74823.3.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74823.3.2 Compare Registers . . . . . . . . . . . . . . . . . . . . . . . .74823.3.3 Top Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74823.3.4 Underflow Output Action . . . . . . . . . . . . . . . . . . . . . . . 75423.3.5 PRS Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 75623.3.6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75623.3.7 Using the LETIMER in EM3 . . . . . . . . . . . . . . . . . . . . . . 75823.3.8 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . 758

23.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

23.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .76023.5.1 LETIMERn_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . 76023.5.2 LETIMERn_CMD - Command Register . . . . . . . . . . . . . . . . .76223.5.3 LETIMERn_STATUS - Status Register . . . . . . . . . . . . . . . . .76223.5.4 LETIMERn_CNT - Counter Value Register . . . . . . . . . . . . . . . .76323.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) . . . . . . . . .76323.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) . . . . . . . . .76423.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) . . . . . . . . . .76423.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) . . . . . . . . . .76523.5.9 LETIMERn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . .76523.5.10 LETIMERn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . .766


23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . .76723.5.12 LETIMERn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . .76823.5.13 LETIMERn_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . 76923.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register . . . . . . . . . .77023.5.15 LETIMERn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . 771

24. PCNT - Pulse Counter . . . . . . . . . . . . . . . . . . . . . . . . . .77224.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772

24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772

24.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .77324.3.1 Pulse Counter Modes . . . . . . . . . . . . . . . . . . . . . . . . 77324.3.2 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . .77524.3.3 Auxiliary Counter . . . . . . . . . . . . . . . . . . . . . . . . .77524.3.4 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . 77624.3.5 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . .77624.3.6 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .77624.3.7 Edge Polarity . . . . . . . . . . . . . . . . . . . . . . . . . .77624.3.8 PRS S0IN and S1IN Input . . . . . . . . . . . . . . . . . . . . . .77624.3.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

24.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

24.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .77924.5.1 PCNTn_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . . 77924.5.2 PCNTn_CMD - Command Register (Async Reg) . . . . . . . . . . . . . .78124.5.3 PCNTn_STATUS - Status Register . . . . . . . . . . . . . . . . . . . 78124.5.4 PCNTn_CNT - Counter Value Register . . . . . . . . . . . . . . . . .78224.5.5 PCNTn_TOP - Top Value Register . . . . . . . . . . . . . . . . . . . 78224.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) . . . . . . . . . . .78324.5.7 PCNTn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . 78324.5.8 PCNTn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . 78424.5.9 PCNTn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . 78524.5.10 PCNTn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . 78624.5.11 PCNTn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . . 78724.5.12 PCNTn_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . .78824.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . 78824.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register . . . . . . . . . . . .78924.5.15 PCNTn_INPUT - PCNT Input Register . . . . . . . . . . . . . . . . .790

25. LESENSE - Low Energy Sensor Interface . . . . . . . . . . . . . . . . . . .79225.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .792

25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .792

25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .79325.3.1 Channel Configuration . . . . . . . . . . . . . . . . . . . . . . .79425.3.2 Scan Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 79525.3.3 Sensor Timing . . . . . . . . . . . . . . . . . . . . . . . . . .79625.3.4 Sensor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . 79725.3.5 Sensor Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 79925.3.6 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . .800


25.3.7 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80325.3.8 DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . .80425.3.9 ACMP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 80425.3.10 ACMP and DAC Duty Cycling. . . . . . . . . . . . . . . . . . . . . 80425.3.11 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . .80425.3.12 PRS Output. . . . . . . . . . . . . . . . . . . . . . . . . . . 80425.3.13 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80525.3.14 Application Examples . . . . . . . . . . . . . . . . . . . . . . .805

25.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

25.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .81225.5.1 LESENSE_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . 81225.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg) . . . . . . . . . . 81525.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) . . . . . . . . . 81725.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg) . . . . . . . . .82025.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg) . . . . . . . . . .82325.5.6 LESENSE_CMD - Command Register . . . . . . . . . . . . . . . . . . 82425.5.7 LESENSE_CHEN - Channel enable Register (Async Reg) . . . . . . . . . . . 82425.5.8 LESENSE_SCANRES - Scan result register (Async Reg) . . . . . . . . . . .82525.5.9 LESENSE_STATUS - Status Register (Async Reg) . . . . . . . . . . . . .82625.5.10 LESENSE_PTR - Result buffer pointers (Async Reg) . . . . . . . . . . . .82725.5.11 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads) . . 82725.5.12 LESENSE_CURCH - Current channel index (Async Reg) . . . . . . . . . . . 82825.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg) . . . . . . . . .82825.5.14 LESENSE_SENSORSTATE - Decoder input register (Async Reg) . . . . . . . . 82925.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg) . . . . . . . 83025.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg) . . . . . 83425.5.17 LESENSE_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . .83725.5.18 LESENSE_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . 83925.5.19 LESENSE_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . .84125.5.20 LESENSE_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . 84325.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . 84525.5.22 LESENSE_ROUTE - I/O Routing Register (Async Reg) . . . . . . . . . . .84725.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg) . . . 84825.5.24 LESENSE_STx_TCONFA - State transition configuration A (Async Reg) . . . . .84925.5.25 LESENSE_STx_TCONFB - State transition configuration B (Async Reg) . . . . .85125.5.26 LESENSE_BUFx_DATA - Scan results (Async Reg) . . . . . . . . . . . .85225.5.27 LESENSE_CHx_TIMING - Scan configuration (Async Reg) . . . . . . . . . . 85325.5.28 LESENSE_CHx_INTERACT - Scan configuration (Async Reg) . . . . . . . . . 85425.5.29 LESENSE_CHx_EVAL - Scan configuration (Async Reg) . . . . . . . . . . . 856

26. ACMP - Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . .85726.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .857

26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .857

26.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .85826.3.1 Warm-up Time . . . . . . . . . . . . . . . . . . . . . . . . . . 85826.3.2 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . 85926.3.3 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . .860


26.3.4 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 86026.3.5 Capacitive Sense Mode . . . . . . . . . . . . . . . . . . . . . . . 86126.3.6 Interrupts and PRS Output . . . . . . . . . . . . . . . . . . . . . . 86126.3.7 Output to GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . 861

26.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

26.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .86326.5.1 ACMPn_CTRL - Control Register . . . . . . . . . . . . . . . . . . .86326.5.2 ACMPn_INPUTSEL - Input Selection Register . . . . . . . . . . . . . . . 86526.5.3 ACMPn_STATUS - Status Register . . . . . . . . . . . . . . . . . . . 86726.5.4 ACMPn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . 86726.5.5 ACMPn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . .86826.5.6 ACMPn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . 86826.5.7 ACMPn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . 86926.5.8 ACMPn_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . .869

27. VCMP - Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . .87027.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .870

27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .870

27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .87127.3.1 Warm-Up Time . . . . . . . . . . . . . . . . . . . . . . . . . . 87127.3.2 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . 87227.3.3 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . .87327.3.4 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 87327.3.5 Interrupts and PRS Output . . . . . . . . . . . . . . . . . . . . . . 873

27.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

27.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .87527.5.1 VCMP_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . 87527.5.2 VCMP_INPUTSEL - Input Selection Register . . . . . . . . . . . . . . .87627.5.3 VCMP_STATUS - Status Register . . . . . . . . . . . . . . . . . . . 87727.5.4 VCMP_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .87727.5.5 VCMP_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . 87827.5.6 VCMP_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .87827.5.7 VCMP_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .879

28. ADC - Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . .88028.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .880

28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .881

28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .88228.3.1 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 88228.3.2 Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . 88328.3.3 Warm-Up Time . . . . . . . . . . . . . . . . . . . . . . . . . . 88428.3.4 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 88528.3.5 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . .88628.3.6 Programming of Bias Current . . . . . . . . . . . . . . . . . . . . .88628.3.7 ADC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 88628.3.8 Interrupts, PRS Output . . . . . . . . . . . . . . . . . . . . . . .890


28.3.9 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . .89028.3.10 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 891

28.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

28.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .89328.5.1 ADCn_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . 89328.5.2 ADCn_CMD - Command Register . . . . . . . . . . . . . . . . . . .89528.5.3 ADCn_STATUS - Status Register . . . . . . . . . . . . . . . . . . .89628.5.4 ADCn_SINGLECTRL - Single Sample Control Register . . . . . . . . . . . . 89828.5.5 ADCn_SCANCTRL - Scan Control Register . . . . . . . . . . . . . . . . 90228.5.6 ADCn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . 90528.5.7 ADCn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .90628.5.8 ADCn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .90728.5.9 ADCn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .90828.5.10 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) . . . . . 90828.5.11 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads) . . . . . . 90928.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register . . . . . . 90928.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register . . . . . . .91028.5.14 ADCn_CAL - Calibration Register . . . . . . . . . . . . . . . . . . . 91128.5.15 ADCn_BIASPROG - Bias Programming Register . . . . . . . . . . . . . . 912

29. DAC - Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . .91329.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913

29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913

29.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .91429.3.1 Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . 91429.3.2 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . .91529.3.3 Programming of Bias Current . . . . . . . . . . . . . . . . . . . . .91529.3.4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91629.3.5 Sine Generation Mode . . . . . . . . . . . . . . . . . . . . . . .91629.3.6 Interrupts and PRS Output . . . . . . . . . . . . . . . . . . . . . . 91729.3.7 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . .91729.3.8 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . .91729.3.9 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . .91729.3.10 Opamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917

29.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

29.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .91929.5.1 DACn_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . 91929.5.2 DACn_STATUS - Status Register . . . . . . . . . . . . . . . . . . .92129.5.3 DACn_CH0CTRL - Channel 0 Control Register . . . . . . . . . . . . . . . 92229.5.4 DACn_CH1CTRL - Channel 1 Control Register . . . . . . . . . . . . . . . 92429.5.5 DACn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . 92529.5.6 DACn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .92629.5.7 DACn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .92729.5.8 DACn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .92829.5.9 DACn_CH0DATA - Channel 0 Data Register . . . . . . . . . . . . . . .92829.5.10 DACn_CH1DATA - Channel 1 Data Register . . . . . . . . . . . . . . . 92929.5.11 DACn_COMBDATA - Combined Data Register . . . . . . . . . . . . . .929


29.5.12 DACn_CAL - Calibration Register . . . . . . . . . . . . . . . . . . . 93029.5.13 DACn_BIASPROG - Bias Programming Register . . . . . . . . . . . . . . 93129.5.14 DACn_OPACTRL - Operational Amplifier Control Register . . . . . . . . . .93229.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register . . . . . . . . . . 93329.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register . . . . . .93429.5.17 DACn_OPA1MUX - Operational Amplifier Mux Configuration Register . . . . . .93729.5.18 DACn_OPA2MUX - Operational Amplifier Mux Configuration Register . . . . . .940

30. OPAMP - Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . .94230.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .942

30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .942

30.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .94330.3.1 Opamp Configuration . . . . . . . . . . . . . . . . . . . . . . . . 94430.3.2 Opamp Modes . . . . . . . . . . . . . . . . . . . . . . . . . .94630.3.3 Opamp DAC Combination . . . . . . . . . . . . . . . . . . . . . .954


30.5 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

31. AES - Advanced Encryption Standard Accelerator . . . . . . . . . . . . . . . . 95531.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .955

31.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .955

31.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .95631.3.1 Encryption/Decryption. . . . . . . . . . . . . . . . . . . . . . . . 95631.3.2 Data and Key Access . . . . . . . . . . . . . . . . . . . . . . . . 95731.3.3 Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . .95831.3.4 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . .95831.3.5 Block Chaining Example . . . . . . . . . . . . . . . . . . . . . . . 959

31.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

31.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .96031.5.1 AES_CTRL - Control Register . . . . . . . . . . . . . . . . . . . .96031.5.2 AES_CMD - Command Register . . . . . . . . . . . . . . . . . . . . 96131.5.3 AES_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . 96131.5.4 AES_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . .96231.5.5 AES_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . 96231.5.6 AES_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . 96231.5.7 AES_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 96331.5.8 AES_DATA - DATA Register (Actionable Reads) . . . . . . . . . . . . . . 96331.5.9 AES_XORDATA - XORDATA Register (Actionable Reads) . . . . . . . . . . . 96431.5.10 AES_KEYLA - KEY Low Register (Actionable Reads) . . . . . . . . . . . . 96431.5.11 AES_KEYLB - KEY Low Register (Actionable Reads) . . . . . . . . . . . . 96531.5.12 AES_KEYLC - KEY Low Register (Actionable Reads) . . . . . . . . . . . . 96531.5.13 AES_KEYLD - KEY Low Register (Actionable Reads) . . . . . . . . . . . . 96631.5.14 AES_KEYHA - KEY High Register (Actionable Reads) . . . . . . . . . . . . 96631.5.15 AES_KEYHB - KEY High Register (Actionable Reads) . . . . . . . . . . . . 96731.5.16 AES_KEYHC - KEY High Register (Actionable Reads) . . . . . . . . . . . . 96731.5.17 AES_KEYHD - KEY High Register (Actionable Reads) . . . . . . . . . . . . 968


32. GPIO - General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . 96932.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .969

32.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .970

32.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .97132.3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . .97232.3.2 EM4 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . .97532.3.3 EM4 Retention . . . . . . . . . . . . . . . . . . . . . . . . . . 97532.3.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . .97632.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . .97732.3.6 Output to PRS . . . . . . . . . . . . . . . . . . . . . . . . . .97732.3.7 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 977

32.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978

32.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .97932.5.1 GPIO_Px_CTRL - Port Control Register . . . . . . . . . . . . . . . . .97932.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register . . . . . . . . . . . . . . 98032.5.3 GPIO_Px_MODEH - Port Pin Mode High Register . . . . . . . . . . . . . . 98232.5.4 GPIO_Px_DOUT - Port Data Out Register . . . . . . . . . . . . . . . .98332.5.5 GPIO_Px_DOUTSET - Port Data Out Set Register . . . . . . . . . . . . .98332.5.6 GPIO_Px_DOUTCLR - Port Data Out Clear Register . . . . . . . . . . . . . 98432.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register . . . . . . . . . . . .98432.5.8 GPIO_Px_DIN - Port Data In Register . . . . . . . . . . . . . . . . . . 98532.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register . . . . . . . . . . . . . 98532.5.10 GPIO_EXTIPSELL - External Interrupt Port Select Low Register . . . . . . . .98632.5.11 GPIO_EXTIPSELH - External Interrupt Port Select High Register . . . . . . . .98932.5.12 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register . . . . . . . . 99232.5.13 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register . . . . . . .99232.5.14 GPIO_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .99332.5.15 GPIO_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . 99332.5.16 GPIO_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . 99432.5.17 GPIO_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .99432.5.18 GPIO_ROUTE - I/O Routing Register . . . . . . . . . . . . . . . . .99532.5.19 GPIO_INSENSE - Input Sense Register . . . . . . . . . . . . . . . . . 99632.5.20 GPIO_LOCK - Configuration Lock Register . . . . . . . . . . . . . . .99732.5.21 GPIO_CTRL - GPIO Control Register . . . . . . . . . . . . . . . . .99732.5.22 GPIO_CMD - GPIO Command Register . . . . . . . . . . . . . . . . . 99832.5.23 GPIO_EM4WUEN - EM4 Wake-up Enable Register . . . . . . . . . . . . . 99832.5.24 GPIO_EM4WUPOL - EM4 Wake-up Polarity Register . . . . . . . . . . . . 99932.5.25 GPIO_EM4WUCAUSE - EM4 Wake-up Cause Register . . . . . . . . . . .1000

33. LCD - Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . .100133.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1001

33.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1001

33.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .100233.3.1 LCD Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . .100233.3.2 Multiplexing, Bias, and Wave Settings . . . . . . . . . . . . . . . . . .100333.3.3 Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . .1004


33.3.4 LCD Contrast . . . . . . . . . . . . . . . . . . . . . . . . . .102133.3.5 VLCD Selection . . . . . . . . . . . . . . . . . . . . . . . . . .102233.3.6 VBOOST Control . . . . . . . . . . . . . . . . . . . . . . . . .102333.3.7 Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .102333.3.8 Data Update . . . . . . . . . . . . . . . . . . . . . . . . . . .102433.3.9 Direct Segment Control (DSC) . . . . . . . . . . . . . . . . . . . . .102533.3.10 Frame Counter (FC) . . . . . . . . . . . . . . . . . . . . . . . .102633.3.11 LCD Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .102733.3.12 Blink, Blank, and Animation Features . . . . . . . . . . . . . . . . . .102733.3.13 LCD in Low Energy Modes . . . . . . . . . . . . . . . . . . . . .103033.3.14 Register Access . . . . . . . . . . . . . . . . . . . . . . . . .1030

33.4 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

33.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .103233.5.1 LCD_CTRL - Control Register (Async Reg) . . . . . . . . . . . . . . . .103233.5.2 LCD_DISPCTRL - Display Control Register . . . . . . . . . . . . . . . .103333.5.3 LCD_SEGEN - Segment Enable Register . . . . . . . . . . . . . . . .103533.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg) . . . . . . . .103633.5.5 LCD_STATUS - Status Register . . . . . . . . . . . . . . . . . . . .103833.5.6 LCD_AREGA - Animation Register A (Async Reg) . . . . . . . . . . . . . . 103833.5.7 LCD_AREGB - Animation Register B (Async Reg) . . . . . . . . . . . . . . 103933.5.8 LCD_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . .103933.5.9 LCD_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . .103933.5.10 LCD_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . 104033.5.11 LCD_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . .104033.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg) . . . . . . . . . .104133.5.13 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg) . . . . . . . . . .104133.5.14 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg) . . . . . . . . . .104233.5.15 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg) . . . . . . . . . .104233.5.16 LCD_SEGD0H - Segment Data High Register 0 (Async Reg) . . . . . . . . .104333.5.17 LCD_SEGD1H - Segment Data High Register 1 (Async Reg) . . . . . . . . .104333.5.18 LCD_SEGD2H - Segment Data High Register 2 (Async Reg) . . . . . . . . .104433.5.19 LCD_SEGD3H - Segment Data High Register 3 (Async Reg) . . . . . . . . .104433.5.20 LCD_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . . .104533.5.21 LCD_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . .104633.5.22 LCD_SEGD4H - Segment Data High Register 4 (Async Reg) . . . . . . . . .104733.5.23 LCD_SEGD5H - Segment Data High Register 5 (Async Reg) . . . . . . . . .104833.5.24 LCD_SEGD6H - Segment Data High Register 6 (Async Reg) . . . . . . . . .104833.5.25 LCD_SEGD7H - Segment Data High Register 7 (Async Reg) . . . . . . . . .104933.5.26 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) . . . . . . . . . .104933.5.27 LCD_SEGD5L - Segment Data Low Register 5 (Async Reg) . . . . . . . . . .105033.5.28 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg) . . . . . . . . . .105033.5.29 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg) . . . . . . . . . .1051

34. FPUEH - Floating Point Unit Exception Handler . . . . . . . . . . . . . . . . .105234.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .1052

34.2 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052



34.3.1 FPUEH_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . 105334.3.2 FPUEH_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .105434.3.3 FPUEH_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .105534.3.4 FPUEH_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .1056

35. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105735.1 Revision 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1057

35.2 Revision 1.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1057

35.3 Revision 0.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1057

35.4 Revision 0.51 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1058

35.5 Revision 0.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1058

36. Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1059


1. Energy Friendly Microcontrollers

1.1 Typical Applications

The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices aredeveloped to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. Thisunique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M4 processor helps designers getmore out of the available energy in a variety of applications.

Ultra low energy EFM32WG microcontrollers are perfect for:

Gas metering Energy metering Water metering Smart metering Alarm and security systems Health and fitness applications Industrial and home automation

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1.2 EFM32WG Development

Because EFM32WG use the Cortex-M4 CPU, embedded designers benefit from the largest development ecosystem in the industry, theARM ecosystem. The development suite spans the whole design process and includes powerful debug tools, and some of the worldstop brand compilers. Libraries with documentation and user examples shorten time from idea to market.

The range of EFM32WG devices ensure easy migration and feature upgrade possibilities.

EFM32WG Reference ManualEnergy Friendly Microcontrollers


2. About This Document

This document contains reference material for the EFM32WG series of microcontrollers. All modules and peripherals in the EFM32WGseries devices are described in general terms. Not all modules are present in all devices, and the feature set for each device mightvary. Such differences, including pinout, are covered in the device-specific datasheet.

2.1 Conventions

Register Names

Register names are given as a module name prefix followed by the short register name:

TIMERn_CTRL - Control Register

The "n" denotes the numeric instance for modules that might have more than one instance.

Some registers are grouped which leads to a group name following the module prefix:

GPIO_Px_DOUT - Port Data Out Register,

where x denotes the port instance (A,B,...).

Bit Fields

Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with (x:y), where x is the start bit andy is the end bit.

Address

The address for each register can be found by adding the base address of the module (found in the Memory Map), and the offset ad-dress for the register (found in module Register Map).

Access Type

The register access types used in the register descriptions are explained in the table below.

Table 2.1. Register Access Types

Access Type Description

R Read only. Writes are ignored.

RW Readable and writable.

RW1 Readable and writable. Only writes to 1 have effect.

RW1H Readable, writable and updated by hardware. Only writes to 1 have effect.

W1 Read value undefined. Only writes to 1 have effect.

W Write only. Read value undefined.

RWH Readable, writable and updated by hardware.

Number format

0x prefix is used for hexadecimal numbers.

0b prefix is used for binary numbers.

Numbers without prefix are in decimal representation.

EFM32WG Reference ManualAbout This Document


Reserved

Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in theRegister Description. Reserved bits might be read as 1 in future devices.

Reset Value

The reset value denotes the value after reset. Registers denoted with X have an unknown reset value and need to be initialized beforeuse. Note that, before these registers are initialized, read-modify-write operations might result in undefined register values.

Pin Connections

Pin connections are given as a module prefix followed by a short pin name:

USn_TX (USARTn TX pin)

The pin locations referenced in this document are given in the device-specific datasheet.

2.2 Related Documentation

Further documentation on the EFM32WG family and the ARM Cortex-M4 can be found at the Silicon Laboratories and ARM web pa-ges:

www.silabs.com

www.arm.com

EFM32WG Reference ManualAbout This Document


http://www.silabs.comhttp://www.arm.com

3. System Overview

3.1 Introduction

The EFM32 MCUs are the worlds most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-M4, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, theEFM32WG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance andlow-energy consumption. See Figure 3.1 Block Diagram of EFM32WG on page 30 for a block diagram of the EFM32WG device.

EFM32WG Reference ManualSystem Overview


3.2 Features

ARM Cortex-M4 CPU platform High Performance 32-bit processor @ up to 48 MHz DSP instruction support and floating-point unit Memory Protection Unit Wake-up Interrupt Controller

Flexible Energy Management System 20 nA @ 3 V Shutoff Mode 0.4 A @ 3 V Shutoff Mode with RTC 0.65 A @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention 0.95 A @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and

CPU retention 63 A/MHz @ 3 V Sleep Mode 225 A/MHz @ 3 V Run Mode, with code executed from flash

256/128/64 KB Flash 32 KB RAM Up to 93 General Purpose I/O pins

Configurable push-pull, open-drain, pull-up/down, input filter, drive strength Configurable peripheral I/O locations 16 asynchronous external interrupts Output state retention and wake-up from Shutoff Mode

12 Channel DMA Controller Alternate/primary descriptors with s

2 EFM32WG Reference Manual TM - Silicon Labs Reference Manual Energy Friendly Microcontrollers

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