1982 Index IEEE Transactions on Computers Vol. C-31 · 1982 Index IEEE Transactions on Computers...

1982 IndexIEEE Transactions on Computers

Vol. C-31

This index covers all items-papers, correspondence, reviews, etc.-thatappeared in this periodical during 1982, and items from prior years that werecommented upon or corrected in 1982. The index is divided into an AuthorIndex and a Subject Index, both arranged alphabetically.The Author Index contains the primary entry for each item; this entry is

listed under the name of the first author and includes coauthor names, title,location of the item, and notice of corrections and comments if any. Cross-references are given from each coauthor name to the name of thecorresponding first author. The location of the item is specified by thejournal name (abbreviated), year, month, and inclusive pages.

The Subject Index contains several entries for.each item, each consistingof a subject heading, modifying phrase(s), first author's name-followed by+ if the paper has coauthors-and enough information to locate the item.For coauthors, title, comments, and corrections if any, etc., it is necessary torefer to the primary entry in the Author Index. Subject cross-references areprovided as required by the subject matter. Also provided wheneverappropriate are listings under generic headings such as Bibliographies (forany paper with at least 50 references, as well as papers that are exclusivelybibliographies), Bookreviews, and Specialissues.

AUTHOR INDEX

A

Abramovici, Miron. A hierarchical, path-oriented approach to faultdiagnosis in modular combinational circuits (Corresp.); T-C Jul 82672-677

Abramovici, Miron, and Melvin A. Breuer. Fault diagnosis in synchronoussequential circuits based on an effect - cause analysis; T-C Dec 821165-1172

Adams, George B., III, and Howard Jay Siegel. On the number ofpermutations performable by the Augmented Data Manipulatornetwork; T-CApr 82 270-277

Adams, George B., III, and Howard Jay Siegel. The Extra Stage Cube: Afault-tolerant interconnection network for supersystems; T-C May 82443-454

Agrawal, Dharma P., see Bhuyan, Laxmi N., T-CApr 82 335-338Agrawal, Dharma P., and Ramesh Jain. A pipelined pseudoparallel system

architecture for real-time dynamic scene analysis; T-C Oct 82 952-962Alegre, Ignacio, see Lang, Tomas, T-CDec 82 1227-1234Aleliunas, Romas, and Arnold L. Rosenberg. On embedding rectangular

grids in square grids (Corresp.); T-CSep 82 907-913Amer, Paul D. A measurement center for the NBS local area computer

network; T-CAug 82 723-729Antonsson, Dan, Bjdrn Gudmundsson, Tomas Hedblom, Bjdrn Kruse, Arne

Linge, Peter Lord, and Tomas Ohlsson. PICAP-A system approachto image processing (Corresp.); T-COct 82 997-1000

Arden, Bruce W., and Hikyu Lee. A regular network for multicomputersystems; T-CJan 82 60-69

Arden, Bruce W., and Ran Ginosar. MP/C: A multiprocessor/computerarchitecture; T-CMay 82 455-473

Arnold, Robert G., Robert 0. Berg, and James W. Thomas. A modularapproach to real-time supersystems; T-CMay 82 385-398

Arun, K. S., see Kung, Sun-Yuan, T-CNov 82 1054-1066Avizienis, Algirdas, see Mangir, Tiilin Erdim, T-CJul 82 609-616Ayache, Jean-Michel, Jean-Pierre Courtiat, and Michel Diaz. REBUS, a

fault-tolerant distributed system for industrial real-time control; T-CJul 82 637-647

B

Baba, Takanobu, Ken Ishikawa, and Kenzo' Okuda. A two-levelmicroprogrammed multiprocessor computer with nonnumericfunctions; T-CDec 82 1142-1 156

Balbo, Gianfranco, see Marsan Ajmone, Marco, T-CDec 82 1179-1191Banerjee, Uptal, Shyh-Ching Chen, David J. Kuck, and Ross A. Towle.

Time and parallel processor bounds for Fortran-like loops; T-C Sep 79660-670.

Comments by Heuft, R. W., and Little, W. D., T-CJan 82 78-81Baron, Robert J.,see Riley, David D., T-CFeb 82 110-118Bartoldus, R. W., see Mikhail, W. F., T-CJun 82 560-564Batcher, Kenneth E. Bit-serial parallel processing systems; T-C May 82

377-384

Bellon, Catherine, and Gabri&le Saucier. Protection against external errorsin a dedicated system; T-CApr 82 311-317

Benz, Hans, see Buehrer, Richard E., T-CNov 82 1035-1044Berg, Robert O., see Arnold, Robert G., T-CMay 82 385-398Bhaskar Rao, D. V., see Kung, Sun-Yuan, T-CNov 82 1054-1066Bhuyan, Laxmi N., and Dharma P. Agrawal. On the generalized binary

system (Corresp.); T-CApr82 335-338Black, James P., see Taylor, David J., T-CJul 82 602-608Bochmann, Gregor V. Hardware specification with temporal logic: An

example; T-CMar 82 223-231Booth, Taylor L., Ed. Editor's notice; T-CJan 82 1Booth, Taylor L., Ed. Editor's notice; T-CApr 82 269Booth, Taylor L., Ed. Announcement; T-CJun 82 477Bose, Bella, and Thammavaram R. N. Rao. Theory of unidirectional error

correcting/detecting codes; T-CJun 82 521-530Bose, Bella, and D. K. Pradhan. Optimal unidirectional error

detecting/correcting codes (Corresp.); T-CJun 82 564-568Brent, Richard P., and H. T. Kung. A regular layout for parallel adders; T-C

Mar82 260-264Breuer, Melvin A., see Abramovici, Miron, T-CDec 82 1165-1172Briggs, Fay6 A., King-Sun Fu, Kai Hwang, and Benjamin W. Wah. PUMPS

architecture for pattern analysis and image database management; T-COct 82 969-983

Briggs,'Faye A., see Dubois, Michel, T-CNov 82 1083-1099Bron, Bernard, see Buehrer, Richard E., T-CNov 82 1035-1044Brundiers, Hans-Joerg, see Buehrer, Richard E., T-CNov 82 1035-1044Buehrer, Richard E., Hans-Joerg Brundiers, Hans Benz, Bernard Bron,

Hansmartin Friess, Walter Haelg, Hans Juergen Halin, AndersIsacson, and Milan Tadian. The ETH-multiprocessor EMPRESS: Adynamically configurable MIMD system; T-CNov 82 1035-1044

Burkowski, Forbes J. A hardware hashing scheme in the design of amultiterm string comparator; T-CSep 82 825-834

Butner, Steven E., see Iyer, Ravishankar K., T-CJul 82 697-706

C

Canto, M. A., see Dormido, S., T-CAug 82 802-805Castillo, Xavier, Stephen R. McConnel, and Daniel P. Siewiorek. Derivation

and calibration of a transient error reliability model; T-C Jul 82658-67 1

Ceri, Stefano, and Giuseppe Pelagatti. Allocation of operations indistributed database access; T-CFeb 82 119-129

Chen, C. C. A distributed algorithm for shortest paths (Corresp.); T-C Sep82 898-899

Chen, Chung Ho. An algebraic model of arithmetic codes (Corresp.); T-CApr82 318-321

Chen, I. N., and R. Willoner. An 0(n) parallel multiplier with bit-sequentialinput and output; T-COct 79 721-727.

Comments by Sips, H. J., T-CApr 82 325-327Chen, Kuo-Wei, see Irani, Keki B., T-CNov 82 1067-1075Chen, Shyh-Ching, see Banerjee, Uptal, T-CSep 79 660-670.Chen, X., and S. L. Hurst. A comparison of universal-logic-module

realizations and their application in the synthesis of combinatorial andsequential logic networks; T-CFeb 82 140-147

Cheng, Yeng-Cheng, see Hwang, Kai, T-CDec 82 1215-1224Cheung, To-Yat. A method for equijoin queries in distributed relational

databases; T-CAug 82 746-751Chien, Y. T., Guest ed., and Edward A. Parrish, Jr., Guest ed. Special issue

on computer architecture for pattern analysis and image databasemanagement; T-COct 82921-922

Chu, Wesley W., and Paul Hurley. Optimal query processing for distributeddatabase systems; T-CSep 82 835-850

Clarke, Edmund M., and Christos N. Nikolaou. Distributed reconfigurationstrategies for fault-tolerant multiprocessor systems; T-C Aug 82771-784

Conte, Gianni, see Marsan Ajmone, Marco, T-CDec 82 1179-1191Courtiat, Jean-Pierre, see Ayache, Jean-Michel, T-CJul 82 637-647Cristian, Flaviu. Exception handling and software fault tolerance; T-C Jun

82 531-540

D

Davidson, Edward S., see Yen, David W. L., T-CNov 82 1116-1121de Faria, Jamie M., Jr., see Varshney, Pramod K., T-CFeb 82 164-170De Prycker, Martin. A performance analysis of the implementation of

addressing methods in block-structured languages; T-CFeb 82 155-163

IEEE T-C 1982 INDEX - 2

De Prycker, Martin. On the development of a measurement system for highlevel language program statistics; T-CSep 82 883-891

Deminet, Jarek. Experience with multiprocessor algorithms; T-C Apr 82278-288

Dias, Daniel M., and Manoj Kumar. Comment on 'Interference analysis ofshuffle/exchange networks' by Thanawastien, S., and Nelson, V. P.; T-CJun 82 546-547

Diaz, Michel, see Ayache, Jean-Michel, T-CJul82 637-647Dormido, S., and' M. A. Canto. An upper bound for the synthesis of

generalized parallel counters (Corresp.); T-CAug 82 802-805Dortok, O.,see Fleischhammer, W., T-CMar 79 273-276.Doty, K. L., J. D. Greenblatt, and S. Y. W. Su. Magnetic bubble memory

architectures for supporting associative searching of relationaldatabases; T-CNov 80 957-970.

Comments byStrader, N. R., II, T-CMar 82 265-266Dubois, Michel, and Faye A. Briggs. Effects of cache coherency in

multiprocessors; T-CNov82 1083-1099

E

El-Ziq, Yacoub M., and Stephen Y. H. Su. Fault diagnosis of MOScombinational networks; T-CFeb 82 129-139

Ercegovac, Milos D.,see Oklobdzija, Vojin G., T-CJan 82 70-75

F

Farley, J.,see Herron, J. M., T-CAug 82 795-800Feather, Arthur E.,see Siegel, Leah J., T-CMar 82 208-218Feldstein, Alan, and Richard Goodman. Loss of significance in floating

point subtraction and addition (Corresp.); T-CApr82 328-335Feng, Tse-yun, see Wu, Chuan-lin, T-COct 82923-933Feng, Tse-yun, Ed. Editor's notice; T-CJul82 573-574Feuer, Michael. Connectivity of random logic; T-CJan 82 29-33Finkel, Raphael A., see Fishburn, John P., T-CApr 82 288-295Fishburn, John P., and Raphael A. Finkel. Quotient networks; T-CApr 82

288-295Flanders, Peter M. A unified approach to a class of data movements on an

array processor; T-CSep 82 809-819Fleischhammer, W., and 0. Dortok. The anomalous behavior of flip-flops in

synchronizer circuits; T-CMar 79 273-276.Comments by Lacroix, G., et al., T-CJan 82 77-78

Franklin, Mark A., Donald F. Wann, and William J. Thomas. Pinlimitations and partitioning of VLSI interconnection networks(Corresp.); T-CNov 82 1109-1116

Friess, Hansmartin, see Buehrer, Richard E., T-CNov 82 1035-1044Fu, King-Sun, see Tanaka, Eiichi, T-C Jul 78 605-612. Correction, Apr 82

327-328Fu, King-Sun, see Briggs, Fay6 A., T-C Oct 82 969-983Fujiwara, Eiji, see Kaneda, Shigeo, T-CJul 82 596-602Fujiwara, Hideo, and Shunichi Toida. The complexity of fault detection

problems for combinational logic circuits (Corresp.); T-C Jun 82555-560

Fung, Leona Y., see Patel, Janak H., T-CJul 82 589-595

G

Gal-Ezer, Ron J., see Kung, Sun-Yuan, T-CNov 82 1054-1066Garcia-Molina, Hector. Elections in a distributed computing system; T-C

Jan 82 48-59Geist, Robert M., and Kishor S. Trivedi. Optimal design of multilevel

storage hierarchies; T-CMar 82 249-260Gelenbe, Erol, Alain Lichnewsky, and Andreas Staphylopatis. Experience

with the parallel solution of partial differential equations on adistributed computing system; T-CDec 82 1157-1164

Gerla, Mario, see Marsan, Marco Ajmone, T-CMar 82 239-248Gerrity, George W. Computer representation of real numbers; T-CAug 82

709-714Gilbert, Barry K., see Swartzlander, Earl E., Jr., T-CMay 82 399-409Ginosar, Ran, see Arden, Bruce W., T-CMay 82 455-473Glaser, Robert E., and Gerald M. Masson. The containment set approach to

upsets in digital systems (Corresp.); T-CJul 82 689-692Goodman, Richard, see Feldstein, Alan, T-CApr82 328-335Greenblatt, J. D., see Doty, K. L., T-CNov 80 957-970.Gudmundsson, Bjorn, see Antonsson, Dan, T-COct 82 997-1000

H

Haelg, Walter, see Buehrer, Richard E., T-CNov 82 1035-1044Hafer, Louis J., and Alice C. Parker. Automated synthesis of digital

hardware; T-CFeb 82 93-109Halin, Hans Juergen, see Buehrer, Richard E., T-CNov 82 1035-1044Haralick, Robert M., see Vaidya, Prashant D., T-COct 82 1025-1031

Hartmann, Carlos R. P.,see Varshney, Pramod K., T-CFeb 82 164-170Hedblom, Tomas, see Antonsson, Dan, T-C Oct 82 997-1000Heidelberger, Philip, and Kishor S. Trivedi. Queueing network models for

parallel processing with asynchronous tasks; T-CNov 82 1099-1109Herron, J. M., J. Farley, K. Preston, Jr., and H. Sellner. A general-purpose

high-speed logical transform image processor (Corresp.); T-C Aug 82795-800

Heuft, Richard W., and Warren D. Little. Improved time and parallelprocessor bounds for Fortran-like loops; T-CJan 82 78-81

Hollaar, Lee A. Direct implementation of asynchronous control units; T-CDec 82 1133-1141

Holzmann, Gerard J. A theory for protocol validation; T-CAug 82 730-738Hong, Se June, Guest ed. Preface: Reliable and fault-tolerant computing; T-

CJuJ2 575-577Huang, Chao H., see Taylor, Fred J., T-CApr 82 321-325Hurley, Paul, see Chu, Wesley W., T-CSep 82 835-850Hurst, S. L.,see Chen, X., T-CFeb 82 140-147Hwang, Kai, see Briggs, Fay6 A., T-C Oct 82 969-983Hwang, Kai, and Yeng-Cheng Cheng. Partitioned matrix algorithms for

VLSI arithmetic systems; T-CDec 82 1215-1224

I

Ibaraki, Toshihide, and Tsunehiko Kameda. Deadlock-free systems for abounded number of processes; T-CMar82 188-193

Ignizio, James P., David F. Palmer, and Catherine M. Murphy. Amulticriteria approach to supersystem architecture definition; T-CMay82410-418

Irani, Keki B., and Nicholas G. Khabbaz. A methodology for the design ofcommunication networks and the distribution of data in distributedsupercomputer systems; T-CMay 82419-434

Irani, Keki B., and Kuo-Wei Chen. Minimization of interprocessorcommunication for parallel computation; T-CNov 82 1067-1075

Isacson, Anders, see Buehrer, Richard E., T-CNov 82 1035-1044Ishikawa, Ken, see Baba, Takanobu, T-CDec 82 1142-1156Iyer, Ravishankar K., Steven E. Butner, and Edward J. McCluskey. A

statistical failure/load relationship: Results of a multicomputer study(Corresp.); T-CJul 82 697-706

J

Jain, Ramesh, see Agrawal, Dharma P., T-C Oct 82 952-962Jernigan, M. E., see Roeser, Peter R., T-CFeb 82 175-177Jess, Jochen A. G., and H. G. M. Kees. A data structure for parallel L/U

decomposition; T-CMar 82 231-239

K

Kamangar, F. A., and K. R. Rao. Fast algorithms for the 2-D discrete cosinetransform (Corresp.); T-CSep 82 899-906

Kameda, Tsunehiko, see Ibaraki, Toshihide, T-CMar 82 188-193Kaneda, Shigeo, and Eiji Fujiwara. Single byte error correcting - double byte

error detecting codes for memory systems; T-CJul82 596-602Kartashev, Steven I., see Kartashev, Svetlana P., T-CJun 82 488-514Kartashev, Svetlana P., and Steven I. Kartashev. Distribution of programs

for a system with dynamic architecture; T-CJun 82 488-514Kartashev, Svetlana P., Guest ed. Supersystems: Current state-of-the-art-

Guest Editor's introduction; T-CMay 82 345-348Kees, H. G. M., see Jess, Jochen A. G., T-CMar 82 231-239Khabbaz, Nicholas G., see Irani, Keki B., T-CMay 82 419-434Khakbaz, Javad. Totaly self-checking checker for 1-out-of-n code using two-

rail codes (Corresp.); T-CJul 82 677-681Kini, Vittal, and Daniel P. Siewiorek. Automatic generation of symbolic

reliability functions for processor - memory - switch structures; T-CAug 82 752-771

Kluge, Werner E., and Kurt Lautenbach. The orderly resolution of memoryaccess conflicts among competing channel processes; T-C Mar 82194-207

Kruse, Bjorn, see Antonsson, Dan, T-C Oct 82 997-1000Kubale, Marek. Comment on 'Decomposition of permutation networks' by

Ramanujam, H. R.; T-CMar 82 265Kuck, David J., see Banerjee, Uptal, T-CSep 79 660-670.Kuck, David J., and Richard A. Stokes. The Burroughs Scientific Processor

(BSP); T-CMay 82 363-376Kulkarni, Ashok V., and David W. L. Yen. Systolic processing and an

implementation for signal and image processing (Corresp.); T-C Oct 821000-1009

Kumar, Manoj, see Dias, Daniel M., T-CJun 82 546-547Kung, H. T., see Brent, Richard P., T-CMar 82 260-264Kung, Sun-Yuan, K. S. Arun, Ron J. Gal-Ezer, and D. V. Bhaskar Rao.

Wavefront array processor: Language, architecture, and applications;T-CNov82 1054-1066

IEEE T-C 1982 INDEX -3

Kunii, Tosiyasu L., see Yamaguchi, Kazunori, T-COct 82 983-996Kushner, Todd, Angela Y. Wu, and Azriel Rosenfeld. Image processing on

ZMOB; T-COct 82 943-951

L

Lacroix, G., P. Marchegay, and G. Piel. Comment on 'The anomalousbehavior of flip-flops in synchronizer circuits' by Fleischhammer, W.,and Dortok, O.; T-CJan 82 77-78

Lai, Hung Chi, and Saburo Muroga. Logic networks of carry - save adders;T-CSep 82 870-882

Lang, Tomis, Mateo Valero, and Ignacio Alegre. Bandwidth of crossbar andmultiple-bus connections for multiprocessors (Corresp.); T-C Dec 821227-1234

Lautenbach, Kurt, see Kluge, Werner E., T-CMar 82 194-207Lawrie, Duncan H., and Chandra R. Vora. The prime memory system for

array access; T-CMay 82 435-442Lawrie, Duncan H., see Montoye, Robert K., T-CNov 82 1076-1082Lee, Daniel T.,see Ni, Lionel M., T-COct 82 1017-1022Lee, Der-Tsai. On k-nearest neighbor Voronoi diagrams in the plane; T-C

Jun 82 478-487Lee, Der-Tsai, and Charles B. Silio, Jr. An optimal illumination region

algorithm for convex polygons (Corresp.); T-CDec 82 1225-1227Lee, Edward Y. S., see Ma, Perng-Yi Richard, T-CJan 82 41-47Lee, Hikyu, see Arden, Bruce W., T-CJan 82 60-69.Lee, Yann-Hang, see Shin, Kang S., T-CNov 82 1045-1053Leland, Will E., and Marvin H. Solomon. Dense trivalent graphs for

processor interconnection; T-CMar 82 219-222Levendel, Ytzhak H., and Premachandran R. Menon. Test generation

algorithms for computer hardware description languages; T-C Jul 82577-588

Lichnewsky, Alain, see Gelenbe, Erol, T-CDec 82 1157-1164Lin, Min-chang, see Wu, Chuan-lin, T-COct 82 923-933Lincoln, Neil R. Technology and design tradeoffs in the creation of a

modern supercomputer; T-CMay 82 349-362Linge, Arne, see Antonsson, Dan, T-COct 82 997-1000Little, Warren D., see Heuft, Richard W., T-CJan 82 78-81Liu, Kuang Y. Architecture for VLSI design of Reed - Solomon encoders

(Corresp.); T-CFeb 82 170-175Liu, Ming T., Guest ed., and Jerome Rothstein, Guest ed. Introduction:

Parallel and distributed processing; T-CNov 82 1033-1035Lord, Peter, see Antonsson, Dan, T-C Oct 82 997-1000Lu, David Jun. Watchdog processors and structural integrity checking

(Corresp.); T-CJul 82 681-685

M

Ma, Perng-Yi Richard, Edward Y. S. Lee, and Masahiro Tsuchiya. A taskallocation model for distributed computing systems; T-CJan 82 41-47

Mangir, Tulin Erdim, and Algirdas Avizienis. Fault-tolerant design forVLSI: Effect of interconnect requirements on yield improvement ofVLSI designs; T-CJul 82 609-616

Marchegay, P., see Lacroix, G., T-CJan 82 77-78Marsan Ajmone, Marco, Gianfranco Balbo, and Gianni Conte.

Comparative performance analysis of single bus multiprocessorarchitectures; T-CDec 82 1179-1191

Marsan, Marco Ajmone, and Mario Gerla. Markov models for multiple busmultiprocessor systems; T-CMar 82 239-248

Masson, Gerald M., see Glaser, Robert E., T-CJul 82 689-692Masson, Gerald M., see Nakamura, Shinji, T-CDec 82 1173-1179McCluskey, Edward J., see Iyer, Ravishankar K., T-CJul 82 697-706McConnel, Stephen R., see Castillo, Xavier, T-CJul 82 658-671McMillen, Robert J., and Howard Jay Siegel. Routing schemes for the

augmented data manipulator network in an MIMD system; T-CDee 821202-1214

Melliar-Smith, P. Michael, and Richard L. Schwartz. Formal specificationand mechanical verification of SIFT: A fault-tolerant flight controlsystem; T-CJul 82 616-630

Memmi, Gerard, and Yves Raillard. Some new results about the (d,k) graphproblem; T-CAug 82784-791

Menon, Premachandran R., see Levendel, Ytzhak H., T-CJul 82 577-588Metzner, John J. Convolutionally encoded memory protection (Corresp.);

T-CJun 82 547-551Meyer, John F. Closed-form solutions of performability; T-CJul 82 648-657Mikhail, W. F., R. W. Bartoldus, and R. A. Rutledge. The reliability of

memory with single-error correction (Corresp.); T-CJun 82 560-564Mili, Ali. Self-stabilizing programs: The fault-tolerant capability of self-

checking programs (Corresp.); T-CJuJ82 685-689Minden, Gary J., see Vaidya, Prashant D., T-COct 82 1025-1031Moldovan, Dan I. On the analysis and synthesis of VLSI algorithms

(Corresp.); T-CNov82 1121-1126Moiloy, Michael K. Performance analysis using stochastic Petri nets

(Corresp.); T-CSep 82 913-917Montoye, Robert K., and Duncan H. Lawrie. A practical algorithm for the

solution of triangular systems on a parallel processing system; T-CNov82 1076-1082

Morris, Kevin, see Sholl, Howard A., T-COct 82 1009-1017Murata, Tadao, see Sowa, Masahiro, T-CSep 82 820-824Muroga, Saburo, see Lai, Hung Chi, T-CSep 82 870-882Murphy, Catherine M., see Ignizio, James P., T-CMay 82 41-418

N

Nakamura, Shinji, and Gerald M. Masson. Lower bounds on crosspoints inconcentrators; T-CDec 82 1173-1179

Nassimi, David, and Sartaj Sahni. Parallel algorithms to set up the Benespermutation network; T-CFeb 82 148-154

Nassimi, David, and Sartaj Sahni. Optimal BPC permutations on a cubeconnected SIMD computer (Corresp.); T-CApr 82 338-341

Nelson, V. P., see Thanawastien, S., T-CAug81 545-556.Ni, Lionel M., Kwan Y. Wong, Daniel T. Lee, and Ronnie K. Poon. A

microprocessor-based office image processing system (Corresp.); T-COct 82 1017-1022

Nikolaou, Christos N., see Clarke, Edmund M., T-CAug 82 771-784Norris, James, see Sholl, Howard A., T-COct 82 1009-1017

0

O'Donnell, Michael J., and Carl H. Smith. A combinatorial problemconcerning processor interconnection networks (Corresp.); T-CFeb 82163-164

Ohlsson, Tomas, see Antonsson, Dan, T-COct 82 997-1000Oklobdzija, Vojin G., and Milos D. Ercegovac. An on-line square root

algorithm (Corresp.); T-CJan 82 70-75Okuda, Kenzo, see Baba, Takanobu, T-CDec 82 1142-1156Ottmann, Thomas A., Arnold L. Rosenberg, and Larry J. Stockmeyer. A

dictionary machine (for VLSI); T-CSep 82 892-897

P

Palmer, David F., see Ignizio, James P., T-CMay 82 410-418Panzieri, F., see Shrivastava, S. K., T-CJul82 692-697Parker, Alice C., see Hafer, Louis J., T-CFeb 82 93-109Parker, Kenneth P., see Williams, Thomas W., T-CJan 82 2-15Parrish, Edward A., Jr., Guest ed., see Chien, Y. T., Guest ed., T-C Oct 82

921-922Patel, Janak H. Analysis of multiprocessors with private cache memories;

T-CApr 82 296-304Patel, Janak H., and Leona Y. Fung. Concurrent error detection in ALU's

by recomputing with shifted operands; T-CJul 82 589-595Patel, Janak H.,see Yen, David W. L., T-CNov82 1116-1121Pelagatti, Giuseppe, see Ceri, Stefano, T-CFeb 82 119-129Piel, G., see Lacroix, G., T-CJan 82 77-78Poon, Ronnie K.,see Ni, Lionel M., T-COct82 1017-1022Porter, W. A. Error tolerant design of multivalued logic functions

(Corresp.); T-CJun 82 551-554Pradhan, D. K., see Bose, Bella, T-CJun 82 564-568Pradhan, Dhiraj K., and Sudhakar M. Reddy. A fault-tolerant

communication architecture for distributed systems; T-C Sep 82863-870

Preston, K., Jr., see Herron, J. M., T-CAug 82 795-800

R

Raillard, Yves, see Memmi, Gerard, T-CAug 82 784-791Ramanujam, H. R. Decomposition of permutation networks; T-C Jul 73

639-643.Comments by Kubale, M., T-CMar82 265

Rao, K. R., see Kamangar, F. A., T-CSep 82 899-906Rao, Thammavaram R. N., see Bose, Bella, T-CJun 82 521-530Reddy, Sudhakar M., see Pradhan, Dhiraj K., T-CSep 82 863-870Rhyne, V. Thomas, see Strader, Noel R., II, T-CAug 82 791-795Riley, David D., and Robert J. Baron. Design and evaluation of a

synchronous triangular interconnection scheme for interprocessorcommunications; T-CFeb 82 110-118

Robinson,. John P., and Chia-Lung Yeh. A method for modulo-2minimization (Corresp.); T-CAug82 800-801

Roeser, Peter R., and M. E. Jernigan. Fast Haar transform algorithms(Corresp.); T-CFeb 82 175-177

Rosenberg, Arnold L., see Ottmann, Thomas A., T-CSep 82 892-897Rosenberg, Arnold L., see Aleliunas, Romas, T-CSep 82 907-913Rosenfeld, Azriel, see Kushner, Todd, T-COct 82 943-951Rothstein, Jerome, Guest ed., see Liu, Ming T., Guest ed., T-C Nov 82

1033-1035Rudin, Harry, and Colin H. West. A validation technique for tightly coupled

protocols; T-CJul 82 630-636Rutledge, R. A., see Mikhail, W. F., T-CJun 82 560-564


s

Sahni, Sartaj, see Nassimi, David, T-CFeb 82 148-154Sahni, Sartaj, see Nassimi, David, T-CApr 82 338-341Sasidhar, J., see Shin, Kang S., T-CNov 82 1045-1053Saucier, Gabriele, see Bellon, Catherine, T-CApr 82 311-317Savage, Carla D., see Snyder, Wesley E., T-C Oct 82 963-968Scholl, Howard A., see Wei, Martin C., T-CSep 82 851-863Schwartz, Richard L., see Melliar-Smith, P. Michael, T-CJul 82 616-630Sellner, H., see Herron, J. M., T-CAug 82 795-800Shapiro, Linda G., see Vaidya, Prashant D., T-COct 82 1025-1031Shin, Kang S., Yann-Hang Lee, and J. Sasidhar. Design of HM2p-A

hierarchical multimicroprocessor for general-purpose applications; T-CNov82 1045-1053

Shiozaki, Akira. Single asymmetric error-correcting cyclic AN codes(Corresp.); T-CJun 82 554-555

Shively, Richard R. Architecture of a programmable digital signalprocessor; T-CJan 82 16-22

Sholl, Howard A., Kevin Morris, and James Norris. A multimicroprocessorsystem for real-time classification of railroad track flaws (Corresp.); T-COct 82 1009-1017

Shrivastava, S. K., and F. Panzieri. The design of a reliable remoteprocedure call mechanism (Corresp.); T-CJul 82 692-697

Siegel, Howard Jay, see Siegel, Leah J., T-CMar 82 208-218Siegel, Howard Jay, see Adams, George B., III, T-CApr 82 270-277Siegel, Howard Jay, see Adams, George B., III, T-CMay 82 443-454Siegel, Howard Jay, see McMillen, Robert J., T-CDec 82 1202-1214Siegel, Leah J., Howard Jay Siegel, and Arthur E. Feather. Parallel

processing approaches to image correlation; T-CMar 82 208-218Siegel, Leah J., see Warpenburg, Michael R., T-C Oct 82 934-942Siewiorek, Daniel P., see Castillo, Xavier, T-CJul 82 658-671Siewiorek, Daniel P., see Kini, Vittal, T-CAug 82 752-771Signaevskii, V. A. Comment on 'Multiprocessor scheduling with memory

allocation; deterministic approach' by Weglarz, J.; T-CSep 82 898Silberman, Gabriel M. Determining fault ratios in multilevel delayed-

staging storage hierarchies; T-CApr 82 305-3 10Silio, Charles B., Jr., see Lee, Der-Tsai, T-CDec 82 1225-1227Sips, H. J. Comment on 'An 0(n) parallel multiplier with bit-sequential

input and output' by Chen, I. N., and Willomer, R.; T-C Apr 82325-327

Six, Hans W., and Derick Wood. Counting and reporting intersections of d-ranges; T-CMar 82 181-187

Smith, Carl H., see O'Donnell, Michael J., T-CFeb 82 163-164Snyder, Wesley E., and Carla D. Savage. Content-addressable read/write

memories for image analysis; T-C Oct 82 963-968Solomon, Marvin H., see Leland, Will E., T-CMar 82 219-222Sowa, Masahiro, and Tadao Murata. A data flow computer architecture

with program and token memories; T-CSep 82 820-824Staphylopatis, Andreas, see Gelenbe, Erol, T-CDec 82 1157-1164Stockmeyer, Larry J., see Ottmann, Thomas A., T-CSep 82 892-897Stokes, Richard A., see Kuck, David J., T-CMay 82 363-376Strader, Noel R., II. Comment on 'Magnetic bubble memory architectures

for supporting associative searching of relational databases' by Doty, K.L., et al.; T-CMar 82 265-266

Strader, Noel R., II, and V. Thomas Rhyne. A canonical bit-sequentialmultiplier (Corresp.); T-CAug 82791-795

Su, S. Y. W.,see Doty, K. L., T-CNov 80 957-970.Su, Stephen Y. H.,see El-Ziq, Yacoub M., T-CFeb82 129-139Swartzlander, Earl E., Jr., and Barry K. Gilbert. Supersystems: Technology

and architecture; T-CMay 82 399-409

T

Tadian, Milan, see Buehrer, Richard E., T-CNov 82 1035-1044Takagi, Naofumi, see Yasuura, Hiroto, T-CDec 82 1192-1201Tanaka, Eiichi, and King-Sun Fu. Error-correcting parsers for formal

languages; T-CJul 78605-612. Correction, Apr 82327-328Taylor, David J., and James P. Black. Principles of data structure error

correction; T-CJul 82602-608Taylor, Fred J., and Chao H. Huang. An autoscale residue multiplier

(Corresp.); T-CApr82 321-325Taylor, Fred J. A VLSI residue arithmetic multiplier; T-C Jun 82 540-546Thanawastien, S., and V. P. Nelson. Interference analysis of

shuffle/exchange networks; T-CAug 81 545-556.Comments byDias, D. M., and Kumar, M., T-CJun 82546-547

Thayse, Andre. Synthesis and optimization of programs by means of P-functions; T-CJan 8234-40

Thomas, James W., see Arnold, Robert G., T-CMay 82385-398Thomas, William J., see Franklin, Mark A., T-CNov 82 1109-1116Toida, Shunichi, see Fujiwara, Hideo, T-CJun 82555-560Towle, Ross A. see Banerjee, Uptal, T-CSep 79660-670.Towsley, Don, and G. Venkatesh. Window random access protocols for

local computer networks; T-CAug 82715-722Trickey, Howard W. Good layouts for pattern recognizers; T-C Jun 82

514-520

+ Check author entry for coauthors

Trivedi, Kishor S., see Geist, Robert M., T-CMar 82 249-260Trivedi, Kishor S., see Heidelberger, Philip, T-CNov 82 1099-1109Tsuchiya, Masahiro, see Ma, Perng-Yi Richard, T-CJan 82 41-47

U

Uhr, Leonard. Comparing serial computers, arrays, and networks usingmeasures of 'active resources' (Corresp.); T-C Oct82 1022-1025

V

Vaidya, Prashant D., Linda G. Shapiro, Robert M. Haralick, and Gary J.Minden. Design and architectural implications of a spatial informationsystem (Corresp.); T-C Oct 82 1025-1031

Vaishnavi, Vijay K. Computing point enclosures; T-CJan 82 22-29Valero, Mateo, see Lang, Tomas, T-CDec 82 1227-1234Varshney, Pramod K., Carlos R. P. Hartmann, and Jamie M. de Faria, Jr.

Application of information theory to sequential fault diagnosis(Corresp.); T-CFeb 82 164-170

Venkatesh, G., see Towsley, Don, T-CAug 82 715-722Vora, Chandra R., see Lawrie, Duncan H., T-CMay 82 435-442

w

Wah, Benjamin W., see Briggs, Faye A., T-COct 82 969-983Wang, Jinpo. Delay and throughput analysis for computer communications

with balanced HDLC procedures; T-CAug 82 739-746Wann, Donald F., see Franklin, Mark A., T-CNov 82 1109-1116Warpenburg, Michael R., and Leah J. Siegel. SIMD image resampling; T-C

Oct 82 934-942Weglarz, J. Multiprocessor scheduling with memory allocation-A

deterministic approach; T-CAug 80 703-709.Comments by Signaevskii, V. A., T-CSep 82 898

Wei, Martin C., and Howard A. Scholl. An expression model for extractionand evaluation of parallelism in control structures; T-CSep 82 851-863

Weide, Bruce W. Modeling unusual behavior of parallel algorithms(Corresp.); T-CNov82 1126-1130

West, Colin H., see Rudin, Harry, T-CJul 82 630-636Williams, Thomas W., and Kenneth P. Parker. Design for testability-A

survey; T-CJan 82 2-15Willoner, R., see Chen, I. N., T-C Oct 79 721-727.Wong, Kwan Y., see Ni, Lionel M., T-COct 82 1017-1022Wood, Derick, see Six, Hans W., T-CMar 82 181-187Wu, Angela Y., see Kushner, Todd, T-COct 82 943-951Wu, Chuan-lin, Tse-yun Feng, and Min-chang Lin. Star: A local network

system for real-time management of imagery data; T-C Oct 82 923-933Wustmann, Gerhard. Autocorrelation function of filtered p-level maximal-

length sequences (Corresp.); T-CJan 82 75-77

y

Yajima, Shuzo, see Yasuura, Hiroto, T-CDec 82 1192-1201Yamaguchi, Kazunori, and Tosiyasu L. Kunii. PICCOLO logic for a picture

database computer and its implementation; T-C Oct 82 983-996Yasuura, Hiroto, Naofumi Takagi, and Shuzo Yajima. The parallel

enumeration sorting scheme for VLSI; T-CDec 82 1192-1201Yeh, Chia-Lung, see Robinson, John P., T-CAug 82 800-801Yen, David W. L., see Kulkarni, Ashok V., T-COct 82 1000-1009Yen, David W. L., Janak H. Patel, and Edward S. Davidson. Memory

interference in synchronous multiprocessor systems (Corresp.); T-CNov82 1116-1 121

SUBJECT INDEX

A

Access control; cf. Computer securityAdaptive systems

multicomputer system with dynamic architecture; software techniques fordistributing hardware resources among user programs. Kartashev,Svetlana P., + , T-CJun82488-514

Additionlogic networks of carry - save adders based on parallel adders withminimum number of NOR gates. Lai, Hung Chi, + , T-C Sep 8287-Q882

loss of significance in floating point addition or subtraction. Feldstein,Alan, + , T-CApr 82 328-335

multioperand addition of Koren's generalized number system. Bhuyan,LaxmiN., + , T-CApr82 335-338

t Check author entry for subsequent comments


regular layout for parallel adders; application to VLSI technology. Brent,RichardP., + , T-CMar 82 260-264

Aircraft computersbit-serial parallel processing systems; airborne associative processor and

ground-based massively parallel processor. Batcher, Kenneth E., T-CMay 82 377-384

Aircraft computers; cf. Aircraft controlAircraft controlSIFT fault-tolerant flight control -system; formal specification and

mechanical verification. Melliar-Smith, P. Michael, + , T-C Jul 82616-630

Algebraalgebra for validation of communication protocols in message passing

systems. Holzmann, GerardJ., T-CAug 82 73073 8Arithmetic

concurrent error detection in arithmetic and logic units by recomputingwith shifted operands. Patel, JanakH., + , T-CJul 82 589-595

Arithmetic; cf. Addition; Floating-point arithmetic; Logarithmic arithmetic;Matrices; Multiplication; Residue arithmetic; Square rooting

Arithmetic codingalgebraic model of arithmetic codes. Chen, Chung Ho, T-C Apr 82

318-321Arrays; cf. Logic arrays; Parallel processingAssociative memories

associative searching of relational databases supported by magneticbubble memories. Strader, NoelR., II, T-CMar 82 265-266

image region-labeling and clustering problems; parallel solution usingcontent-addressable read/write memories suitable for VLSIimplementation. Snyder, Wesley E., + , T-C Oct 82 963-968

Associative processingbit-serial parallel processing systems; airborne associative processor and

ground-based massively parallel processor. Batcher, Kenneth E., T-CMay 82 377-384

Asynchronous sequential logic circuit testingsynchronizer circuits; anomalous behavior of flip-flops in response to

logically undefined input conditions. Fleischhammer, W, + , T-CMar 79 273-276. t

Asynchronous sequential logic circuitsdirect implementation of asynchronous control units. Hollaar, Lee A., T-CDec82 1133-1141

Automata; cf. Stochastic automata

B

BibliographiesVLSI logic; design for testability. Williams, Thomas W., + , T-CJan 82

2-15Binary arithmetic; cf. ArithmeticBiomedical imaging, X-ray; cf. Tomography, X-rayBroadcast channels

local area network measurement center of US National Bureau ofStandards. Amer, PaulD., T-CAug 82 723-729

Buffer memories; cf. Cache memoriesBuffered communication; cf. Message switchingBusiness economics; cf. Communication system economics; Computer

economics

C

Cache memoriescache coherency effects in multiprocessors. Dubois, Michel, - , T-CNov 82 1083-1099

microprocessors with private cache memories and single shared mainmemory; analysis. Patel, Janak H., T-CApr 82 296-304

Cellular logicgeneral-purpose high-speed logical transform image processor. Herron, J.M, + , T-CAug82795-800

Circuit topology; cf. TreesCircuits; cf. Graph theory; Logic circuitsClustering methods; cf. Pattern clustering methodsCMOS

abbr. ofComplementary MOS.CMOS integrated circuits, logic

symbol-sliced logic structure for VLSI implementation ofReed - Solomonencoders. Liu, Kuang Y, T-CFeb 82 170-175

Coding/decoding; cf. Arithmetic coding; Convolutional coding; Cycliccoding; Error-correction coding; Error-detection coding

Combinational logic circuit testingfault detection problems for combinational logic circuits; computational

complexity. Fujiwara, Hideo, + , T-CJun 82 555-560hierarchical path-oriented approach to fault diagnosis in modular

combinational circuits. Abramovici, Miron, T-CJul 82 672-677


large MOS combinational networks designed for testability; testing. El-Ziq, YacoubM., + , T-CFeb 82129-139

Combinational logic circuitsuniversal-logic-module realizations; comparison and application in

synthesis of combinatorial and sequential logic networks. Chen,X, + ,T-CFeb 82140-147

Combinational logic circuits; cf. AdditionCommunication system performance

local area network measurement center of US National Bureau ofStandards. Amer, PaulD., T-CAug 82 723-729

performance analysis using stochastic Petri nets. Molloy, Michael K., T-CSep 82 913-917

Communication system reliabilityfault-tolerant communication architecture for distributed processors.

Pradhan, DhirajK., + , T-CSep 82 863-870Communication system testing; cf. Communication system performanceCommunication systems; cf. Computer communication; Data

communicationCompilers; cf. Computer language processorsComponent reliability; cf. Computer reliabilityComputer arithmetic; cf. ArithmeticComputer communication

distributed supercomputer systems; combined problem of file allocationand communication network design. Irani, Keki B., + , T-CMay 82419-434

remote procedure calls for local area networks; reliability issues.Shrivastava, S. K., + , T-CJul 82 692-697

Computer communication; cf. Computer networks; Data communication;Distributed computing; Message switching; Multiprocessing,intercommunication; Multiprocessing, interconnection

Computer communication protocolsalgebra for validation of communication protocols in message passing

systems. Holzmann, GerardJ, T-CAug 82 730-738protocols used in ring-topology systems; validation techniques. Rudin,

Harry, + , T-CJu182 630-636window-random access protocols for local computer networks using

single bus. Towsley, Don, + , T-CAug82 715-722Computer control; cf. Programmable control; Specific topicComputer economics

allocation of operations in distributed database access; model that usesminimization of transmission costs as optimality criterion. Cer,Stefano, + , T-CFeb82119-129

optimal query processing policy for distributed database systems; modelleading to minimum operating cost. Chu, Wesley W, + , T-C Sep 82835-850

Computer fault toleranceclosed-form solutions of performability. Meyer, John F., T-C Jul 82

648-657distributed reconfiguration strategies for shared-memory fault-tolerant

multiprocessor systems. Clarke, Edmund M., + , T-C Aug 8277 1-784

Extra Stage Cube fault-tolerant interconnection network for use in large-scale parallel and distributed supercomputer systems. Adams, GeorgeB., III, + , T-CMay 82 443-454

REBUS fault-tolerant distributed system for industrial real-time controLAyache, Jean-Michel, + , T-CJul 82 637-647

reliable and fault-tolerant computing; special issue. T-CJul 82 575-706reliable and fault-tolerant computing; special issue foreword. Hong, Se

June, Guest ed., T-CJul82 575-577SIFT fault-tolerant flight control system; formal specification and


Computer fault tolerance; cf. Computer reliability; Computer software faulttolerance; Digital system fault tolerance; Logic circuit fault tolerance;Memory fault tolerance

Computer language processorsregular expression compiler for custom VLSI layout; implementation of

recognizers using networks of programmable logic arrays. Trickey,Howard W., T-CJun 82 514-520

Computer languagesaddressing methods in block-structured languages; performance analysis.DePrycker, Martin, T-CFeb 82 155-163

D-algorithm generalization to circuits containing functional modulesdescribed in computer hardware description languages. Levendel,YtzhakH., + , T-CJul82577-588

portable measurement system for high-level language program statistics.DePrycker, Martin, T-CSep 82 883-891

wavefront-based language and architecture for programmable special-purpose VLSI multiprocessor array. Kung, Sun- Yuan, + , T-C Nov82 1054-1066

Computer networkscomparing serial computers, arrays, and networks using measures of

'active resources'. Uhr, Leonard, T-C Oct82 1022-1025local area network measurement center of US National Bureau of

Standards. Amer, Paul D., T-CAug 82 723-729



local network system for real-time management of imagery data, Star.Wu, Chuan-lin, + , T-C Oct 82 923-933

window-random access protocols for local computer networks usingsingle bus. Towsley, Don, + , T-CAug82715-722

Computer networks; cf. Computer communication; Distributed computing;Minicomputer networks

Computer operating systems; cf. Computer software, operating systemsComputer performance

closed-form solutions of performability. Meyer, John F., T-C Jul 82648-657

comparing serial computers, arrays, and networks using measures of'active resources'. Uhr, Leonard, T-COct82 1022-1025

computer performance models of parallel processing systems in which jobsubdivides into two or more asynchronous tasks; queueing networkmodels. Heidelberger, Philip, + , T-CNov 82 1099-1109

local area network measurement center of US National Bureau of.Standards. Amer, PaulD., T-CAug82 723-729

multiple-bus multiprocessor systems; Markovian models for performanceevaluation. Marsan, Marco Ajmone, + , T-CMar 82 239-248

single-bus multiprocessor architectures; comparative performanceanalysis using Markov models. Marsan Ajmone, Marco, + , T-CDec82 1179-1 191

Computer performance; cf. Computer software performanceComputer peripherals

failure processes in digital computers due to hardware transients;modeling methodology. Castillo, Xavier, + , T-CJuJ82 658-671

Computer pipeline processingBurroughs Scientific Processor, BSP; high-performance scientificcomputer combining parallelism and pipelining with conflict-freeaccess to arrays in parallel memory. Kuck, David J, + , T-CMay 82363-376

Control Data Cyber 205; technological and design tradeoffs. Lincoln, NeilR., T-CMay 82 349-362

dictionary machine suitable for VLSI implementation. Ottmann, ThomasA., + , T-CSep 82 892-897

parallel enumeration sorting scheme suitable for VLSI implementation.Yasuura, Hiroto, + , T-CDec 82 1192-1201

pipelined pseudoparallel system architecture for real-time dynamic sceneanalysis. Agrawal, Dharma P., + , T-COct 82 952-962

railroad track flaws classification in real-time using multimicroprocessorsystem. Sholl, Howard A., + , T-COct 82 1009-1017

supersystem technology and architecture. Swartzlander, Earl E., Jr., +T-CMay 82 399-409

systolic processing of signals and images; VLSI implementation.Kulkarni, Ashok V., + , T-COct 82 1000-1009

Computer pipeline processing; cf. Parallel processingComputer power supplies

failure processes in digital computers due to hardware transients;modeling methodology. Castillo, Xavier, + , T-CJul 82 658-671

Computer programming; cf. Computer languages; Computer softwareComputer reliability

automatic generation of symbolic reliability functions for processor -memory - switch interconnection structures. Kini, Vittal, + , T-CAug 82 752-771

failure in distributed computing systems; election of coordinator node forreorganization. Garcia-Molina, Hector, T-CJan 8248-59


single-byte error correcting - double-byte error detecting codes forincreased memory reliability. Kaneda, Shigeo, + , T-CJul 82 596-602

statistical computer failure/load relationship. Iyer, RavishankarK., +T-CJul82 697-706

Computer reliability; cf. Computer fault tolerance; Computer softwarereliability

Computer Society; cf. IEEE Computer SocietyComputer software; cf. Specific application or topicComputer software fault tolerance

error correction in robust data structures. Taylor, David J, + , T-C Jul82602-608

programmed exception handling and default exception handling based onautomatic backward recovery; unified point of view. Cristian, Flaviu,T-CJun 82 531-540

self-checking and self-stabilizing programs; verification and use ofexecutable assertions in detection and recovery from program errors.Mili, Ali, T-CJul82 685-689

Computer software fault tolerance; ef. Computer software reliabilityComputer software, language processors; cf. Computer language processorsComputer software metrics

portable measurement system for high-level language program statistics.DePrycker, Martin, T-CSep 82883-891

Computer software, operating systemsdeadlock-free systems for bounded number of processes; resource

allocation. Ibaraki, Toshihide, + , T-CMar 82 188-193multicomputer system with dynamic architecture; software techniques for

distributing hardware resources among user programs. Kartashev,Svetlana P., + , T-CJun 82 488-514


Computer software, operating systems; cf. Computer language processors;Data management; Multiprocessing

Computer software performancecounterintuitive behavior of some parallel algorithms; study using

probabilistic model of class of parallel algorithms. Weide, Bruce W, T-CNov82 1126-1130

expression model for extraction and evaluation of parallelism in controlstructures. Wei, Martin C., + , T-CSep 82 851-863

Computer software performance; cf. Computer software metricsComputer software reliability

remote procedure calls for local area networks; reliability issues.Shrivastava, S. K., + , T-CJul 82 692-697

Computer software reliability; cf. Computer software fault toleranceComputer software requirements and specificationsSIFT fault-tolerant flight control system; formal specification and


Computer software testing; cf. Computer software verificationComputer software verification

error detection; use of watchdog processors in implementation ofstructural integrity checking. Lu, DavidJun, T-CJul 82 681-685

self-checking and self-stabilizing programs; verification and use ofexecutable assertions in detection and recovery from program errors.Miit, Ali, T-CJuI 82 685-689

totally self-checking checker for 1-out-ofn code using two-rail codes.Khakbaz, Javad, T-CJul 82 677-681

Computer testing; cf. Computer performance; Computer softwareverification; Logic circuit testing; Memory testing

Computersspecial issue on supersystems. T-CMay 82 345-473special issue on supersystems; foreword. Kartashev, Svetlana P., Guest

ed., T-CMay 82 345-348Computers; cf. Computer pipeline processing; Database systems;

Distributed computing; Memories; Microcomputers;Microprogramming; Military computers; Multiprocessing; Parallelprocessing

Content-addressable memories; cf. Associative memoriesControl systems; cf. Correlation methods; Distributed control; Industrial

controlConvolution


Convolutional codingmemory protection technique in which individually code-protectedmemory cells are supplemented with convolutionally encodedredundant cells. Metzner, John J, T-CJun 82 547-551

Correlation methodsimage correlation; multimicroprocessor systems using single instruction

stream - multiple data stream parallelism. Siegel, Leah J, + , T-CMar 82 208-218

nonrecursive digital filtered pseudorandom p-level maximal-lengthsequences; autocorrelation function. Wustmann, Gerhard, T-C Jan 8275-77

Costs; cf. Communication system economics; Computer economicsCounting circuits

generalized parallel counter synthesized from network of smaller ones;upper bound to number of levels required. Dormido, S., + , T-CAug82 802-805

Cryptographyminimization method for modulo-2 expansion of switching function;

application to 32 data encryption standard select functions of sixvariables. Robinson, John P., + , T-CAug 82 800-801

Cyclic codingsingle asymmetric error-correcting cyclic AN codes. Shiozaki, Akira, T-CJun 82 554-555

D

Data communication; cf. Computer communication; Message switchingData management

allocation of operations in distributed database access; model that usesminimization of transmission costs as optimality criterion. Ceri,Stefano, + , T-CFeb 82 119-129

data flow computer architecture with program and token memories.Sowa, Masahiro, +, T-CSep 82 820-824

data movements in multidimensional store on array processor consideredin terms of changes to data mapping rather than physical datamovement. Flanders, PeterM., T-CSep 82 809-819

distributed supercomputer systems; combined problem of file allocationand communication network design. Irani, Keki B., + , T-CMay 82419-434

error correction in robust data structures. Taylor, David J., + , T-C Jul82602-608



Data management; cf. Database management systems; Database systemsData processing; cf. Image processing; List processingData security; cf. CryptographyData transmission; cf. Data communicationDatabase management systems

deadlock-free systems for bounded number of processes; resourceallocation. Ibaraki, Toshihide, + , T-CMar82 188-193

Database systems; cf. Distributed database systems; File systems; Imagedatabases

Database systems, relationalassociative searching of relational databases supported by magnetic

bubble memories. Strader, NoelR., II, T-CMar 82 265-266entity-oriented relational database system for spatial information;

application to watershed data Vaidya, Prashant D., + , T-C Oct 821025-1031

Database systems, relational; cf. Distributed database systems, relationalDatabase systems, searching


hardware-based hashing scheme in design of multiterm string comparatorfor text retrieval. Burkowski, Forbes J., T-CSep 82 825-834

optimal query processing policy for distributed database systems; modelleading to minimum operating cost. Chu, Wesley W, + , T-C Sep 82835-850

Decentralized ...; cf. Distributed ...

Decision procedures; cf. Pattern classificationDifferential equations; cf. Partial differential equationsDigital arithmetic; cf. ArithmeticDigital communication; cf. Data communicationDigital filters; cf. Nonrecursive digital filtersDigital image processing; cf. Image processingDigital integrated circuits

canonical bit-sequential multiplier suitable for VLSI implementation.Strader, NoelR., II, + , T-CAug82 79 1-795




pin limitations and partitioning of VLSI interconnection networks.Franklin, MarkA., + , T-CNov82 1109-1116

residue arithmetic multipliers that overcome moduli size limitation byusing VLSI technology, special architectures, and moduli choice.Taylor, FredJ, T-CJun 82 540-546

special-purpose VLSI arrays; analysis and synthesis of VLSI algorithmsbased on transformations of index sets. Moldovan, Dan I, T-CNov 821121-1126


VLSI; embedding rectangular grids in square grids. Aleliunas,Romas, + , T-CSep 82 907-913

Digital integrated circuits; cf. Microcomputers; Semiconductor logiccircuits; Semiconductor memories

Digital signal ...; cf. SignalDigital system fault tolerance

containment set approach to upsets in digital systems. Glaser, RobertE., + , T-CJuJ82 689-692

dedicated distributed systems; protection against external errors. Bellon,Catherine, + , T-CApr82 311-317

fault-tolerant communication architecture for distributed processors.Pradhan, DhirajK., + , T-CSep 82 863-870

Digital system fault tolerance; cf. Computer fault tolerance; Logic circuitfault tolerance; Memory fault tolerance

Digital system testinginformation-theoretic approach for generation of near-optimum

sequential fault location experiments. Varshney, Pramdod K., + , T-CFeb 82 164-170

Digital system testing; cf. Computer testing; Logic circuit testing; Memorytesting

Distributed computingdelay and throughput analysis with balanced HDLC procedures. Wang,

Jinpo, T-CAug82 739-746distributed supercomputer systems; combined problem of file allocationand communication network design. Irani, Keki B., + , T-CMay 82419-434

expression model for extraction and evaluation of parallelism in controlstructures. Wei, Martin C, + , T-CSep 82 851-863

failure in distributed computing systems; election of coordinator node forreorganization. Garcia-Molina, Hector, T-CJan 82 48-59

fault-tolerant communication architecture for distributed processors.Pradhan, DhirajK., + , T-CSep 82 863-870

multicomputer system with dynamic architecture; software techniques fordistributing hardware resources among user programs. Kartashev,Svetlana P., + , T-CJun 82488-514


parallel sollution of partial differential equations on distributedcomputing system. Gelenbe, Erol, + , T-CDec 82 1157-1164

programmable digital signal processors; architecture of Bell LaboratoriesSynchronous Distributed Processor. Shively, Richard R., T-C Jan 8216-22

protocols used in ring-topology systems; validation techniques. Rudin,Harry, + , T-C Jul 82630-636

real-time supersystems; modular approach using very high speedintegrated circuit technology. Arnold, Robert G., + , T-C May 82385-398

remote procedure calls for local area networks; reliability issues.Shrivastava, S. K., + , T-CJul82 692-697

SIFT fault-tolerant flight control system; formal specification andmechanical verification. Melliar-Smith, P. Michael, + , T-C Jul 82616-630

special issue on parallel and distributed processing T-C Nov 821033-1130

special issue on parallel and distributed processing; foreword Liu, MingT, Guest ed., + , T-CNov82 1033-1035

special issue on supersystems. T-CMay 82 345473special issue on supersystems; foreword. Kartashev, Svetlana P., Guest

ed., T-CMay 82 345-348supersystem technology and architecture. Swartzlander, EarlE., Jr., +T-CMay 82 399-409

supersystems; multicriteria approach to architecture definition. Ignizio,JamesP., + , T-CMay82410-418

task allocation model for distributed computing systems. Ma, Perng-YiRichard, + , T-CJan 8241-47

Distributed computing; cf. Computer communication; Distributed databasesystems; Microcomputer networks; Multiprocessing

Distributed controldedicated distributed systems; protection against external errors. Bellon,

Catherine, + , T-CApr 82 311-317Distributed database systems

allocation of operations in distributed database access; model that usesminimization of transmission costs as optimality criterion. Ceri,Stefano, + , T-CFeb 82 119-129

local network system for real-time management of imagery data, Star.Wu, Chuan-lin, + , T-COct 82923-933

optimal query processing policy for distributed database systems; modelleading to minimum operating cost. Chu, Wesley W., + , T-C Sep 82835-850

Distributed database systems, relationalprocessing of general equijoin queries in distributed relational databases.

Cheung, To-Yat, T-CAug 82 746-751Dynamic programming

regular expression compiler for custom VLSI layout; implementation ofrecognizers using networks of programmable logic arrays. Trickey,Howard W, T-CJun 82514-520

E

Economics; cf. Communication system economics; Computer economicsElectromagnetic transient analysis


Error-correction codingreliability of memory with single-error correction. Mikhail, W F, +T-CJun 82 560-564


unidirectional error correcting/detecting codes; theory. Bose, Bella, +T-CJun 82 521-530

unidirectional error-correcting/detecting codes; class of optimal t-error-correcting and multiple unidirectional error-detecting systematic codes.Bose, Bella, + , T-CJun 82 564-568

Error-correction coding; cf. Arithmetic coding; Convolutional coding;Cyclic coding; Reed - Solomon coding

Error-detection codingsingle-byte error correcting - double-byte error detecting codes for

increased memory reliability. Kaneda, Shigeo, + , T-CJul 82 596-602totally self-checking checker for l-out-ofn code using two-rail codes.Khakbaz, Javad, T-CJu]82 677-681

unidirectional error correcting/detecting codes; theory. Bose, Bella, +T-CJun 82 521-530

unidirectional error-correcting/detecting codes; class of optimal t-error-correcting and multiple unidirectional error-detecting systematic codes.Bose, Bella, + , T-CJun 82 564-568



F

Failure analysis; cf. System reliabilityFast transforms; cf. TransformsFault tolerance; cf. Computer fault tolerance; Computer software fault

tolerance; Digital system fault tolerance; Logic circuit fault tolerance;Memory fault tolerance

Faults; cf. Digital system testingFET integrated circuits, logic; cf. CMOS integrated circuits, logic; MOS

integrated circuits, logicFile systems

distributed supercomputer systems; combined problem of file allocationand communication network design. Irani, Keki B., + , T-C May 82419-434

optimal file assignment in storage hierarchy. Geist, Robert M, + , T-CMar82 249-260

Filters; cf. Digital filtersFinite-state automata; cf. Sequential logic circuitsFinite-wordlength effects

multioperand addition of Koren's generalized number system. Bhuyan,LaxmiN., + , T-CApr82335-338

Firmware; cf. MicroprogrammingFlight control; cf. Aircraft controlFlip-flops

synchronizer circuits; anomalous behavior of flip-flops in response tologically undefined input conditions. Fleischhammer, W., +, T-CMar 79 273-276. t

Floating-point arithmeticcomputer representation of real numbers; extension of Hwang's model.

Gerrity, George W, T-CAug 82709-714loss of significance in floating point addition or subtraction. Feldstein,

Alan, + , T-CApr 82 328-335online floating-point square-root algorithm. Oklobdzija, Vojin G., +T-CJan 82 70-75

G

Geometric programmingoptimal illumination region algorithm for convex polygons. Lee, Der-

Tsai, + , T-CDec 821225-1227Geometry

computational geometry; reporting and counting all pairs of intersectingor overlapping d-ranges in given set of d-ranges. Six, Hans W, + , T-CMar82 181-187

point enclosure problem; solution in plane using S-tree static datastructure. Vaishnavi, Vijay K, T-CJan 82 22-29

Geophysical measurements; cf. Terrain mappingGraph theory

dense trivalent graphs for processor interconnection. Leland, WillE., + , T-CMar 82 219-222

distributed algorithm for finding all shortest paths. Chen, C C., T-C Sep82 898-899

(d,k) graph problem; new results. Memmi, Gerard, + , T-C Aug 82784-791

multicomputer interconnection network geometry; multitree-structuredinterconnection graph. Arden, Bruce W., + , T-CJan 82 60-69

Graph theory; cf. TreesGroup theory

algebraic model of arithmetic codes. Chen, Chung Ho, T-C Apr 82318-321

H

Haar transformsfast Haar transform algorithms. Roeser, Peter R., + , T-C Feb 82

175-177Hierarchical memories; cf. Memory hierarchiesHierarchical systems

distributed software for hierarchical multiprocessors. Deminet, Jarek, T-CApr82 278-288

hierarchical path-oriented approach to fault diagnosis in modularcombinational circuits. Abramovici, Miron, T-CJul 82 672-677

HM2p hierarchical multimicroprocessor; tree structured multiprocessorhaving two distinct hierarchies for data processing and datadistribution. Shin, KangS., + , T-CNov82 1045-1053

Hierarchical systems; cf. Memory hierarchies

I

IEEE Computer SocietyEditorial Board change. Booth, TaylorL., Ed., T-CApr 82 269


editorial staff changes. Booth, TaylorL., Ed., T-CJan 82 1IEEE Transactions on Computers; appointment of new Editor-in-Chief.

Booth, TaylorL., Ed., T-CJun 82477IEEE Transactions on Computers; Editorial Board changes. Feng, Tse-

yun, Ed., T-CJul 82 573-574referees for Jan 1980- June 1981. T-CJan 82 82-85

Image analysiscomputer management for pattern analysis and image database

management; specialissue. T-COct 82 921-1031computer architecture for pattern analysis and image database

management; special issue foreword. Chien, Y T, Guest ed., + , T-COct 82 921-922

multiprocessor architecture for pattern analysis and image databasemanagement, PUMPS. Briggs, FayeA., + , T-COct 82 969-983

Image databasescomputer architecture for pattern analysis and image database

management; special issue foreword. Chien, Y T., Guest ed., + , T-COct 82921-922

computer management for pattern analysis and image databasemanagement; special issue. T-COct 82 921-1031

entity-oriented relational database system for spatial information;application to watershed data Vaidya, Prashant D., + , T-C Oct 821025-1031

local network system for real-time management of imagery data, Star.Wu, Chuan-lin, + , T-COct 82923-933

logic for image database computer; PICCOLO logic and implementation.Yamaguchi, Kazunori, + , T-C Oct 82983-996

multiprocessor architecture for pattern analysis and image databasemanagement, PUMPS. Briggs, FayeA., + , T-COct 82969-983

Image motion analysispipelined pseudoparallel system architecture for real-time dynamic scene

analysis. Agrawal, Dharma P., + , T-COct 82 952-962Image processing

comparing serial computers, arrays, and networks using measures of,active resources'. Uhr, Leonard, T-C Oct 82 1022-1025

general-purpose high-speed logical transform image processot Herron, J.M, + , T-CAug 82 795-800

image correlation; multimicroprocessor systems using single instructionstream - multiple data stream parallelism. Siegel, Leah J, + , T-CMar82 208-2 18

multimicroprocessor system for image processing, ZMOB. Kushner,Todd, + , T-COct82 943-951

office image processing; shared-bus shared-database multimicroprocessorsystem for interactive image processing in office document system. Ni,Lione]M, + , T-COct821017-1022

parallel image processing system, PICAP. Antonsson, Dan, + , T-C Oct82997-1000


Image reconstructionimage resampling using microprocessor array operating in SIMD mode.

Warpenburg, MichaelR., + , T-COct 82 934-942Image region analysis

image region-labeling and clustering problems; parallel solution usingcontent-addressable read/write memories suitable for VLSIimplementation. Snyder, Wesley E., + , T-C Oct 82963-968

Image segmentationimage region-labeling and clustering problems; parallel solution using

content-addressable read/write memories suitable for VLSIimplementation. Snyder, Wesley E., + , T-COct 82 963-968

Industrial controlREBUS fault-tolerant distributed system for industrial real-time controLAyache, Jean-Michel, + , T-CJul 82 637-647

Industrial power system transientsfailure processes in digital computers due to hardware transients;

modeling methodology. Castillo, Xavier, + , T-CJul 82 658-671Information systems


Information theoryinformation-theoretic approach for generation of near-optimum

sequential fault location experiments. Varshney, Pramod K., + , T-CFeb 82 164-170

Integrated circuitsreal-time supersystems; modular approach using very high speed

integrated circuit technology. Arnold, Robert G., + , T-C May 82385-398

Integrated circuits; cf. Digital integrated circuits; MOS integrated circuits;Semiconductor logic circuits; Semiconductor memories

Integrated-circuit fabrication; cf. LayoutIntegrated-circuit interconnections; cf. Integrated-circuit metallization;

LayoutIntegrated-circuit measurements; cf. Integrated-circuit testing



Integrated-circuit metallizationcomputer random logic; relation between partitioning properties ofcomputer logic and distribution of connection lengths. Feuer, Michael,T-CJan 82 29-33

VLSI yield model with module redundancy; effects of interconnectdensities and logic module complexities. Mangir, TWilin Erdim, + , T-CJuJ82 609-616

Integrated-circuit testing; cf. Digital system testing; Logic circuit testingInterconnected systems; cf. Hierarchical systemsInterconnection networks

concentrators; lower bounds on required number of crosspoints.Nakamura, Shinji, + , T-CDec 82 1173-1179

multicomputer interconnection network geometry; multitree-structuredinterconnection graph. Arden, Bruce W, + , T-CJan 82 60-69

Interconnection networks; cf. Multiprocessing, interconnection;Permutation networks

Interconnection, integrated circuits; cf. Integrated-circuit metallization;Layout

L

Languageserror-correcting parsers for context-free and context-sensitive languages

with substitution, insertion, and deletion errors. Tanaka, Eiichi, +T-CJuJ 78 605-612. Correction, Apr 82 327-328

Languages; cf. Computer languagesLarge-scale systems; cf. Hierarchical systemsLayout

regular expression compiler for custom VLSI layout; implementation ofrecognizers using networks of programmable logic arrays. Trickey,Howard W, T-CJun 82 514-520

regular layout for parallel adders; application to VLSI technology. Brent,RichardP., + , T-CMar82 260-264

VLSI; embedding rectangular grids in square grids. Aleliunas,Romas, + , T-CSep 82 907-913

Lightingoptimal illumination region algorithm for convex polygons. Lee, Der-

Tsai, + , T-CDec 82 1225-1227Linear algebra; cf. MatricesList processing

error correction in robust data structures. Taylor, DavidJ., +L, T-CJul82602-608

Logarithmic arithmeticcomputer representation of real numbers; extension of Hwang's modeL

Gerrity, George W, T-CAug 82 709-714Logic

temporal logic; use for specification of hardware modules. Bochmann,Gregor V., T-CMar 82 223-231

Logic; cf. Specific topicLogic arrays

regular expression compiler for custom VLSI layout; implementation ofrecognizers using networks of programmable logic arrays. Trickey,Howard W, T-CJun 82 514-520

totally self-checking checker for 1-out-ofn code using two-rail codes.Khakbaz, Javad, T-CJul 82 677-681

Logic circuit fault tolerancepolylogic circuits; effect of component errors on behavior. Porter, W A.,

T-CJun 82 551-554VLSI yield model with module redundancy; effects of interconnect

densities and logic module complexities. Mangir, Tilin Erdim, T-CJul 82 609-616

Logic circuit testingconcurrent error detection in arithmetic and logic units by recomputing

with shifted operands. Patel, JanakH., + , T-CJul82 589-595D-algorithm generalization to circuits containing functional modules

described in computer hardware description languages. Levendel,Ytzhak H., + , T-CJul 82 577-588

VLSI logic; design for testability. Williams, Thomas W, + , T-CJan 822-15

Logic circuit testing; cf. Asynchronous sequential logic circuit testing;Combinational logic circuit testing; Sequential logic circuit testing

Logic circuits; cf. Combinational logic circuits; Counting circuits; Flip-flops; Logic arrays; Logic modules; Semiconductor logic circuits;Sequential logic circuits; Stochastic logic circuits

Logic designCMU-DA (Carnegie - Mellon University Design Automation) system;data-memory allocator for hardware synthesis at register-transfer levelfrom behavioral descriptions written in ISP language. Hafer, LouisJ, + , T-CFeb 82 93-109

Logic design; cf. Logic modulesLogic functions

minimization method for modulo-2 expansion of switching function;application to 32 data encryption standard select functions of sixvariables. Robinson, John P., + , T-CAug 82 800-801


Logic moduleslogic networks of carry - save adders based on parallel adders withminimum number of NOR gates. Lai, Hung Chi, + , T-C Sep 82870-882

LSI (large-scale integration); cf. Integrated circuits

M

Magnetic bubble memoriesassociative searching of relational databases supported by magnetic

bubble memories. Strader, Noel R., II, T-CMar82 265-266Markov processes

multiple-bus multiprocessor systems; Markovian models for performanceevaluation. Marsan, Marco Ajmone, ,v , T-CMar 82 239-248

performance analysis using stochastic Petri nets. Molloy, MichaelK., T-CSep 82 913-917

shuffle/exchange networks; interference analysis based on discreteMarkov chain model. Thanawastien, S., + , T-CAug81 545-556. t

single-bus multiprocessor architectures; comparative performanceanalysis using Markov models. Marsan Ajmone, Marco, + , T-CDec82 1179-1191

Mathematical programming; ccf. Dynamic programming; Nonlinearprogramming

Matricesalgorithm for solution of triangular systems on parallel processing system.Montoye, Robert K., + , T-CNov 82 1076-1082

large linear equation systems; elimination-tree as data structure forparallel L/U decomposition. Jess, Jochen A. G., + , T-C Mar 8223 1-239

matrix decomposition algorithm for permutation networks. Kubale,Marek, T-CMar 82 265

partitioned matrix algorithms suitable for VLSI implementation. Hwang,Kai, + , T-CDec 82 1215-1224

Matrix multiplicationsystolic processing of signals and images; VLSI implementation.

Kulkarni, Ashok V., + , T-COct 82 1000-1009Memories

temporal logic; use for specification of hardware modules. Bochmann,Gregor V., T-CMar 82 223-231

Memories; cf. Associative memories; Cache memories; Paged memories;Semiconductor memories

Memory allocation; ci. Memory managementMemory fault tolerancememory protection technique in which individually code-protectedmemory cells are supplemented with convolutionally encodedredundant cells. Metzner, John J, T-CJun 82 547-551

reliability of memory with single-error correction. Mikhail, W. F, +T-CJun 82 560-564

Memory hierarchiesmultilevel delayed-staging storage hierarchies; determination of fault

ratios. Silberman, GabrielM, T-CApr82 305-3 10optimal file assignment in storage hierarchy. Geist, Robert M., + , T-CMar 82 249-260

Memory managementBurroughs Scientific Processor, BSP; high-performance scientific

computer combining parallelism and pipelining with conflict-freeaccess to arrays in parallel memory. Kuck, David J, + , T-CMay 82363-376

conflict-free parallel array access memory based on use of prime numberof memories and powerful combination of indexing hardware and dataalignment switches. Lawrie, Duncan H., + , T-CMay 82435-442

memory access conflict in synchronous multiprocessor system with Nprocessors andM shared memories. Yen, David W. L., + , T-CNov82 1116-1121

memory access conflicts; orderly resolution among competing channelprocesses. Kiuge, WernerE., + , T-CMar 82 194-207

multiprocessor scheduling with memory allocation; deterministicapproach. W9glarz, J., T-CAug 80 703-709. t

Memory management; cf. Data management; Memory hierarchiesMemory testing

multilevel delayed-staging storage hierarchies; determination of faultratios. Silberman, GabrielM., T-CApr 82 305-3 10

Message switchingalgebra for validation of communication protocols in message passing

systems. Holzmann, GerardJ, T-CAug82 730-738message-oriented interprocessor communication network utilizing simple

fixed algorithm to store-and-forward short messages over directed datalines. Riley, DavidD., + , T-CFeb82 10-118

Metallization; cf. Integrated-circuit metallizationMicrocomputer applications; cf. Specific topicMicrocomputer networks

augmented data manipulator networks; number of possible connectionpermutations achieved by last stage. O'Donnell, Michael J., + , T-CFeb 82 163-164



image resampling using microprocessor array operating in SIMD mode.Warpenburg, MichaelR., + , T-COct 82934-942

multicomputer interconnection network geometry; multitree-structuredinterconnection graph. Arden, Bruce W, + T-CJan 8260-69

multimicroprocessor system for image processing, ZMOB. Kushner,Todd, + , T-C Oct 82 943-951

office image processing; shared-bus shared-database multimicroprocessorsystem for interactive image processing in office document system. Ni,LionelM., + , T-COct 82 1017-1022

railroad track flaws classification in real-time using multimicroprocessorsystem. Sholl, HowardA., + T-COct 82 1009-1017

REBUS fault-tolerant distributed system for industrial real-time control.Ayache, Jean-Michel, + , T-CJuI82 637-647

Microcomputer software; cf. Specific applicationMicroprocessorsprogrammable digital signal processors; architecture of Bell Laboratories'

Synchronous Distributed Processor. Shively, Richard R., T-C Jan 8216-22

Microprocessors; cf. Microcomputer networks; MultiprocessingMicroprogramming

synthesis and optimization of programs by P-functions. Thayse, Andre, T-CJan 82 34-40

two-level microprogrammed multiprocessor for nonnumeric problems.Baba, Takanobu, + , T-CDec 82 1142-1156

Military computersreal-time supersystems; modular approach using very high speed


Missile computersreal-time supersystems; modular approach using very high speed


MOS

abbr. ofMetal-oxide-semiconductor.MOS integrated circuits, logic

large MOS combinational networks designed for testability; testing. El-Ziq, Yacoub M., + , T-CFeb 82 129-139

totally self-checking checker for l-out-ofn code using two-rail codes.Khakbaz, Javad, T-CJul 82 677-681

MOS integrated circuits, logic; cf. CMOS integrated circuit, logicMOSFET circuits; cf. MOS integrated circuitsMotion measurement; cf. Image motion analysisMultidimensional signal processing; cf. Image processingMultilevel systems; cf. Hierarchical systemsMultiplication

canonical bit-sequential multiplier suitable for VLSI implementation.Strader, Noel R.,II, + , T-CAug 82 791-795

generalized parallel'counter synthesized from network of smaller ones;upper bound to number of levels required. Dormido, S., + , T-CAug82 802-805

logic networks of carry - save adders based on parallel adders withminimum number of NOR gates. Lai, Hung Chi, +, T-C Sep 82870-882

0(n) parallel multiplier with bit-sequential input and out. Sips, H. J., T-CApr82 325-327


Multiprocessingcache coherency effects in multiprocessors. Dubois, Michel, + , T-CNov82 1083-1099

data flow computer architecture with program and token memories.Sowa, Masahiro, + , T-CSep 82 820-824

distributed reconfiguration strategies for shared-memory fault-tolerantmultiprocessor systems. Clarke, Edmund M, + , T-C Aug 82771-784

distributed software for hierarchical multiprocessors. Deminet, Jarek, T-CApr82 278-288

HM2p hierarchical multimicroprocessor; tree structured multiprocessorhaving two distinct hierarchies for data processing and datadistribution. Shin, KangS., + , T-CNov 82 1045-1053

memory access conflict in synchronous multiprocessor system with Nprocessors and M shared memories. Yen, David W. L., + , T-CNov82 1116-1121

microprocessors with private cache memories and single shared mainmemory; analysis. Patel, Janak H., T-CApr 82 296-304

MP/C multiprocessor/computer architecture for concurrent computing.Arden, Bruce W, + , T-CMay 82 455-473

multiprocessor architecture for pattern analysis and image databasemanagement, PUMPS. Biggs, Fay6A., + , T-COct 82 969-983

multiprocessor scheduling with memory allocation; deterministicapproach. Wfglarz, J., T-CAug 80 703-709. t

single-bus multiprocessor architectures; comparative performanceanalysis using Markov models. Marsan Ajmone, Marco, + , T-CDec82 1179-1 191


transformation of large networks into quotient networks that emulate thelarge networks with fewer processors. Fishburn, John P., + , T-CApr82288-295

two-level microprogrammed multiprocessor for nonnumeric problems.Baba, Takanobu, + , T-CDec 821142-1156

Multiprocessing; cf. Distributed computing; Microcomputer networks;Parallel processing

Multiprocessing, intercommunicationminimization of interprocessor communication for parallel computation.

Irani, KekiB., + , T-CNov82 1067-1075task allocation model for distributed computing systems. Ma, Perng-Yi

Richard, + , T-CJan 8241-47Multiprocessing, interconnectionaugmented data manipulator network in MIMD systems; routing

schemes. McMillen, RobertJ, + , T-CDec 82 1202-1214augmented data manipulator networks; number of possible connection

permutations achieved by last stage. O'Donnell, Michael J, + , T-CFeb 82 163-164

automatic generation of symbolic reliability functions for processor -memory - switch interconnection structures. Kini, Vittal, + , T-CAug 82 752-771

crossbar and multiple-bus connections; effective bandwidth. Lang,Tomas, + , T-CDec82 1227-1234

dense trivalent graphs for processor interconnection. Leland, WillE., + , T-CMar 82 219-222

Extra Stage Cube fault-tolerant interconnection network for use in large-scale parallel and distributed supercomputer systems. Adams, GeorgeB., III, + , T-CMay 82 443-454

message-oriented interprocessor communication network utilizing simplefixed algorithm to store-and-forward short messages over directed datalines. Riley, DavidD., + , T-CFeb 82 1 1 8118

minimization of interprocessor communication for parallel computation.Irani, KekiB., + , T-CNov82 1067-1075

multiple-bus multiprocessor systems; Markovian models for performanceevaluation. Marsan, MarcoAjmone, + , T-CMar 82 239-248

optimal BPC permutations on cube-connected SIMD computer. Nassimi,David, + , T-CApr82338-341

pin limitations and partitioning of VLSI interconnection networks.Franklin, Mark A., + , T-CNov 82 1109-1116

shuffle/exchange networks; interference analysis based on discreteMarkov chain model. Thanawastien, S., +, T-CAug81545-556. t

SIMD machines with Augmented Data Manipulator interconnectionnetwork; number of distinct data permutations performable in singlepass through ADM network. Adams, George B., III, + , T-CApr 82270-277

Multivibrators; cf. Flip-flops

N

Nets; cf. Petri netsNetworks; cf. Circuits; Computer communicationNonrecursive digital filters

nonrecursive digital filtered pseudorandom p-level maximal-lengthsequences; autocorrelation function. Wustmann, Gerhard, T-CJan 8275-77

Numerical methods; cf. Arithmetic; Matrices; Partial differential equations

0

Office automationoffice image processing; shared-bus shared-database multimicroprocessor

system for interactive image processing in office document system. Ni,Lione/M., + ,T-COct821017-1022

Operating systems; cf. Computer software, operating systemsOptimization methods; cf. Dynamic programmingOrthogonal transforms; cf. Transforms

P

Parallel processingalgorithm for solution of triangular systems on parallel processing system.Montoye, Robert K., + , T-CNov 82 1076-1082

bit-serial parallel processing systems; airborne associative processor andground-based massively parallel processor. Batcher, Kenneth E., T-CMay 82 377-384

Burroughs Scientific Processor, BSP; high-performance scientificcomputer combining parallelism and pipelining with conflict-freeaccess to arrays in parallel memory. Kuck, David J., + , T-CMay 82363-376

comparing serial computers, arrays, and networks using measures of'active resources'. Uhr, Leonard, T-COct 82 1022-1025


IEEE T-C 1982 INDEX -1I

computer performance models of parallel processing systems in which jobsubdivides into two or more asynchronous tasks; queueing networkmodels. Heidelberger, Philip, + , T-CNov 82 1099-1 109

conflict-free parallel array access memory based on use of prime numberof memories and powerful combination of indexing hardware and dataalignment switches. Lawrie, Duncan H., + , T-CMay 82 435-442

counterintuitive behavior of some parallel algorithms; study usingprobabilistic model of class of parallel algorithms. Weide, Bruce W., T-CNov82 1126-1130

data movements in multidimensional store on array processor consideredin terms of changes to data mapping rather than physical datamovement. Flanders, PeterM, T-CSep 82 809-819

ETH-multiprocessor EMPRESS; dynamically configurable multiple-instruction stream - multiple-data stream system capable of handlingtwo-stage parallelism. Buebrer, Richard E., + , T-C Nov 821035-1044

expression model for extraction and evaluation of parallelism in controlstructures. Wei, Martin C., + , T-CSep 82 851-863

Fortran-like loops; improved time and parallel processor bounds. Heuft,Richard W, + , T-CJan 82 78-81

general-purpose high-speed logical transform image processor. Herron, J.M., + , T-CAug 82 795-800

generalized parallel counter synthesized from network of smaller ones;upper bound to number of levels required. Dormido, S., + , T-CAug82 802-805

image correlation; multimicroprocessor systems using single instructionstream - multiple data stream parallelism. Siegel, Leah J., + , T-CMar82 208-218


image resampling using microprocessor array operating in SIMD mode.Warpenburg, MichaelR., + , T-C Oct 82 934-942


local network system for real-time management of imagery data, Star.Wu, Chuan-lin, + , T-COct 82 923-933

logic for image database computer; PICCOLO logic and implementation.Yamaguchi, Kazunori, -1 , T-COct 82983-996

multimicroprocessor system for image processing, ZMOB. Kushner,Todd, + , T-C Oct 82 943-951

0(n) parallel multiplier with bit-sequential input and out. Sips, H. J., T-CApr82 325-327


parallel image processing system, PICAP. Antonsson, Dan, + , T-C Oct82997-1000


partitioned matrix algorithms suitable for VLSI implementation. Hwang,Kai, + , T-CDec 821215-1224

pipelined pseudoparallel system architecture for real-time dynamic sceneanalysis. Agra wal, Dharma P, + , T-C Oct 82952-962

special issue on parallel and distributed processing T-C Nov 821033-1130

special issue on parallel and distributed processing; foreword. Liu, MingT, Guest ed., + , T-CNov 82 1033-1035

special issue on supersystems. T-CMay 82 345-473special issue on supersystems; foreword. Kartashev, Svetlana P., Guest

ed., T-CMay 82 345-348special-purpose VLSI arrays; analysis and synthesis of VLSI algorithms

based on transformations of index sets. Moldovan, Dan L, T-CNov 821121-1126

supersystem technology and architecture. Swartzlander, Earl E., Jr., +T-CMay 82399-409


Parallel processing; cf. Computer pipeline processing; MultiprocessingPartial differential equations


Pattern classificationk-nearest neighbor Voronoi diagrams in plane. Lee, Der-Tsai, T-CJun 82

478-487railroad track flaws classification in real-time using multimicroprocessor

system. Sholl, HowardA., + , T-COct 82 1009-1017Pattern clustering methods

image region-labeling and clustering problems; parallel solution usingcontent-addressable read/write memories suitable for VLSIimplementation. Snyder, WesleyE., + , T-COct 82963-968

Pattern recognitionregular expression compiler for custom VLSI layout; implementation of

recognizers using networks of programmable logic arrays. Trickey,Howard W, T-CJun 82 514-520


Pattern recognition; cf. Image analysis; Pattern classificationPermutation networksaugmented data manipulator networks; number of possible connection

permutations achieved by last stage. O'Donnell, Michael J., + , T-CFeb 82 163-164

Benes permutation network; paral/lel algorithm to determine switchsettings. Nassimi, David, + , T-CFeb 82 148-154

matrix decomposition algorithm for permutation networks. Kubale,Marek, T-CMar82 265

SIMD machines with Augmented Data Manipulator interconnectionnetwork; number of distinct data permutations performable in singlepass through ADM network. Adams, George B., III, + , T-CApr 82270-277

Permutationsoptimal BPC permutations on cube-connected SIMD computer. Nassimi,David, + , T-CApr82 338-341

Petri netsperformance analysis using stochastic Petri nets. Molloy, Michael K., T-CSep 82 913-917

Picture processing; cf. Image processingPipeline processing; cf. Computer pipeline processingPower supplies; cf. Computer power suppliesProbability

counterintuitive behavior of some parallel algorithms; study usingprobabilistic model of class of parallel algorithms. Weide, Bruce W., T-CNov82 1126-1130

Programmable controlprogrammable digital signal processors; architecture of Bell Laboratories'


Programming; cf. Computer languages; Microcomputer software; Specificapplication

Pseudorandom sequences; cf. Shift-register sequencesPulse analysis; cf. Electromagnetic transient analysis

QQueuing analysiscomputer performance models of parallel processing systems in which job

subdivides into two or more asynchronous tasks; queueing networkmodels. Heidelberger, Philip, + , T-CNov 82 1099-1 109

R

Rail transportationrailroad track flaws classification in real-time using multimicroprocessor

system. Sholl, HowardA., + , T-COct 82 1009-1017Random ...; cf. Probability; Stochastic ...

Random number generation; cf. Pseudorandom number generationRecurrent coding; cf. Convolutional codingReed - Solomon coding

symbol-sliced logic structure for VLSI implementation ofReed - Solomonencoders. Liu, Kuang Y., T-CFeb 82 170-175

Registers; cf. Shift registersRelaxation oscillators; cf. Flip-flopsReliability; cf. System reliabilityResidue arithmetic

autoscale residue multiplier which inhibits dynamic range overflow.Taylor, FredJ, + , T-CApr82 321-325


Roundoff errors; cf. Finite wordlength effects

S

Sampling methods; cf. Signal sampling/reconstructionSatellite computers; cf. Space-vehicle computersSearch methods; cf. Database systems, searching; Information systemsSemiconductor device testing; cf. Integrated-circuit testingSemiconductor logic circuitscomputer random logic; relation between partitioning properties of

computer logic and distribution of connection lengths. Feuer, Michael,T-CJan 82 29-33

VLSI yield model with module redundancy; effects of interconnectdensities and logic module complexities. Mangir, Tulin Erdim, + , T-CJul 82 609-616

Semiconductor logic circuits; cf. CMOS integrated circuits, logic; Logiccircuit testing; MOS integrated circuits, logic

Semiconductor memoriesreliability of memory with single-error correction. Mikhail, W F., +,T-CJun 82560-564




Sequences; cf. Shift-register sequencesSequential logic circuit testing

fault diagnosis based on effect - cause analysis. Abramovici, Miron, +T-CDec 821165-1172

Sequential logic circuit testing; cf. Asynchronous sequential logic circuittesting

Sequential logic circuitsuniversal-logic-module realizations; comparison and application in

synthesis of combinatorial and sequential logic networks. Chen,X, +, T-CFeb 82 140-147T

Sequential logic circuits; cf. Asynchronous sequential logic circuits;Automata

Shift-register sequencesnonrecursive digital filtered pseudorandom p-level maximal-length

sequences; autocorrelation function. Wustmann, Gerhard, T-C Jan 8275-77

Signal processingprogrammable digital signal processors; architecture of Bell Laboratories'


systolic processing of signals and images; VLSI implementation.Kulkarni, Ashok V., +, T-COct82 1000-1009


Signal processing; cf. Image processingSignal sampling/reconstruction; cf. Image reconstructionSite security monitoring

optimal illumination region algorithm for convex polygons. Lee, Der-Tsai, + , T-CDec 82 1225-1227

Software; cf. Computer softwareSorting/merging


Source coding; cf. Arithmetic codingSpace-vehicle computers

real-time supersystems; modular approach using very high speedintegrated circuit technology. Arnold, Robert G., + , T-C May 82385-398

Special issuescomputer architecture for pattern analysis and image databasemanagement T-C Oct 82 921-1031

parallel and distributed processing. T-CNov 82 1033-1130reliable and fault-tolerant computing. T-CJul 82 575-706supersystems; current state-of-the-art. T-CMay 82 345-473

Square-rootingonline floating-point square-root algorithm. Oklobdzija, Vojin G., +

T-CJan 82 70-75Stochastic automata

optimal illumination region algorithm for convex polygons. Lee, Der-Tsai, + , T-CDec 82 1225-1227

Stochastic logic circuitscomputer random logic; relation between partitioning properties of

computer logic and distribution of connection lengths. Feuer, Michael,T-CJan 82 29-33

Stochastic processes; cf. Markov processesStorage; cf. MemoriesStore-and-forward switching; cf. Message switchingSupersystems; cf. Distributed computing; Parallel processing

Switching circuits; cf. Semiconductor logic circuitsSwitching functions; cf. Logic functionsSwitching systems; cf. Interconnection networksSystem reliability; cf. Computer reliability; Computer software reliability;

Fault tolerance

T

Terrain mappingentity-oriented relational database system for spatial information;

application to watershed data. Vaidya, Prashant D., + , T-C Oct 821025-1031

Testing; cf. Computer software testing; Computer testing; Digital systemtesting

Text processinghardware-based hashing scheme in design of multiterm string comparator

for text retrieval. Burkowski, Forbes J, T-CSep 82 825-834Time synchronization; cf. SynchronizationTomography, X-ray

supersystem technology and architecture. Swartzlander, EarlE., Jr., +T-CMay 82 399-409

Transformsgeneral-purpose high-speed logical transform image processor. Herron, J.M, + , T-CAug 82 795-800

two-dimensional discrete cosine transform; fast algorithms. Kamangar, F.A., + , T-CSep 82 899-906

Transforms; cf. Haar transformsTransient analysis; cf. Electromagnetic transient analysisTrees

error correction in robust data structures. Taylor, DavidJ, + , T-CJul82602-608

image region-labeling and clustering problems; parallel solution usingcontent-addressable read/write memories suitable for VLSIimplementation. Snyder, WesleyE., + , T-COct 82 963-968


point enclosure problem; solution in plane using S-tree static datastructure. Vaishnavi, ViayK., T-CJan 8222-29

Trees; cf. Hierarchical systemsTruncation errors; cf. Finite wordlength effects

V

Vehicle control; cf. Aircraft controlVLSI (very large-scale integration); cf. Integrated circuits

w

Water resourcesentity-oriented relational database system for spatial information;

application to watershed data Vaidya, Prashant D., +, T-C Oct 821025-1031

Wiring; cf. Integrated-circuit metallization; Layout

X

X-ray imaging; cf. Tomography, X-ray

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1982 Index IEEE Transactions on Computers Vol. C-31 · 1982 Index IEEE Transactions on Computers...

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Transcript of 1982 Index IEEE Transactions on Computers Vol. C-31 · 1982 Index IEEE Transactions on Computers...