15205-Piu Common Utrm b
description
Transcript of 15205-Piu Common Utrm b
/ B
Rev DateRev.Document ID
2005-06-16B15205-891586
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BGAOS
Common Tests for Plug In Units for IFU
Next Generation
Table of ContentsConfidential
Document IDRev.Rev Date
15205-891586B2005-06-16
Common Tests for Plug In Units for IFU
Next Generation
CONFIDENTIAL
Rev DateRev.Document ID
2005-06-16B15205-891586
Common Tests for Plug In Units for IFU
Next Generation
CONFIDENTIAL
21.Introduction
1.1Purpose and scope21.2References21.3Terminology and abbreviations21.4Open issues32.unit description43.Test Station Description43.1Test Station overview43.2Test Jig53.2.1Test Board, PIUT53.2.2Mechanical enclosure for PIUT53.3Test Station Equipment53.3.1Nera Equipment53.3.2Instruments53.3.3JTAG Equipment63.3.4General Equipment63.3.5Cables63.4Test Station Software63.4.1First time Set-up of Test Station64.Operational Tests74.1Test overview74.2Initial Process Tests84.2.1Automatic Optical Inspection (AOI)84.2.2In-Circuit Testing (ICT) (Flying Probe Test (FPT) / Bed of Nails)84.3Power-On Tests84.3.1Current Limit Test84.4Boundary Scan Test94.4.1Infrastructure Test94.4.2Interconnect Test94.4.3Adapter Test94.5Functional Tests104.5.1Current Consumption104.5.2SBC Software download104.5.3SBC Address Detection104.5.4Front LED Test114.5.5Hot Swap Test (3.3v)114.5.6FPGA Software download114.5.7Inventory124.5.8Secondary Voltages12
Change Record
RevDatePages affectedChanges
A2005-03-09Initial issue
B2005-06-16All1,7,1212
3Confidential stamp added in header and footer.25MHz detection test removed.
Altered revision format and serial no format in table 4-2.
Reduced no. of open issues
1. Introduction
1.1 Purpose and scope
This Unit Test Requirement for Manufacturing describes the common tests for all the Plug-In Units (PIU) to the IFU.
The purpose of this document is to:
Define test requirements for the PIU.
Describe (in some detail) how the tests shall be performed.
Describe necessary equipment, instruments and software to perform the tests.
Be a reference and input for test development and documentation (Test Instructions/-Results, etc.).
1.2 References
Nera specifications
Ref. No. / Document codeTitle / description
[1] NGP\00106IFU-System Design Specification
[2] In e-Matrix, various objectsBoard schematics and drawings
[3] Test Board (PIUT) schematics and drawings\\Nera64\Next_Generation_Prod\Detail Design Phase\IFU\PIUT-PlugInUnitTest
[4] NG-IFU\BASIC\00053IFU Software Download
[5] NG-IFU\BASIC\00060Functional Test Station Description PIU
[6] NG-IFU\BASIC\00061PIUT Board and FPGA Design Specification
Table 11: References
1.3 Terminology and abbreviations
Abbreviations Descriptions
ADCAnalogue to Digital Converter
AOIAutomatic Optical Inspection
BGABall Grid Array
BISTBuilt-in Self Test (Test performed without instruments)
CMICodec Mark Invertion
CMOSComplementary Metal Oxide Semiconductor
DACDigital to Analogue Converter
DXCDigital Cross Connect
EMCElectro Magnetic Compatibility
FETField Effect Transistor
FPFrame Pulse
FPGAField Programming Gate Array
ICTIn-Circuit Testing
IEEEInstitute of Electrical and Electronics Engineers
IFIntermediate Frequency
IFUInterFace Unit
I/OInput/Output
JTAGJoint Test Action Group
LIULine Interface Unit
MDSMain Data Switch
MODEMMOdulatorDEModulator
MSOHMultiplex Section OverHead
NROPNera Radio Overhead Processor
OHC BusOverHead Connection Bus
PCBPrinted Circuit Board
PIUPlug In Unit
PIUTPlug In Unit Test (Test Board for Supervisory Unit)
PODConnection Box used with JTAG Boundary Scan controller
PSUPower Supply
QAMQuadrature Amplitude Modulation
RCVRReCeiVeR
RIURadio Interface Unit
RPSRadio Protection Switching
RSOHRegenerator Section OverHead
SBCSu Bus Controller
SDHSynchronous Digital Hierarchy
SOHSection OverHead
SUSupervisory Unit
TCKTest Clock
TDITest Data In
TDOTest Data Out
TMSTest Mode Select
TRSTTest Reset
UBNNera Networks PCB
UUTUnit Under Test
XCVRTransceiver
XPICCross Polar Interference Canceller
Table 12: Terminology and abbreviations
1.4 Open issues
Consider using fan for test of some PIU.
2. unit description
The PIU interfaces the motherboard with user interface or radio equipment.
3. Test Station Description
3.1 Test Station overview
Figure 31: Test Station overview shows a general setup of a test-jig for a Plug-In Unit. The various units might have minor changes to this setup. The boundary scan part of the test might be performed on a separate test station. In such a station, the Ethernet and RS232 communication is not needed.
Figure 31: Test Station overview3.2 Test Jig
The UUT will be placed in a Test Jig (Fixture) for the tests. The Test Jig will consist of a dedicated Test Board named Plug-In-Unit-Test (PIUT) and a mechanical enclosure.3.2.1 Test Board, PIUT
The Test Board (ET5157A) is normally referred to as the PIUT. The UUT connects to the PIUT via a 95-pin and in some cases an additional 55-pin connector. The PIUT has an FPGA that needs to be programmed if the units power has been off. The PIUT has several connectors for various test equipment; such as boundary scan and software download. See Figure 31. See also document [6] for details.The main connectors are:
-48DC In
D-Sub connector
TAP1 (10-pin)3M 10-Pin connector for accessing JTAG chain on UUT (PM3705 controller)
TAP1 (20-pin)3M 20-Pin connector for accessing JTAG chain on UUT (JT 3710/37x7 controller)
TAP2 (10-pin)3M 10-Pin connector for accessing JTAG chain on PIUT (PM3705 controller)
TAP2 (20-pin)3M 20-Pin connector for accessing JTAG chain on PIUT (JT 3710/37x7 controller)
Ethernet1
LAN Connector for communicating with UUT
Ethernet2
LAN Connector for communicating with PIUT
RS-232
For serial communication with UUT.
RS-232
For serial communication with PIUT
3.2.2 Mechanical enclosure for PIUT
It is intended to use a similar enclosure on the PIUT as for the IFU. The PIUT is designed with similar dimensions as the IFU Motherboard. UUT will be inserted into PIUT slot No. 3. Slot No. 1, 2, 4, and 5 will be closed by blind panels. The mechanical enclosure will have an open top for easy access to test connectors on the PIUT board.
3.3 Test Station Equipment
The following equipment is needed to do the common test for a PIU.
3.3.1 Nera Equipment
PIUT, ET5157A
PIUT frame including a vertical board
3.3.2 Instruments
48V Power Supply, GPIB Controllable.Ex. Agilent E3645A
GPIB Interface for PCEx. Agilent 82357A/USB
3.3.3 JTAG Equipment
Boundary Scan Controller.Ex. JT3727 (/ PCI or TSI) or JT3710 (/ PCI or USB)
Boundary Scan POD.Ex. JT2137/12 or JT2147
3.3.4 General Equipment
Test PC with Windows 2000 or newer and 2 LAN connections.
Ethernet Switch
Barcode reader
3.3.5 Cables
TP Cables (LAN cables)
GPIB Cable
RS-232 Cable
48V Cable
TAP Cables
3.4 Test Station Software
The following programs are needed to test and program the IFU PIU.
Test TypeProgram typeNameUsed for
Boundary scanJTAG test SW from JTAG Technologies BVPCA2176Production package
PM3790Boundary Scan Diagnostics
Functional testEthernet ServerBootp ServerSets up the TCP/IP connection
TCL platformActiveTCL (wish84.exe)Sending configuration commands to UUT.
TFTP serverTFTPD32Server for software download
TCL scriptxxx.tclVarious TCL script made specifically for the tests.
TclDriverUdpTclDriver.dllTCL driver with basic TCL commands.
LPC CodesbcFlash.hexProgramming the LPC.
FPGA codefpga.nffProgramming the FPGA.
Table 31: Programs needed during testing
3.4.1 First time Set-up of Test Station
Check document [5] for details on first time station setup.4. Operational Tests
This chapter shall define the performance parameters which are required to be tested in the manufacturing test, and specify parameter values with sufficient margins to guaranteed values.
The test software used for the operational tests should record test results with at least article code, serial number, test date, test point, and test results.
Boundary scan tests should work on the UUT regardless if the software is downloaded or not.
The UUT should be visually inspected before the tests are performed to eliminate obvious faults such as heat sink not mounted correctly.
4.1 Test overview
Table 41 below shows an overview of the tests to be done. Further description of the tests is given in the chapters to follow.
Test no.Tests / operationsPurpose / Comments
Initial Process Tests
1Automatic Optical Inspection (AOI)Automatic Optical Inspection
2In-Circuit Testing (ICT)In Circuit Test
Power-On-Test
3Current Limit TestEnsure there are no short circuits
Boundary Scan Tests
4Infrastructure TestTo verify the JTAG chain is operational
5Interconnect TestTo verify all nets between Boundary Scan Circuits
6Adapter TestTo verify the J1 connection to the PIUT board
Functional Tests
7Current ConsumptionCheck that the current consumption is within requirements.
8SBC Software downloadDownload SBC software to the UUT.
9SBC Address DetectionCheck the SBC and address bus connectors.
10Front LED TestVerify that front LED is working
11Hot Swap Test (3.3v)Verify hot swap functionality
12FPGA Software downloadDownload FPGA software to the UUT.
Inventory
Set inventory data.
14Secondary Voltages Checks the secondary voltages.
Table 41: Test Overview4.2 Initial Process Tests
These tests are performed before the UUT is inserted in the Test Station.
4.2.1 Automatic Optical Inspection (AOI)
Tests that correct components are mounted and that they have correct orientation.
4.2.2 In-Circuit Testing (ICT) (Flying Probe Test (FPT) / Bed of Nails)Perform an ICT to at least test components not covered by boundary scan or functional tests.The power circuits should be included in the test.
4.3 Power-On Tests
4.3.1 Current Limit Test
The purpose of this test is to verify that there are no major shot circuits either in the -48V supply or secondary voltages. This should be checked before doing any boundary scan or functional tests.
Set the current limit to X mA on the power supply, where X depends on the PIU.
Check current consumption does not exceed 90% of the current limit.
If excessive current consumption:
Turn off power immediately.
Measure the resistance between GND and power circuits using a multimeter
Inspect board carefully for short circuits and components mounted incorrectly.
If this test is performed using a GPIB controlled power supply, test no 4.5.1 (Current Consumption) can be done at this point in stead of later.
4.4 Boundary Scan Test
1. Perform infrastructure test to verify the JTAG chain is operational.
2. Perform interconnect test to verify all nets between Boundary Scan Circuits.
3. Perform adapter test to verify the J1 connection to the PIUT board.
At the moment the SBC is not a Boundary Scan circuit even though its in the TDI-TDO chain.
The IC is therefore bypassed with a special BSDL-file.
4.4.1 Infrastructure Test
Test the JTAG chain, TDI-TDO. This verifies that the JTAG chain is operational.
The netlist is found in eMatrix.
4.4.2 Interconnect Test
Test signals between Boundary Scan circuits and input/output signals.
Test Pull-up and Pull-down nets.
This requires that PWR and GND nets must be defined in the .NIF file
(The main purpose of the .NIF file is to disable drivers which otherwise can cause bus conflicts.)
Handle all attentions in the .ECN-file.
4.4.3 Adapter Test
Test signals between Boundary Scan circuits on the UUT and Boundary Scan circuits on the Test Jig.
Define an adapter file (.ADP-file).
4.5 Functional Tests
The following describes functional tests to be performed on each produced UUT. Some of the tests can be performed in any order, but we suggest using the same order as the chapters in this document. To minimize the test time, simultaneous testing of several test points should be used if possible.
Set up the test station as shown in Figure 31.
4.5.1 Current Consumption
The purpose of this test is to check that the current consumption is within the requirements.
Set the current limit to Y mA on the power supply, where Y depends on the PIU.
Requirements: X mA where X depends on the PIU.
If excessive current consumption:
Turn off power immediately.
Measure the resistance between GND and power circuits using a multimeter.
Inspect board carefully for short circuits and components mounted incorrectly.
4.5.2 SBC Software download
The SBC controls, among others, the FTP communication and needs software before any other test can be performed.
Procedure:
1. Download software to the SBC. See download document [4] for details.
2. Set slot address and unit address
3. Reset the UUT
4. Verify that the UUT has SBC downloaded4.5.3 SBC Address Detection
The purpose of this test is to check that the SBC and connections are correct. This is verified by checking that the SBC detects the correct addresses. This test assumes that the SBC software and FPGA code are already downloaded to the PIUT and SBC software is downloaded to the UUT. The test can be performed automatically by running a TCL script.
The script should do the following:
1. Verify that the UUT reads the address sat in the PIUT.
2. Alter the slot address in PIUT to 110.1110 (6.14) and verify that the address is detected in the UUT.
3. Alter the slot address in PIUT to 001.0001 (1.1) and verify that the address is detected in the UUT.
4. Return 0 if the test succeeds, and an error code if the test fails.
Check the return value from the TCL script to determine pass/fail status of the test.
4.5.4 Front LED Test
The purpose of this test is to verify that the front LED is working. The LED is controlled from the SBC.
The LED can be set in different modes:
Green LED ON indicates no alarms on unit.
Red LED ON indicates critical alarms on unit.
Set the green LED to ON and verify by visual inspection that the green LED is green.
Set the red LED on and verify by visual inspection that the red LED is red.
Since this test requires interaction with the test engineer, the test should be put towards the beginning (after SBC download) or end of the test sequence for the UUT.
4.5.5 Hot Swap Test (3.3v)
This test is used for verifying that the Hot Swap controller is working and the connection between PIUT and UUT.
The Hot swap signal (HSWAP) is controlled from the PIUTs FPGA1 (IC300, pin 99) and can be strapped with a jumper (P306) to 3.3 volt to set the signal high. (This strap is used in boundary scan test.) The signal goes trough PIUTs connector J1 on pin no. 10C to the UUT. On the UUT the signal goes to the Hot Swap controller to enable/disable the 3.3 volt to pass trough.
This test assumes that the SBC software and FPGA code are already downloaded to the PIUT and SBC software is downloaded to the UUT.
This test can be done automatically by running a TCL script. The scrip should do the following:
1. Set the Hot Swap signal low from the PIUT and verify that UUT powers down.
2. Set the Hot Swap signal high from the PIUT and verify that UUT powers up.
3. Return 0 if the test succeeds, and an error code if the test fails.
The script should read the SBC software version to check if the UUT is running.4.5.6 FPGA Software download
The FPGA needs to be downloaded every time you cold-boot the UUT.
1. Download the configuration file to the FPGA as described in [4]. 2. Verify that the FPGA code is downloaded by writing and reading to the FPGA register.
If the download is OK, the test-LED should be blinking aprox. 1-2 HzIf the download fails, the LEDs will not blink. In that case check that the 25MHz and 10MHz oscillator from PIUT is correct.
4.5.7 Inventory
Set the inventory data according to Table 42. Check that the inventory is stored correctly.
Data to be setValueExample
Product code[Product code]FDM5559A
Revision[Current revision]R1A
Serial number[Current serial number]80130015
Manufacturing date[Current date in format yyyy-mm-dd]2005-05-25
Table 42: Inventory
4.5.8 Secondary Voltages
The SBC contains an A/D converter for measuring analogue values. This is used to verify key voltages on the UUT. The secondary voltages might be measuring different voltages depending on the UUT. Requirements for each unit is stated in their respectively UTRM document.Check that the secondary voltages are within spec according to UUT specific UTRM document.
PIU
PIUT
ET5157A
Windows XP/2000 PC
Two LAN + GPIB
48V Power Supply
Controllable
Agilent E3645A
Boundary Scan
Controller
JT3727/PCI
JT3710/USB
JT3727/USB
JTAG POD
JT2137/12
TAP1 (UUT)
TAP2 (PIUT)
JTAG Cable
Switch
RS232
Ethernet 1
J1
95-Pin
J2
55-Pin
J1
95-Pin
+ 3.3V (4)
48V Valid
Ref_CLK
SYNC(3)
OHC bus (4)
Main Data Bus#1 (10)
Serial Diag. (2)
RESET#
JTAG (6)
SU Bus
10/100 Ethernet A (4)
IFU address (3)
SLOT address (4)
HSWAP
SU Bus
1G Ethernet (4) NC
SU Bus
10/100 Ethernet B (4) NC
Ethernet 2
GPIB
Office
LAN
GND (22)
2-Pin D-Sub
48V Connector
3M
10-Pin
3M
20-Pin
3M
10-Pin
3M
20-Pin
9-Pin D-Sub
DIAG-RS232-
PIU (UUT)
Ethernet
PIU (UUT)
Ethernet
PIUT
P4
P1
P2
P7
P8
P5B
P5A
9-Pin D-Sub
DIAG-RS232-
PIUT
P6
P11
3M
20-Pin
Debug PIUT
P9
3M
20-Pin
Debug UUT
P3
Test Jig ET5157A
USB-PIU
Type B
P10
USB-PIU
Type A
P12
UUT
Barcode reader
-48V
On PIUT releases until M1A you have to remove the jumper from P306 (or set the jumper to 2-4) before running the script.
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