14.ECE 301 - Synthesizable HDL
Transcript of 14.ECE 301 - Synthesizable HDL
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VITU N I V E R S I T Y
ECE 301 - VLSI System Design(Fall 2011)
Verilog HDL
Prof.S.Sivanantham
VIT UniversityVellore, Tamilnadu. India
E-mail: [email protected]
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After completing this lecture, you will be able to:
Understand issues of language translation Describe the considerations of clock signals
escr e e cons era ons o rese s gna s
Describe the partition issues for synthesis
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Synthesis tools at least perform the following critical tasks:
Detect and eliminate redundant logic Detect combinational feedback loops
xp o on -care con ons
Detect unused states
Make state assignments
S nthesize o timal multilevel lo ic sub ect to constraints.
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Think hardware.
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Language structure translation
Synthesizable operators Synthesizable constructs
ass gnmen s a emen
if .. else statement
case statement loop structures
always statement
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Arithmetic Bitwise Reduction Relational
+: add
- : subtract
* : multiply
/ : divide
% : modulus
~ : NOT
&: AND
| : OR
^: XOR
~ , ^~: XNOR
&: AND
|: OR
~&: NAND
~|: NOR
^: XOR
>= : greater than or equal
: greater than
: right shift
==: equa ty
!=: inequality
&&: AND
|| : OR
! : NOT
caseequality===: equality
!==: inequality
Miscellaneous
{ , }: concatenation
{const_expr{ }}: replication>: arithmetic right shift: : con ona
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Features of if-else statement:
The if-else statement infers a priority-encoded, cascadedcombination of multiplexers.
,ifelse structure, otherwise, a latch will be inferred.
For sequential logic, we need not specify a completeif else structure, otherwise, we will get as a noticeremoving redundant expression from synthesis tools.
always @(enable or data)if (enable) y = data; //infer a latch
always @(posedge clk)if (enable) y
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Features of case statement:
A case statement infers a multiplexer. The consideration of using a complete or incomplete
statement.
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--- -
// creating a latch example._ _ , ,
input enable, data;output y;reg y;
lat
y
D QC ydataenable
t e o y o testing program.always @(enable or data)
if (enable) y = data; //due to lack of else part, synthesizer infer a latch for y.endmodule
Coding style: Avoid using any latches in your design.
ss gn ou pu s or a npu con ons o avo n erre a c es.For example:
always @(enable or data)
ECE301 VLSI System Design FALL 2011 S.Sivanantham
.if (enable) y = data;
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---
// Creating a latch examplemodule latch_infer_case(select, data, y);
input [1:0] select;input [2:0] data; e
d
[0]
[1][0]
select[1:0][1:0]
// The body of 3-to-1 MUXalways @(select or data)
case (select)
_ _
y_1
ed
ed y
[1]
[1]
[2]
DQ
Cy
data[2:0][2:0]
' : y = ata se ect ;2'b01: y = data[select];2'b10: y = data[select];
// The followin statement is used to avoidinferrin a latchun1_select_3
[0]
[1]
// default: y = 2'b11;endcase
endmodule
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---
a our p ase c oc examp e --- enerate ncorrect ar ware
module four_phase_clock_wrong(clk, phase_out);input clk;out ut re 3:0 hase out // hase out ut_// the body of the four phase clockalways @(posedge clk) begin
phase_out
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---
// a four phase clock example --- synthesizable version_ _ _ , _
input clk;output reg [3:0] phase_out; // phase output// the body of the four phase clocka ways (pose ge c )
case (phase_out)
4'b0000: phase_out
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// an example to illustrating the mixed usage of posedge/negedge signal.// The result cannotbe synthesized. Try it in your system !!
module DFF_bad (clk, reset, d, q);input clk, reset, d;
// the body of DFFalways @(posedge clkorreset)
beginreset q
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// an exam le to illustrate the mixed usa e of osed e/ne ed e si nal.// try it in your system !!module DFF_good (clk, reset_n, d, q);input clk, reset_n, d;ou pu reg q;// the body of DFFalways @(posedge clk ornegedge reset_n)begin
if (!reset_n) q
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// an N-bit adder using for loop.module nbit_adder_for( x, y, c_in, sum, c_out);parameter N = 4; e ine e au t size
input [N-1:0] x, y;input c_in;out ut re N-1:0 sumoutput reg c_out;reg co;
integer i;
[0]
[0]
[0]
[0]
[3]
sum[3:0]
spec y e unc on o an n- a er us ng or oop.always @(x or y or c_in)begin
co = c_in;for (i = 0; i < N; i = i + 1)
sum_1[1:0]
+un19_sum[1:0]
+un40_sum[1:0]
+un61_sum[1:0]
+
[0]
[1:0][0]
[1]
[1:0][1]
[1]
[2]
[1:0][2]
[1]
[1:0][3]
[1]
c_out[1]
c_in
y[3:0][3:0]
x[3:0][3:0]
{co, sum[i]} = x[i] + y[i] + co;c_out = co; end
endmodule
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---// a multiple cycle example --- This is an incorrect version.// Please try to correct it!
+[7:0]
[7:0]
[7:0]
data_b[7:0][7:0]
mo u e mu t p e_cyc e_examp e_a c , reset_n, ata_a, ata_ , tota ;
parameter N = 8;parameter M = 4;in ut clk, reset n;
un3_total[7:0]
total[7:0]
R
[3]
2
[7:0]Q[7:0]
[7:0]D[7:0]E
total[7:0][7:0]
reset_n
clk
_input [M-1:0] data_a;input [N-1:0] data_b;
output [N-1:0] total;
un1_data_a_1
[1]
[0]data_a[3:0]
[3:0]
-integer i;// what does the following statement do?always @(posedge clk or negedge reset_n)begin
Why the synthesizedresult is like this?
i (!reset_n) tota
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Random logic using flip-flops or latches
is independent of any software and type of ASIC.
is independent of easy to use but inefficient in terms of.
Register files in datapaths
use a s nthesis directive or hand instantiation.
RAM standard components
are supplied by an ASIC vendor.
depend on the technology. RAM compilers
A flip-flop may take up 10 to 20times the area of a 6-transistorstatic RAM cell.
ECE301 VLSI System Design FALL 2011 S.Sivanantham
are the most area-efficient approach.
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Goals of coding guidelines:
Testability
Performance
mp ca on o s a c m ng ana ys s
Gate-level behavior that matches that of the original RTLcodes.
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Using single global clockvo ng us ng gate c oc s
Avoiding mixed use of both positive and negative edge-tri ered fli -flo s
Avoiding using internally generated clock signals
D Q D Q: Combinational logic
Top module(a) An ideal clock scheme
clk
Module A Module B
Clockgenerator
Module B
clk_A
clk_Bclk
clk_n clk
D Q
CK
D Q
CKModule A Module B
ECE301 VLSI System Design FALL 2011 S.Sivanantham
(b) An example of using both positive and negative edge-triggered flip-flops
(c) Using a separate clock moduleat the top level.
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The basic design issues of resets are:
sync ronous or sync ronous
An internal or external power-on reset? More than one reset, hard vs. soft reset?
The basic writing styles for both asynchronous and synchronous reset areas follows:
always @(posedge clkorposedge reset)
if (reset) ..
else ..
always @(posedge clk)
if (reset) ..
else ..
The only logic function for the reset signal should be a direct clear of all
Asynchronous reset Synchronous reset
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p- ops.
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Asynchronous reset
.
since reset is a special signal like clock, it requires a tree of buffers to beinserted at place and route.
does not re uire a free-runnin clock.
does not affect flip flop data timing.
makes static timing analysis (or cycle-based simulation) moredifficult.
makes the automatic insertion of test structure more difficult.
Synchronous reset
is eas to im lement.
It is just another synchronous signal to the input. requires a free-running clock
in particular, at power-up, for reset to occur.
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Avoid internally generated conditional resets.
always @(posedge gate ornegedge reset_n or posedge timer_load_clear)if (!reset_n || timer_load_clear) timer_load
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Keep related logic within the same module.
D Q D QComb. logic Comb. logic Comb. logic
clk
A BCK CK Module BModule A
D Q D QComb. logic Comb. logic
b Good st le
clk
A+BCK CK Module A Module B
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Register all outputs.
D Q
CK
D Q
CK
Comb. logicComb. logic
clk
Module A Module B
.
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Synthesis tools tend to maintain the original hierarchy.
w
xD Q
(a) Resources in different
modules cannot be shared.clk
y
z CK
w
xD Q
w
y D Q
clk
z CK
clk
xz
CK
ECE301 VLSI System Design FALL 2011 S.Sivanantham
(b) Resources in the same module can be shared.