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TABLE I. Different types of SRAM cells used in this paper,VDD = V DDM =1.3V, = (W N2 /LN2)/(W N3 /LN3).

Type Inverter

Tr.s AccessTr.(s) V SSM

BL pre- charge

5TSDG HVT SVT 1.0 600mV 600mV Low-Power 6T HVT SVT 1.4 600mV V DD

Conv. 6T HVT SVT 1.4 0mV V DD

2 5TSDG DESIGN A conventional 6T cell in comparison with the 5TSDG is

demonstrated in Fig. 1 (a) and Fig. 1 (b) respectively. A blockdiagram of 5TSDG cell including the sub-column circuitry isdepicted in Fig. 1 (c). Standby and Ground control circuits arerequired one per every sub-column while V SSM control isshared in the entire memory array. TABLE I specifies someof the design parameters of 5TSDG, low-power 6T, as well asconventional 6T cells used in this paper for comparison. Anarea reduction of ~13% is predicted compared to aconventional 6T cell using standard 65nm design rules [1].

The portless 5T SRAM in [16] does not use a dedicatedread-write port transistor, but has an access transistor thatshorts Q and Qz nodes during read and write. V DDM nodes arereplaced by dual bit lines for I/O and power reduction. Adetailed comparison between 5TSDG and the portless 5TSRAM of [16] would be useful future work. The portlessdesign appears to need larger PMOS and access transistorsthan 5TSDG.

2.1 Standby ModeOne of the effective and proven methods to suppress

leakage power during standby in 6T SRAMs is to usedynamic sleep design while maintaining a sufficient Static

Noise Margin (SNM), which ultimately determines theintegrity of the stored data [4][6]. The most effective way touse this method is by raising the negative supply voltage ofthe memory cells, V SSM , as opposed to lowering the positiveone, V DDM , to minimize bit line and cell leakage power[1][4][12].

Considering this method in 5T SRAM, a prominentfeature of 5TSDG is that instead of using an external on-chippower supply to raise V SSM voltage above ground in standby,with existence of enough leakage sources especially sub-threshold and gate leakage currents in advanced technologies,the leaking memory array can be used as a power source tocollect these charges from Vg 1 and Vg 2 via M g1 and M g2causing a natural rise of V SSM to a desired biasing level usingVSSM control circuit for fine tuning [1]. After evaluating

performance, stability and power consumptions bysimulations, with various combinations of threshold voltages(V th) for each single transistor in 5TSDG, it is found that V thof the inverter pairs have the most significant impact on theleakage power while the access transistor, N 3 has the mostsignificant impact on performance and stability. Therefore,the two inverter pairs N 1-P1 and N 2-P2 are selected to havehigh threshold voltages (HVT) while the access transistor N 3 has a smaller V th, (in this case Standard V th, SVT). All celltransistors are selected to have equal sizes (W i=0.15 m,L i=0.06 m).

Using two carefully sized diode-connected transistors, M 1 and M 2, the voltage across the cell in standby can be biased toremain static for various temperatures and process corners(See also [14]). In this design, a minimum voltage across thecell, V min = V DDM -VSSM, of 0.7V is selected to yield sufficientstability [7], resulting in a simulated SNM between 181-222mV in all corners and temperatures at V DDM =1.3V [10]. A64Kbit memory array arranged in 64x16 blocks wassimulated in standby mode using BSIM v.4 and HSPICE atVDD=VDDM =1.3V. The large capacitance of V SSM consistingof mostly junction and wire capacitors and sufficientavailable leakage current are the key factors in stability ofVSSM during standby/write/read modes. In case of lack ofleakage especially due to HVT transistors, in some corners ortemperatures, M 1 is turned on more strongly to provide thecharges to V SSM . During read and write operations, V SSMremains within about 20 mV of the standby steady statevalue.

Another unique feature of 5TSDG that makes it differentfrom previous research work is that V SSM can also be used to

pre-charge the bit line, BL, in standby via M stby as shown inFig. 1 (c) so that 1) channel and gate leakage through N 3 isreduced and minimized by up to 90% especially when a 0 isstored, and 2) the cell maintains a reasonable Read Noise

Margin (RNM) when accessed close to the optimumachievable point and 3) To accelerate read/write operationexplained in the next sections.

TABLE II shows standby leakage current and worst caseRNM for various types of SRAM cells introduced in TABLEI. Fig. 2 compares the power consumption of 5TSDGincluding peripheral circuits with a low-power 6T design invarious process corners. Traditional 5T designs as in [8][9],where V SSM is held at V SS level, require lower V th for internalcell transistors in 65nm technology, such as N 1, and P 2 (Fig.1), to enable write 1 operation discussed in section 2.4.Thus, even though some leakage power is saved by cutting abit line and biasing the other to a lower voltage, the overallleakage is quite high, being about half of the conventional 6Tcell value in TABLE II.

TABLE II. Leakage current and RNM comparison indifferent SRAM types (not including peripheral circuits)

64 cells 5TSDG Low-Power 6T Conventional 6T Leakage (nA) 80.6 88.7 2020.0

RNM (mV) 172.3 123.2 123.2

Fig. 2 5TSDG vs. low-power 6T SRAM designs: (64KbSRAM array and peripheral circuits, FF corner on the left,120 , 50% 0s 50% 1s stored in the array, 1 1.3mW)

00.10.20.30.40.50.60.7

0.80.9

1

Proposed 5T Low-Power 6T

N o r m a l

i z e d

S t a n

d b y

P o w e r

FFFS

SF

TT

SS

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2.2 Read OperationThe read operation is similar to a 6T S

only one bit line is used. In 5TSDG, thcharged in standby by V SSM which is near tto maximize RNM in the worse case (FS).of this pre-charge method compared to [9]

require an additional power supply on chipconverter or a level shifter which will add topower consumption. A simple sense amplif5TSDG is shown in Fig. 3 (b). Although nit is attractive due to its simplicity and thatclock signal [13]. During read, rd signal incausing Vg 1 and Vg 2 to be pulled down toMg2rd , which will maximize RNM and readglobal bit line, Gbit, is the output of the senpre-charged to V SSM through M 8 in standdown to V SS by M 7 during a read 0. Theralways implied unless Gbit is pulled downshould have a sufficient noise margin ttrigger. This sense amplifier can be share

from two adjacent sub-columns. For instacolumn composed of two 64 cell sub-coamplifier is placed in between bit lines Bitand SelR signals should be selected byselect the appropriate bit line to read fromused to pre-charge the input of the inverterFor similar bit line capacitances, read speSRAMs is comparable.

Fig. 4 (a) shows simulation results of thea conventional 6T cell using a sense amplifi(a). In this simulation, WL pulse is artificialthat BL reaches about V DD /2 in read freasons. Gbit and Gbitz are the outputs of thand are pre-charged high using prez pulseoperation.

Fig. 4 (b) demonstrates the read opeusing a sense amplifier shown in Fig. 3memory array arranged in 64x16 bitneighboring cells sharing the same word li0 and a 1 on Q0 and Q1 nodes, and haBL0 and BL1 respectively. Gbit load in 5as that in Gbit and Gbitz in the 6T counterpGbit0 and Q1-Q1z-BL1-Gbit1 are related tstoring a 0 and 1 respectively and sharinline (WL).

A dynamic increase in Q0 node occur0 due to the current flow from the bit linthe word line is raised and as shown inDuring read 1 a drop of voltage in Q1 noa similar reason (Q min). Q max and Q min shread upset i.e. they should be less and morevoltage of the inverter pairs, respectively, tread into a write, especially in FS corner.the probability of read-upset in 5T cell,increase word-line rise time and make thereduce their capacitances [2]. The latterread speed by reducing bit line swing delay.

RAM except thatbit line is pre-

e optimum pointnother advantage

is that it does not

such as a DC-DCthe chip area andier circuit used int the fastest type,

it does not need aig. 1 (c) is raisedVSS by M g1rd andperformance. Thee amplifier and isby and is pulledfore, a read 1 is. Inverter M 5-M6

prevent a falseby two bit lines

ce, in a 128-celllumns, the senseL and BitR. SelL

row decoder to. M 3 and M 4 are

5-M 6 in standby.ed in 5T and 6T

read operation inr shown in Fig. 3

ly generated suchor power savinge sense amplifier,s before the read

ation of 5TSDG(b) in a 64Kbitblocks for two

ne, WL, storing aving two bit linesSDG is the same

art. Q0-Q0z-BL0- a cell in 5TSDG

g the same word-

while reading ato N 3 and N 2 as

Fig. 4 (b) (Q max).e is observed for

ould not cause athan the tripping

o avoid turning ao further reduce

it is possible toit lines shorter toay also improve

BL

M 1

M 3

M 4

M 2

V DD

SQ

V SS

M 5

selz

Gbit

M 6

M 8

V DDprez

(a)

(b)Fig. 3 Sense amplifier used in th

conventional 6T (a) and 5

(a)

(b)Fig. 4 (a) Read operation in a conRead operation in 5TSDG, (typic

selL

selR

M 3M 4

BitL

BitR

M 1

M 2

SQz

BLZ

e

Gbitz

M 7

M 9

prezV DD

read operation of theSDG cells (b).

entional 6T SRAM (b)l corner (TT), 120 ).

GbitM 5

M 6

M 7

M 8stby

V SSM

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TABLE III shows the trip voltage vs. Qmareading in different corners in 5TSDG. Tcompared with RNM measurements forcases in worst case corner FS, show the stRNM is measured with V SSM on the bit liThe best biasing value for V SSM maximizescorner.

TABLE III. 5TSDG: Trip point voltage v120 )

5T Cell Trip Voltage (mV) /Q maxFF FS SF TT

883/193 866/185 934/202 899/195T Cell Q min (V)

1.19 1.18 1.24 1.22

2.3 VSSM Stability in DynamicDuring standby mode of the 5TSDG cel

a power supply to raise V g1 and V g2 abcharge the bit-line. During read operation,driven to V SS to maximize RNM and the reother hand, after a read operation is complthe bit-line are driven back to V SSM sincewill be in standby again. This voltage swinthe bit-line affects voltage level of V SSM sinof these voltages takes charges away fromdrop by an amount of V i, where i consecutive read operations. In a case of reline will actually add charges to V SSM bmuch less than the effect of the ground lcharges after being driven low for a read.is highly capacitive with much higher capand V g2, and many memory cells in standbcharges to it. Therefore, V SSM changes very

operation especially when it has large capto large memory arrays), and even if it dohelp the read operation in terms of perfonoise margin (see Fig. 5). In addition,decrease beyond a steady-state value, andcomplete, it is pulled back towards its staan increase in memory cell leakage (see FFig. 8 shows how V SSM reaches a steadymany read operations for different SRAM1Mb, and 2Mb) in FF corner. This figurewhen larger number of memory cells arethe initial values of which are instadecays after each read, and the total desteady-state value, , will be smaller tharrays. After each read cycle, is reduc0V. At this point (steady state), the mesufficiently increased such that it can fullycharges between read cycles. V SSM voltagcycle ( i) can be described by equation 1.

1 .

where

C C C

and Qmin whileese results whenarious mismatchbility of 5TSDG.ne similar to [9].RNM for the FS

. Q max and Q min,

(mV)SS

5 905/196

1.24

odel, V SSM is used asve V SS and pre-

, V g1 and V g2 aread speed. On theted, V g1, V g2 andthe memory cellg of V g1, V g2 andce each re-charge

SSM causing it tois the index ofding a 1, the bitt that amount is

ines taking awayortunately, V SSM

acitance than V g1 y provide electriclittle during read

citance (attacheds, it will actuallyrmance and read

VSSM does notwhen reading isdby level due to

ig. 6 and Fig. 7).-state value afterrray sizes (64Kb,emonstrates that

attached to V SSM ,ntaneous voltageay to reach the

an that of smallerd until it reachesmory leakage isreplenish the loste after each read

. (1)

,

C ,

C C

C , C , C , and are the capthe bit-line respectively. It is assumbeen driven to 0V initially. voltages after a read 0 and a read

are the number of 0 and 1 bi(16 bits/word in the simulation rstandby, C includes thecolumn connections, and V SSM iread, a single sub-column with capremoved. is the averageover the i-th read cycle period, .reduced. Similarly, is thethe i-th read cycle. As the memor approaches to one sinceC (stby). Part of is causeoverlap between rd and stby signals

This effect on VSSM

occurs alsothe bit-lines are charged and diexplanatory purposes, read operatsevere, is selected to be demonstraper bit-line and number of bits perthis effect.

Fig. 5 RNM variations vs. bit-linvertical line) for various corner

Fig. 6 The response of VSSM wheleft floating in standby for 64Kb, 12

from left to right for 5T SRAM ar

0.15

0.17

0.19

0.21

0.23

0.25

0.27

0.42 0.46 0.5 0.54

R N M ( V )

Bit-line pre-charge vo

C C C ,

citances of V g1, V g2, anded that V g1 and V g2 havend are the bit-line

1 respectively. and

ts in a word respectivelysults of this paper). Incapacitance of all sub-

nterconnections. Duringcitance of C C isemory leakage current

t is increased as V SSM is voltage at the end of

array size is increased, approaches

by a small amount ofin Fig. 4 (b).

in write operation whencharged. However, for

ion, which is the mosted. The number of cellsword also contribute to

biasing (=V SSM , e.g.s in the 5TSDG cell

forced to 0 volts and8Kb, 256Kb, and 512Kbray (FF corner, 120 )

0.58 0.62

ltage (V)

SS

FS

TT

SF

FF

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Fig. 7 Effect of read operation on V SSM (bits/word, FF, 120 , 1.

Fig. 8 V SSM Saturation during repeated rea64Kb, 1Mb and 2Mb 5T SRAM arrays (6

120 )2.4 Write Operation

Since a 5T SRAM cell only has a singleither a 0 (W0) or a 1 (W1) into theusing the same bit-line. This is different frowhere there is technically no difference beW1, i.e. by selectively pulling down onedepending on the data status, a W0 operatone side of the cell and the feedback will restorage node to the complement value. Iperformed in a similar way. On the other haline is pulled high by global write signal,the word-line is selected, state toggle is

driven high by the write circuit in W1 anotherwise. Using conventional 6T transistorit is almost impossible to write a 1 in a 56T cell: 1) N 2 needs to be stronger than N 3 factor , typically between (1.2~1.5) to mai[4]. 2) P 1 and P 2 need to be weak enough,size for write-ability purposes. 3) The acceNMOS, which does not pull up strongly dnature. These constraints will oppose raisin5T memory cell for a W1 using a single bithis problem, [9] suggests using different (transistors such as, using a CR of ~0.4

64Kb array 16)

d operations forbits/word, FF,

e bit-line, writingcell is performed

the 6T structuretween a W0 or a

of the bit linesion is applied onover the opposite

5TSDG, W0 isd, in W1, the bit-

wr, so that wheninitiated. Gwr is

is driven to V SS ratios and sizing,cell because in ay cell ratio (CR)tain read stabilityusually minimumss transistor is anue to its physical

Q if applied in at line. To combat /L) sizes for the, weakening P 1,

strengthening P 2 and N 1 with the copposed to 5TSDG in this paper, d50% reduction of RNM when comcell and therefore is more suscfluctuations in more advanced technprocess variations.

On the other hand, to makedisconnecting Vg 2 from V SS and lettvoltage by using a capacitor while kwrite. This method will weaken N 2 bwill facilitate W1. However, thisadvantage of leakage power reductio

As illustrated in Fig. 1 and5TSDG, V SSM is connected to Vg 1,standby mode. In W0, Vg 2 stays cowhile Vg 1 floats near V SSM . In W1,through M g1w1 . M equ is turned on bywhen W1 and is at V SS otherwise. Tto limit Vg=Vg 2-Vg 1 as shown inthe disturbed cells in the same subM equ is chosen through simulation toprocess corners especially for fastThis disturbance can also be minimipulse period to its limit. In summarstronger current drive than N 2 sinceincreased by V SSM .

The threshold voltage of access trole in W1 performance. Simulastandby power varies less than 2%low V th (HVT, SVT, LVT) for N 3.performance, the V th of N 3 can be rRNM. In 5TSDG, V th of N 3 can bLVT to maintain a reasonable R

shown in TABLE IV (for W1 delayRNM can be further increasedcapacitance and/or increasing word-l

TABLE IV. RNM and W1 compariN3, at worst case RNM (F

5T Cell RNM (mV) / W1 Delay (

LVT (~230 mV) SVT(~440 mV)

144.1/96.8 172.3/116.4

Fig. 9 W1 operation of 5TSDG c(120 )

BL

WL

Qz

Q

W1 Delay

ost of noise margin. Asesign in [9] will cause aared to conventional 6Teptible to performancelogies, especially due to

1 possible, [8] suggestsing it float near a biasingeeping Vg 1 at V SS duringy lowering its V DS whichmethod does not take

n opportunities.

as discussed earlier, inVg 2 and the bit lines in

nnected to V SSM via Mg 2 g1 is pulled down to V SS

Gwr signal which is highe role of this transistor isig. 9 to improve SNM ofcolumn. The strength oflimit write disturb for allMOS corner cases [2].

ed by reducing the writey, in W1, N 1 will have aits V DS is maximized i.e.

ransistor, N 3, plays a keytion results reveal that

using high, standard orIn order to improve W1duced with some loss of

e between the HVT andM/W1 performance as

measurement see Fig. 9).by reducing bit-lineine rise time [2].

son for different V th forcorner, 120 )

s) for Various N3 V th

HVT(~600 mV)

225.1/170.6

ll in slow corner (SS)

Vg 1

Vg 2

5T SS

Vg

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Therefore, to improve read stability(particularly W1), the solution is to findpoint considering the fact that N 3 does notstandby power consumption. Limited to thrselection, SVT for N 3 is reasonable as shoHowever, in chip foundries, even asomewhere between LVT and SVT canchanging gate oxide thickness. Fig. 11 comperformance of 5TSDG with a low-pdescribed in TABLE I. For both cases, W1from when WL = 50%V DDM to when Q=8delay is measured similarly but when QVSS. This measurement is different from whTABLE IV (word-line to Q-Qz cross point)31% slower than a conventional 6T deimproved by reducing V th of N 3. W0 perfoto conventional 6T cell.

Fig. 10 (a) shows how the voltage of V gSNM on disturbed cells while driving V g2 (at V SSM) mimicking that there is no

demonstrates the reverse scenario where Vand V g2 varies from 0V to V SSM. Similarly,that with no weak equalization betweendisturbed cells are susceptible to data cenvironmental disturbances. The strengtdetermine the limitation on this disturbanceVg2 from V SSM and not allowing V g1 to bmuch. In 5TSDG, M equ was ratioed sudisturbed SNM was greater than ~50mV.

Fig. 10 SNM in W1 disturb cells vs. V g1 a(120 )

Fig. 11 W1 (left) and W0 (right) delaydifferent corners between 5TSDG and lo

(120 )

0

50

100

150

200

250

300

350

Propoed 5T Low-Power 6T

W r i

t e ' 1 ' D e l a y

( p s )

FF

FS

SF

TT

SS 0

10

20

30

40

50

60

Propos

W r i

t e ' 0 ' D e l a y

( p s )

and write-abilityreasonable mid-

play a key role ine choices for V th n in TABLE IV.lower thresholdbe achieved byares W0 and W1wer 6T SRAMelay is measured%V DDM , and W020%V DDM above

at was reported in. W1 can be ~11-

sign and can bermance is similar

1 in W1can affectat a fixed voltage

equ. Fig. 10 (b)

g1 is fixed at 0V,this figure showsVg1 and V g2, theorruption due toh of M equ willby both loweringpulled down so

ch that the W1

nd V g2 voltages

omparison in-power 6T cell

The write margin of the proposbe divided into W0 margin (W0M),since as opposed to the 6T cell coundifferent WMs. One of the commonin conventional 6T SRAMs is byBL voltage able to flip the cell stateis defined to be the difference betvoltage, V DDM , and the minimum B1 into the cell while W0M is defiBL voltage able to write a 0 into(V DDM =1.3V), for a typical-typical~0.5V, and W0M is ~0.4V.

3 DYNAMIC POWER C ONDynamic power consumption o

into read and write power. Power coa function of Vmin, which determDuring several consecutive reads,driven to V SS and V SSM freconsumption is changed as supplythe square law dependency. This pothe frequency of V SSM swing durinthe dynamic power consumed due tground lines of 5TSDG, where ,and V g2 capacitances, is V SSM-Vof voltage swing.

Reading a 0 (R0) consumes m1 (R1) since in R0, the bit-line istrigger the sense amplifier, and the gamplifier is also pulled down. In R1to be pulled high enough to avamplifier, and the global bit-line sta

read power and standby power for vkeeping Vmin=V DDM -VSSM constantblock of 5TSDG. As V DDM is increaccordingly causing in equationoperation. Therefore, read power iwith higher V DDM .

Fig. 12 Comparison of normalizedvs. V DDM for 5TSDG cell, 64x16 bi

continuously from 16-bit word

d 5T Low-Power 6T

FF

FS

SF

TT

SS

0.00

0.20

0.40

0.60

0.80

1.00

1 1.1 1.2

N o r m a l

i z e d

P o w e r

VDDM (V)

d 5T SRAM design canand W1 margin (W1M)erpart, W0 and W1 havemethods to measure WM

easuring the maximum[15]. For 5TSDG, W1Meen the positive supplyvoltage able to write a

ned to be the maximumthe cell. In the 5TSDGcorner (TT), W1M is

UMPTION 5TSDG can be divided

nsumption during read isines V SSM biasing level.g1 and V g2 in Fig. 1 areuently. Active poweroltage is changed due tower is also dependent on

read. Equation 2 showsthe voltage swing of the

is the summation of V g1 S and is the frequency

(2)

re power than reading aulled sufficiently low to

lobal bit-line of the sense, bit-line is only requiredid activating the senses at V SSM . Fig. 12 shows

rious V DDM values whileat 0.7V for a 64x16 bitsed, V SSM also increases2 to increase during read

increased quadratically

read and standby powert block, reading 16 0s(FF corner, 120 )

1.3

Read

Standby

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Fig. 13 demonstrates case study results of worst-case (FF,120 ) normalized power consumption in standby mode,read, and write operations of 5TSDG in comparison withlow-power 6T design. Other corners have similar resultscomparable to Fig. 2. Read power consists of standby powerof the idle memory cells, and the dynamic power describedby equation 2. In this case study where a 64Kbit arrayconsisting of 64x16 bit blocks was studied (readingcontinuously from a 16-bit word), 5TSDG could achieve upto ~30% power reduction in read mode compared to that ofthe low-power 6T structure. In this example, R1 consumes~7% less power in 5TSDG compared to a R0 as explainedearlier. Obviously, larger number of read operations willresult in a linearly higher power consumption difference incomparison with standby power due to larger values of inequation 2. Read operation of the low-power 6T and 5TSDGdesigns in this experiment were similar to Fig. 4(a) and Fig.4(b) respectively. In a pipelined smart memory, back-to-back reads from the same sub-block would consume lessdynamic power if V g1 and V g2 are held at V SS betweenconsecutive reads.

The 5TSDG write power can be divided into W0 and W1power, each consisting of idle cell standby power, plus thedynamic power. In Fig. 13, a 64Kbit array consisting of64x16 bit blocks was studied while writing into a 16-bitword. In this example, W0 consumes ~80% less power, andW1 consumes ~9% less power compared with a low-power6T structure in worst case scenario (FF corner, 120 ). SinceR0 and R1 use similar power, storing bits to favor W0 (i.e.cell inverted) may reduce total power.

Fig. 13 Case study results of the worst-case write powerconsumption in comparison with read and standby power for

5TSDG vs. low power 6T design (FF, 120 ), 1 33.8mW

4 C ONCLUSION In this paper, the operation of a new low-power and high

performance design for a 5T SRAM cell was addressed whichhas improvements in static and dynamic power consumption,stability margins and performance when compared toprevious designs in this area. The stability of the novelbiasing scheme in dynamic mode was analyzed. Thereduction in dynamic power consumption in comparison with

a low-power 6T counterpart was demonstrated. A significantarea saving is predicted compared to a conventional 6T cell.

5 R EFERENCES [1] Jarollahi, Hooman, Hobson, R.F., Power and AreaEfficient 5T-SRAM with Improved Performance in 65nmCMOS for Low-Power SoC, IEEE International MidwestSymposiom on Circuits and Systems, 2010, MWSCAS2010., Aug. 2010, In Press.[2] Hobson, R.F., "A 5T SRAM Cell with 4 PowerTerminals for Read/Write/Standby Assist," Proceedings ofthe 2009 Intl Conference on Computer Design, CDES 2009,pp.10-16, 13-16 Jul. 2009.[3] H.Qin, et al., "Standby supply voltage minimization fordeep sub-micron SRAM", Microelectronics Journal, vol 36,pp. 789-800, Mar. 2005.[4] Sui Huang, et al., "A novel SRAM structure for leakagepower suppression in 45nm technology," Communications,Circuits and Systems, 2008. ICCCAS 2008. InternationalConference on, pp.1070-1074, 25-27 May 2008.[5] Fu-Liang Yang, et al., "Electrical CharacteristicFluctuations in Sub-45nm CMOS Devices," CustomIntegrated Circuits Conference, 2006. CICC '06. IEEE,pp.691-694, 10-13 Sep. 2006.[6] Hamzaoglu, F., et al., "A 153Mb-SRAM Design withDynamic Stability Enhancement and Leakage Reduction in45nm High- Metal-Gate CMOS Technology," Solid-StateCircuits Conference, 2008. ISSCC 2008. Digest of TechnicalPapers. IEEE International, pp.376-621, 3-7 Feb. 2008.[7] Khellah, M., et al., "A 256-Kb Dual-VCC SRAMBuilding Block in 65-nm CMOS Process With ActivelyClamped Sleep Transistor, " Solid-State Circuits, IEEEJournal of, vol.42, no.1, pp.233-242, Jan. 2007.[8] Tran, H., "Demonstration of 5T SRAM and 6T dual-portRAM cell arrays, " VLSI Circuits, 1996. Digest of TechnicalPapers., 1996 Symposium on, pp.68-69, 13-15 Jun. 1996.[9] Carlson, I., et al., "A high density, low leakage, 5TSRAM for embedded caches," Solid-State CircuitsConference, 2004. ESSCIRC 2004. Proceeding of the 30thEuropean, pp. 215- 218, 21-23 Sep. 2004.[10] Seevinck, et al., "Static-noise margin analysis of MOSSRAM cells," Solid-State Circuits, IEEE Journal of , vol.22,no.5, pp. 748- 754, Oct. 1987.[11] Hook, T.B., et al., "Noise margin and leakage in ultra-low leakage SRAM cell design," Electron Devices, IEEETransactions on, vol.49, no.8, pp. 1499- 1501, Aug. 2002.[12] Romanovsky, S., et al., "Leakage reduction techniquesin a 0.13 um SRAM cell," VLSI Design, 2004. Proceedings.17th Intl Conference on, pp. 215- 221, 2004.[13] Hobson, R.F., "A New Single-Ended SRAM Cell WithWrite-Assist," Very Large Scale Integration (VLSI) Systems,IEEE Transactions on, vol.15, no.2, pp.173-181, Feb. 2007.[14] Lysinger, M., et al., "A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS," Quality Electronic

Design, 2008. ISQED 2008. 9th International Symposiumon, pp.23-29, 17-19 Mar. 2008.[15] Zheng Guo, et al., "Large-scale read/write marginmeasurement in 45nm CMOS SRAM arrays," VLSI Circuits,2008 IEEE Symposium on, pp.42-43, 18-20 June 2008.[16] Wieckowski, M., Patil, S., Margala, M.; , "PortlessSRAMA High-Performance Alternative to the 6TMethodology," Solid-State Circuits, IEEE Journal of, vol.42,no.11, pp.2600-2610, Nov. 2007.

0.00

0.20

0.40

0.60

0.80

1.00

1.20

Read '0' Read '1' Write '0' Write '1' Standby

N o r m a l

i z e d

P o w e r

Proposed 5T

Low-power 6T