12/13/2013

2 Input 1 Output Arbiter to achieve fair arbitration for two 4 bit data Transmission

EE 477 Final Project

JOYDEEP SAHA (USC ID: 6594466840 ) MOHAN RUDRAPPA (USC ID: 2787644374 )

1. PART I: State Diagram of 2-1 arbiter

Figure 1: State Diagram of 2-1 Arbiter

From the above State Diagram, the FSM helps us in designing the Next state logic and Output function

logic.

The state diagram suggests that the FSM is a two-state FSM. On the application of Reset, the FSM goes

to Sx state where the arbiter picks up the X input. On the positive rising edge of clock, the FSM goes to

pre-determined next state. Using the current state, the next state is calculated. We are using one-hot

method which uses two flip-flops for saving two states such that the current state is preserved to calculate

the next state.

2. PART II: Detailed explanation of design

1) Next State Logic (NSL) design

NSL uses the current state of the FSM to determine the next state of the FSM. Considering the current

state, the truth table for the above state diagram designed for the arbiter for determining next state is:

Figure 2: Next State Logic Block Diagram

Next State Logic

(NSL) Current Sx/ Sy

Y_Ready

X_Ready

Clk

Next Sx/ Sy

X_Ready Y_Ready Qi_Sx

(Previous State)

Qi_Sy

(Previous State)

Qd_Sx

(Next State)

Qd_Sy

(Next State)

0 0 0 1 0 1

0 0 1 0 1 0

0 1 X X 0 1

1 0 X X 1 0

1 1 0 1 1 0

1 1 1 0 0 1

Table 1 : NSL Truth Table

Based on above truth table we get following equations for next state:

Qd_Sx = (X_Ready ∙ Y_Ready ∙ Qi_Sx ) + ( X_Ready ∙ Y_Ready) + (X_Ready ∙ Y_Ready ∙ Qi_Sy)

Qd_Sy = (X_Ready ∙ Y_Ready ∙ Qi_Sy ) + ( X_Ready ∙ Y_Ready) + (X_Ready ∙ Y_Ready ∙ Qi_Sx)

Next State Sx Design:

Figure 3: Next State design for Sx State

The next state goes to Sx state in following cases:

The current state is Sx and X_Ready and Y_Ready both are 0.

The current state is Sx and X_Ready is 1 and Y_Ready is 0.

The current state is Sy and X_Ready is 1 and Y_Ready is 0.

The current state is Sy and both X_Ready and Y_Ready are 1.

Next State Sy Design:

Figure 4: Next State design for Sy State

The next state goes to Sy state in following cases:

The current state is Sy and X_Ready and Y_Ready both are 0.

The current state is Sy and X_Ready is 0 and Y_Ready is 1.

The current state is Sx and X_Ready is 0 and Y_Ready is 1.

The current state is Sx and both X_Ready and Y_Ready are 1.

2) Output Function Logic (OFL) design

Figure 5: Output Function Logic Block Diagram

Output Function Logic

(OFL) R_Stall

Y_Ready

X_Ready

Sx/ Sy

X_Stall

Y_Stall

R_Ready

Sel

There are overall 4 input control signals.

Reset: When Reset is asserted, the initial set will be set to Sx and the Reset signal is considered to

be active low signal. There is only one single reset which resets the entire system to initial state.

X_Rea dy : It is an asynchronous input which suggests that X Data is ready for input.

Y_Ready : It is an asynchronous input which suggests that Y Data is ready for input.

Sx/Sy: The next state calculated by NSL is given as input to OFL.

There are overall 4 output control signals.

X_Stall Design:

X_Stall is designed such that it is generated asynchronously in following conditions:

When R_Stall goes high, X_Stall goes high.

When X_Ready and Y_Ready are both 1 and the next state is Sx, then X_Stall is generated.

X_Stall = R_Stall + (X_Ready ∙ Y_Ready ∙ Qd_Sx)

Figure 6: X_Stall OFL design

Y_Stall Design:

Y_Stall is designed such that it is generated asynchronously in following conditions:

When R_Stall goes high, Y_Stall goes high.

When X_Ready and Y_Ready are both 1 and the next state is Sy, then Y_Stall is generated.

Y_Stall = R_Stall + (X_Ready ∙ Y_Ready ∙ Qd_Sy)

Figure 7: Y_Stall OFL design

R_Ready Design:

R_Ready is designed such that it is generated synchronously in following conditions:

When R_Stall is low and either X_Ready and Y_Ready is 1 it is generated after two clocks such

that it goes high when register R output is genereated for that clock.

Figure 8: R_Ready OFL design

Sel signal Design:

Sel signal is generated as per following truth table:

X_Ready Y_Ready Sx (next state) Sy(next state) Sel

0 0 0 1 1

0 0 1 0 0

0 1 X X 1

1 0 X X 0

1 1 0 1 1

1 1 1 0 0

Table 2 : Sel Truth Table

The above truth table can be simplified as Sx(Next state) and Sy(Next state) are generated from current

state and X_Ready and Y_Ready.

Sx(Next State) Sy(Next State) Sel

1 0 0

0 1 1

Table 3 : Sel Simplified Truth Table

Nsl output QSy is connected to Sel pin to generate the Sel Signal.

QSy Sel

Figure 9: Sel OFL design

3) DataPath Unit(DPU) Design:

Figure 10: DPU design

The registers are gated with Clk and R_Stall such that register values are not updated when R_Stall is

raised high.

3. PART III: Implementation of Design

For the logic to be implemented, we need two-input AND, two-input OR, three-input OR and three-input

AND. For this purpose, considering minimum area 2x1 MUX and 4x1 MUX using transmission gates is

designed which will be used for the logic of OR and AND. Then the NSL, OFL and DPU is designed.

1) Implementation of 2 i/p OR and AND:

Figure 11: Schematic of 2x1 MUX

Symbol realized for this 2x1 MUX is:

Figure 12: Symbol of 2x1 MUX

Layout of 2x1 MUX is:

Figure 13: Layout of 2x1 MUX

LVS Match of layout of 2x1 MUX:

Figure 14: LVS Match of Layout of 2x1 MUX

When in3 input signal is connected to ground, with inputs in1 and in2, it behaves as AND Gate.

in3 in2 in1 Out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

Table 4 : Truth Table of 2x1 MUX acting as AND Gate

When in1 input signal is connected to Vdd, with inputs in2 and in3, it behaves as AND Gate.

in1 in2 in1 Out

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Table 5 : Truth Table of 2x1 MUX acting as OR Gate

The output of simulation for OR output is:

Figure 15: Simulation output of 2x1 MUX as OR Gate

The output of simulation for AND output is:

Figure 16: Simulation output of 2x1 MUX as AND Gate

2) Implementation of 3 i /p AND:

Figure 17: Schematic of 4x1 MUX as 3 i/p AND Gate

This is achieved by connecting both the in3 input terminals of 2x1 MUX to ground. Then when both in3

and in2 is 1 then only in1 gets selected and it gives output 1 when all three are 1.

Symbol realized for this 4x1 MUX as 3-i/p AND Gate is:

Figure 18: Symbol of 4x1 MUX as 3 i/p AND Gate

Layout of above schematic is:

Figure 19: Layout of 4x1 MUX as 3 i/p AND Gate

LVS Match of the above layout is given as:

Figure 20: LVS Match of Layout of 4x1 MUX as 3 i/p AND Gate

Simulation output of the AND Gate is:

Figure 21: Simulation output of 4x1 MUX as 3 i/p AND Gate

3) Implementation of 3 i/p OR:

Figure 22: Schematic of 4x1 MUX as 3 i/p OR Gate

This is achieved by connecting both the in1 input terminals of 2x1 MUX to Vdd. Then when either of in1

or in2 or in3 pin inputs are 1 the output is 1.

Symbol realized for this 4x1 MUX as 3-i/p OR Gate is:

Figure 23: Symbol of 4x1 MUX as 3 i/p OR Gate

Layout of above schematic is:

Figure 24: Layout of 4x1 MUX as 3 i/p OR Gate

LVS Match of the above layout is given as:

Figure 25: LVS Match of Layout of 4x1 MUX as 3 i/p OR Gate

Simulation output of the OR Gate is:

Figure 26: Simulation output of 4x1 MUX as 3 i/p OR Gate

4) Implementation of NSL:

Figure 27: Schematic of NSL

The NSL is designed as per the explanation given in previous section.

Symbol realized for this NSL is:

Figure 28: Symbol of NSL

Layout of above schematic is:

Figure 29: Layout of NSL

NSL DRC check:

Figure 30: DRC Check of layout of NSL

The layout is checked for zero DRC error. LVS Match of the above layout is given as:

Figure 31: LVS Match of Layout of NSL

Simulation output of the NSL Schematic is:

Figure 32: Simulation output of NSL Schematic with Reset

Figure 33: Simulation output of NSL schematic without Reset

Simulation output of the NSL Layout is:

Figure 34: Simulation output of NSL Layout without Reset

Figure 35: Simulation output of NSL Layout with Reset

5) Implementation of OFL:

Figure 36: Schematic of OFL

The OFL is designed as per the explanation given in previous section.

Symbol realized for this OFL including the NSL is:

Figure 37: Symbol of OFL

Layout of above schematic is:

Figure 38: Layout of OFL

OFL DRC check:

Figure 39: DRC Check of layout of OFL

The layout is checked for zero DRC error. LVS Match of the above layout is given as:

Figure 40: LVS Match of Layout of OFL

Simulation output of the OFL Schematic is:

Figure 41: Simulation output 1 of OFL Schematic

Figure 42: Simulation output 2 of OFL Schematic

Simulation output of the OFL Layout is:

Figure 43: Simulation output 1 of OFL Layout

Figure 44: Simulation output 2 of OFL Layout

4. PART IV: 2-1 Arbiter Final Design

Figure 45: Schematic of Arbiter

Here X, Y and R registers are gated with clock and R_Stall such that whenever R_Stall is high the

registers are not updated.

Layout of above schematic is:

Figure 46: Layout of arbiter

DRC check for layout of arbiter:

Figure 47: DRC Check of Layout of arbiter

The layout is checked for zero DRC error. LVS Match of the above layout is given as:

Figure 48: LVS Match of Layout of Arbiter

Simulation output (Register R outputs: Q[3:0]) of the Schematic of Arbiter is:

Figure 49: Simulation output 1 of Arbiter Schematic

Simulation output (X_Stall,Y_Stall, R_Ready and Sel) of the Schematic of Arbiter is:

Figure 50: Simulation output 2 of Arbiter Schematic

Simulation output (Register R outputs: Q[3:0]) of the Layout of Arbiter is:

Figure 51: Simulation output 1 of Arbiter Layout

Simulation output (X_Stall,Y_Stall, R_Ready and Sel) of the Schematic of Arbiter is:

Figure 52: Simulation output 2 of Arbiter Layout

The output summary is as follows:

The input sequence given is: Reset, X_Ready, Y_Ready, R_Stall, X[3:0], Y[3:0]. Here Reset is active low

signal. The output matches with the test output provided.

Input R[3:0]

(Here Q[3:0])

R_Ready X_Stall Y_Stall

0XXXXX 0 0 0 0

1000XX 0 0 0 0

1100AF 0 0 0 0

1100FA 0 0 0 0

1010XA A 1 0 0

1100FX F 1 0 0

1110FA A 1 1 0

1110FA F 1 0 1

1110FA A 1 1 0

1110FA F 1 0 1

1111BC A 1 1 1

1111XX A 1 1 1

1110DE F 1 1 0

1110DE D 1 0 1

1000XX E 1 0 0

1000XX D 1 0 0

1XX0XX 0 0 0 0

Table 6 : Output Summary

5. PART V: Performance and Area

From the layout above, the area is found to be 334.45 * 34.15 = 11421.47 µm2

The schematic is run for a clock of time period 2 ns.The datapath unit has a delay of 1 clock. There is

delay of two clocks in overall, for the final register output as input is provided after clock edge and for

proper latching of data to the register.