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February 2001 1 2001 Actel Corporation

Discont inued v3.0

Integrator Series FPGAs:1200XL and 3200DX FamiliesFeatures

High Capaci ty

2,500 to 30,000 Logic Gates Up to 3Kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 250 User-Programmable I/O Pins

High Performance

225 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode

Ease-of-Integra t ion

Synthesis-Friendly Architecture Supports ASIC DesignMethodologies.

95100% Device Utilization using AutomaticPlace-and-Route Tools.

Deterministic, User-Controllable Timing Via TimingDriven Software Tools with Up To 100% Pin Fixing.

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

General Descr ipt ion

Actels Integrator Series FPGAs are the first programmablelogic devices optimized for high-speed system logicintegration. Based on Actels proprietary antifusetechnology and 0.6-micron double metal CMOS processIntegrator Series devices offer a fine-grained, register-richarchitecture with embedded dual-port SRAM and wide-decode circuitry.

Integrator Series 3200DX and 1200XL families weredesigned to integrate system logic which is typically implemented in multiple CPLDs, PALs, and FPGAs. Thesedevices provide the features and performance required fortodays complex, high-speed digital logic systems. The3200DX family offers fast dual-port SRAM for implementinFIFOs, LIFOs, and temporary data storage. The largenumber of storage elements can efficiently addressapplications requiring wide datapath manipulation andtransformation functions such as telecommunications,networking, and DSP.

Integrator Ser ies Product Prof i le Family

1200XL 3200DX

Device A1225XL A1240XL A1280XL A3265DX A32100DX A32140DX A32200DX A32300DX

Capacity Logic Gates 1

SRAM Bits2,500N/A

4,000N/A

8,000N/A

6,500N/A

10,0002,048

14,000N/A

20,0002,560

30,0003,072

Logic Modules Sequential Combinatorial Decode

231220N/A

348336N/A

624608N/A

51047520

70066220

95491224

1,2301,184

24

1,8881,833

28

SRAM Modules(64x4 or 32x8) N/A N/A N/A N/A 8 N/A 10 12

Dedicated Flip-Flops 231 348 624 510 700 954 1,230 1,888

Clocks 2 2 2 2 6 2 6 6

User I/O (Maximum) 83 104 140 126 152 176 202 250

JTAG No No No No Yes Yes Yes Yes

Packages PL84

PQ100VQ100PG100

PL84 PQ100PQ144TQ176PG132

PL84PQ160 PQ208

TQ176PG176 CQ172

PL84PQ100PQ160TQ176

PL84PQ160PQ208TQ176CQ84

PL84PQ160PQ208TQ176CQ256

PQ208RQ208RQ240CQ208CQ256

RQ208RQ240CQ256

Note: Logic gate capacity does not include SRAM bits as logic.

v3.0

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In tegra tor Ser ies FPGAs: 1200XL and 3200DX Fami l ies

2 Discontinued v3.0

Order ing Informat ion

Application (Temperature Range)C = Commercial (0 to +70C)I = Industrial (40 to +85C)M = Military (55 to +125C)B = MIL-STD-883

Package TypeCQ = Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack RQ = Plastic Power Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack

Speed GradeBlank = Standard Speed

1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard 3 = Approximately 35% Faster than Standard F = Approximately 30% Slower than Standard

Part Number A1225 = 2500 Gates A1240 = 4000 Gates A3265 = 6500 Gates A1280 = 8000 Gates A32100 = 10000 Gates A32140 = 14000 Gates A32200 = 20000 Gates A32300 = 30000 Gates

Die RevisionXL = 1200XL FamilyDX = 3200DX Family

Package Lead Count

A1225 PQ 100 CXL

Operating VoltageV = 3.3 Volt

Blank = 5.0 Volt

V

Note: This family has been discontinued.

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Discontinued v3.0 3


Product Plan

Speed Grade* Application

F Std 1 2 3 C I M B

A1225XL Device

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

100-Pin Ceramic Pin Grid Array (CPGA)

A1225XLV Device


100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A1240XL Device





176-Pin Thin Plastic Quad Flat Pack (TQFP)

A1240XLV Device



A3265DX Device





A3265DXV Device



A1280XL Device



172-Pin Ceramic Quad Flat Pack (CQFP)




A1280XLV Device



A32100DX Device





Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: 1 = Approx. 15% faster than Standard

I = Industrial P = Planned 2 = Approx. 25% faster than Standard M = Military = Not Planned 3 = Approx. 35% faster than Standard

F = Approx. 40% slower than Standard Only Std, 1, 2 Speed Grade Only Std, 1 Speed Grade

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4 Discontinued v3.0


A32100DXV Device



A32140DX Device






A32140DXV Device



A32200DX Device


208-Pin Plastic Power Quad Flat Pack (RQFP)




A32200DXV Device



A32300DX Device




A32300DXV Device



Product Plan (Continued)

Speed Grade* Application

F Std 1 2 3 C I M B

Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: 1 = Approx. 15% faster than Standard

I = Industrial P = Planned 2 = Approx. 25% faster than Standard M = Military = Not Planned 3 = Approx. 35% faster than Standard

F = Approx. 40% slower than Standard Only Std, 1, 2 Speed Grade

Only Std, 1 Speed Grade

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Discontinued v3.0 5


Development Tool Suppor tThe devices are fully supported by Actels line of FPGA development tools, including the Actel DeskTOP series andDesigner Advantage tools. The Actel DeskTOP series is anintegrated design environment for PCs that includes designentry, simulation, synthesis, and place and route tools.Designer Advantage, Actels suite of FPGA developmentpoint tools for PCs and Workstations, includes the ACTgenMacro Builder, timing-driven place and route and analysistools, and device programming software.

In addition, the devices contain ActionProbe circuitry thatprovides built-in access to every node in a design, enabling100 percent real-time observation and analysis of a device'sinternal logic nodes without design iteration. The probecircuitry is accessed by Silicon Explorer II, an easy-to-useintegrated verification and logic analysis tool that cansample data at 100 MHz (asynchronous) or 66 MHz(synchronous). Silicon Explorer II attaches to a PCsstandard COM port, turning the PC into a fully functional

18-channel logic analyzer. Silicon Explorer II allowsdesigners to complete the design verification process attheir desks and reduces verification time from several hoursper cycle to only a few seconds.

Integrator Ser ies Archi tecturalOverview

The 1200XL and 3200DX architecture is composed ofine-grained building blocks which produce fast, efficientlogic designs. All devices within the Integrator Series arecomposed of logic modules, routing resources, clocknetworks, and I/O modules which are the building blocks todesign fast logic designs. In addition, a subset of devicescontain embedded dual-port SRAM and wide-decodemodules. The dual-port SRAM modules are optimized forhigh-speed datapath functions such as FIFOs, LIFOs, andscratchpad memory. The Integrator Series Product Profile Family on page 1 lists the specific logic resourcescontained within each device.

Plast ic Device Resources

User I/Os

Device PLCC 84-Pin VQFP 100-Pin PQFP100-Pin PQFP 144-Pin PQFP 160-Pin PQFP 208-PinRQFP

240-Pin TQFP 176-Pin

A1225XL 72 83 83

A1240XL 72 83 104 103

A3265DX 72 83 125 126

A1280XL 72 125 140 140

A32100DX 72 125 152 142

A32140DX 72 125 176 150

A32200DX 176* 202 A32300DX 176 202

Package Definitions (Consult your local Actel Sales Representative for product availability.)PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array, VQFP = Very Thin Quad FlatPack, RQFP = Plastic Power Quad Flat Pack

* Also available in RQFP 208-pin.

Hermet ic Device Resources

User I/Os

DeviceCPGA

176-PinCQFP84-Pin

CQFP172-Pin

CQFP208-Pin

CQFP256-Pin

A1280XL 140 140

A32100DX 60 A32140DX 176

A32200DX 176 202

A32300DX 212

Package Definitions (Consult your local Actel Sales Representative for product availability.)CPGA = Ceramic Pin Grid Array, CQFP = Ceramic Quad Flat Pack

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6 Discontinued v3.0

Logic Modules

3200DX and 1200XL devices contain three types of logicmodules: combinatorial (C-modules), sequential(S-modules), and decode (D-modules). 1200XL devicescontain only the C-module and S-module, while the 3200DX devices contain D-modules and dual-port SRAM modules inaddition to the S-module and C-module.

The C-module is shown in Figure 1 and implements thefollowing function:

Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11

where:

S0=A0*B0

S1=A1+B1

The S-module shown in Figure 2 is designed to implementhigh-speed sequential functions within a single logicmodule. The S-module implements the same combinatoriallogic function as the C-module while adding a sequentialelement. The sequential element can be configured as

either a D-type flip-flop or a transparent latch. To increaseflexibility, the S-module register can be bypassed so that itimplements purely combinatorial logic.

Figure 1 C-Module Implementation

D00

D01

D10

D11

S0

S1

Y

A0B0

A1

B1

Figure 2 S-Module Implementation

D11

D01

D00

D10Y OUT

S1

S0

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

D11

D01

D00

D10Y

S1S0

Up to 7-Input Function Plus Latch

Y

Up to 4-Input Function Plus Latch with Clear

D11

D01

D00

D10

Y OUT

S1

S0

Up to 8-Input Function (Same as C-Module)

SD1

D0

CLR

D Q

OUT

CLR

D Q

OUT

GATE

D Q

GATE

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Discontinued v3.0 7


3200DX devices contain a third type of logic module,D-modules, which are arranged around the periphery of thedevice. D-modules contain wide-decode circuitry whichprovides a fast, wide-input AND function similar to thatfound in product term architectures ( Figure 3). TheD-module allows 3200DX devices to perform wide-decodefunctions at speeds comparable CPLDs and PAL devices.The output of the D-module has a programmable inverterfor active HIGH or LOW assertion. The D-module output ishard-wired to an output pin or can be fed back into thearray to be incorporated into other logic.

Dual-Port SRAM Modules

Several 3200DX devices contain dual-port SRAM modulesthat have been optimized for synchronous or asynchronousapplications. The SRAM modules are arranged in 256-bitblocks which can be configured as 32x8 or 64x4 (refer toIntegrator Series Product Profile Family on page 1 for thenumber of SRAM blocks within a particular device). SRAM

modules can be cascaded together to form memory spacesof user-definable width and depth. A block diagram of the3200DX dual-port SRAM block is shown inFigure 4.

Figure 3 D-Module Implementation

7 Inputs

Hard-Wire to I/O

Feedback to Array

ProgrammableInverter

Figure 4 3200DX Dual-Port SRAM Block

SRAM Module32 x 8 or 64 x 4

(256 Bits)

ReadPort

Logic

WritePort

Logic

RD[7:0]

Routing Tracks

Latches

ReadLogic

[5:0] RDAD[5:0]

REN

RCLK

LatchesWD[7:0]

LatchesWRAD[5:0]

WriteLogic

MODE

BLKENWEN

WCLK

[5:0]

[7:0]

The 3200DX SRAM modules are true dual-port structurescontaining independent READ and WRITE ports. EachSRAM module contains six bits of read and write addressing(RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bitblocks. When configured in byte mode, the highest orderaddress bits (RDAD5 and WRAD5) are not used. The readand write ports of the SRAM block contain independentclocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The SRAMblock contains eight data inputs (WD[7:0]) and eightoutputs (RD[7:0]) which are connected to segmented vertical routing tracks.

The 3200DX dual-port SRAM blocks provide an optimsolution for high-speed buffered applications requiring fastFIFO and LIFO queues. Actels ACTgen Macro Buildeprovides the capability to quickly design memory functions,

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8 Discontinued v3.0

such as FIFOs, LIFOs, and RAM arrays. Additionally, unusedSRAM blocks can be used to implement registers for otherlogic within the design.

I /O Modules

The I/O modules provide the interface between the devicepins and the logic array. Figure 5 is a block diagram of the

I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module(refer to the Macro Library Guide for more information). I/Omodules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directionalpins (Figure 5).

Figure 5 I/O Module

G/CLK*

Q D

EN

PAD

* Can be Configured as a Latch or D Flip-Flop

From Array

To Array

(Using C-Module)

G/CLK*

Q D

The Integrator Series devices contain flexible I/O structures where each output pin has a dedicated output enablecontrol. The I/O module can be used to latch input and/oroutput data, providing a fast set-up time. In addition, the Actel Designer Series software tools can build a D-typeflip-flop using a C-module to register input and/or outputsignals.

Actels Designer Series development tools provide a designlibrary of I/O macrofunctions which can implement all I/Oconfigurations supported by the Integrator Series FPGAs.

Routing Struc ture

The Integrator Series architecture uses vertical andhorizontal routing tracks to interconnect the various logicand I/O modules. These routing tracks are metalinterconnects that may either be of continuous length orbroken into pieces called segments. Varying segmentlengths allows interconnection of over 90% of design tracksto occur with only two antifuse connections. Segments can

be joined together at the ends using antifuses to increasetheir lengths up to the full length of the track. Allinterconnects can be accomplished with a maximum of fourantifuses.

Horizontal Routing

Horizontal channels are located between the rows of modules and are composed of several routing tracks. Thehorizontal routing tracks within the channel are dividedinto one or more segments. The minimum horizontalsegment length is the width of a module pair, and themaximum horizontal segment length is the full length of thechannel. Any segment that spans more than one-third therow length is considered a long horizontal segment. A typical channel is shown in Figure 6. Non-dedicatedhorizontal routing tracks are used to route signal nets;dedicated routing tracks are used for the global clocknetworks and for power and ground tie-off tracks.

Vertical Routing

Another set of routing tracks run vertically through themodule. Vertical tracks are of three types: input, output, andlong, and are divided into one or more segments. Eachsegment in an input track is dedicated to the input of a particular module; each segment in an output track isdedicated to the output of a particular module. Longsegments are uncommitted and can be assigned duringrouting. Each output segment spans four channels (twoabove and two below), except near the top and bottom of thearray where edge effects occur. Long Vertical Tracks containeither one or two segments. An example of vertical routing

tracks and segments is shown in Figure 6.

Figure 6 Routing Structure

Vertical Routing Tracks

Antifuses

LogicSegmentedHorizontalRoutingTracks

Modules

Antifuse Struc ture

An antifuse is a normally open structure as opposed to thenormally closed fuse structure used in PROMs or PALs. Theuse of antifuses to implement a programmable logic deviceresults in highly-testable structures as well as efficient

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Discontinued v3.0 9


programming algorithms. The structure is highly testablebecause there are no pre-existing connections; therefore,temporary connections can be made using pass transistors.These temporary connections can isolate individualantifuses to be programmed and individual circuitstructures to be tested, which can be done before and afterprogramming. For example, all metal tracks can be testedfor continuity and shorts between adjacent tracks, and thefunctionality of all logic modules can be verified.

Clock Networks

Two low-skew, high-fanout clock distribution networks areprovided in each 3200DX device. These networks arereferred to as CLK0 and CLK1. Each network has a clockmodule (CLKMOD) that selects the source of the clocksignal and may be driven as follows:

1. Externally from the CLKA pad

2. Externally from the CLKB pad

3. Internally from the CLKINA input4. Internally from the CLKINB input

The clock modules are located in the top row of I/Omodules. Clock drivers and a dedicated horizontal clocktrack are located in each horizontal routing channel.

The user controls the clock module by selecting one of twoclock macros from the macro library. The macro CLKBUF isused to connect one of the two external clock pins to a clocknetwork, and the macro CLKINT is used to connect aninternally-generated clock signal to a clock network. Sinceboth clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. The clock input padsmay also be used as normal I/Os, bypassing the clocknetworks (see Figure 7).

Figure 7 Clock Networks

CLKB

CLKA

FromPads

ClockDrivers

CLKMOD

CLKINB

CLKINA

S0S1

InternalSignal

CLKO(17)

CLKO(16)

CLKO(15)

CLKO(2)

CLKO(1)

Clock Tracks

The 3200DX devices which contain SRAM modules (allexcept A3265DX and A32140DX) have four additionalregister control resources, called quadrant clock networks(Figure 8 on page 10). Each quadrant clock provides a local,high-fanout resource to the contiguous logic modules withinits quadrant of the device. Quadrant clock signals canoriginate from specific I/O pins or from the internal array and can be used as a secondary register clock, registerclear, or output enable.

Tes t Circui t ry All devices contain Actels ActionProbe test circuitry whichtest and debug a design once it is programmed into a device.Once a device has been programmed, the ActionProbe testcircuitry allows the designer to probe any internal nodeduring device operation to aid in debugging a design. Inaddition, 3200DX devices contain IEEE Standard 1149.1boundary scan test circuitry.

IEEE Standard 1149.1 Boundary Scan Testing (BST)

IEEE Standard 1149.1 defines a four-pin Test Access Port(TAP) interface for testing integrated circuits in a system.The 3200DX family provides five BST pins: Test Data I(TDI), Test Data Out (TDO), Test Clock (TCK), and TestMode Select Test Reset (TRST) (3200DX24A only). Deviceare configured in a test chain where BST data can be

transmitted serially between devices via TDO-to-TDIinterconnections. The TMS and TCK signals are sharedamong all devices in the test chain so that all componentsoperate in the same state.

The 3200DX family implements a subset of the IEEEStandard 1149.1 BST instruction in addition to a privateinstruction, which allows the use of Actels ActionProbefacility with BST. Refer to the IEEE Standard 1149.1specification for detailed information regarding BST.

Boundary Scan Circuitry

The 3200DX boundary scan circuitry consists of a Test

Access Port (TAP) controller, test instruction register, a JPROBE register, a bypass register, and a boundary scanregister. Figure 9 on page 10 shows a block diagram of the3200DX boundary scan circuitry.

When a device is operating in BST mode, four I/O pins areused for the TDI, TDO, TMS, and TCK signals. An activreset (nTRST) pin is not supported; however, the 3200DX device contain power-on circuitry that resets the boundary scan circuitry upon power-up. Table 1 on page 11summarizes the functions of the IEEE 1149.1 BST signals.

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Figure 8 Quadrant Clock Network

QuadClock

Module

QCLKA

QCLKB

*QCLK1IN

S0 S1

QCLK1

QuadClock

Module*QCLK2IN

S0 S1

QCLK2

QuadClock

Module

QCLKC

QCLKD

*QCLK3IN

S0S1

QCLK3

QuadClock

Module*QCLK4IN

S0S1

QCLK4

*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 9 3200DX IEEE 1149.1 Boundary Scan Circuitry

JPROBE Register

Boundary Scan Register

InstructionDecode

Control Logic

TAP Controller

InstructionRegister

BypassRegister

TMS

TCK

TDI

OutputMUX TDO

JTAG

JTAG


10 Discontinued v3.0

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Table 1 IEEE 1149.1 BST Signals

Signal Name Function

TDI Test Data InSerial data input for BST instructions anddata. Data is shifted in on the rising edgeof TCK.

TDO Test Data Out Serial data output for BST instructionsand test data.

TMS Test Mode Select Serial data input for BST mode. Data isshifted in on the rising edge of TCK.

TCK Test Clock Clock signal to shift the BST data intothe device.

Discontinued v3.0 11


JTAG

All 3200DX devices are IEEE 1149.1 (JTAG) compliant.3200DX devices offer superior diagnostic and testingcapabilities by providing JTAG and probing capabilites.These functions are controlled through the special JTAGpins in conjunction with the program fuse.

JTAG fuse programmed:

TCK must be terminatedlogical high or low doesntmatter (to avoid floating input)

TDI, TMS may float or at logical high (internal pull-up ispresent)

TDO may float or connect to TDI of another device (its anoutput)

JTAG fuse not programmed:

TCK, TDI, TDO, TMS are user I/O. If not used, they will beconfigured as tristated output.

BST Instructions

Boundary scan testing within the 3200DX devices iscontrolled by a Test Access Port (TAP) state machine. TheTAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers withinthe device. The TAP controller uses the TMS signal tocontrol the testing of the device. The BST mode isdetermined by the bitstream entered on the TMS pin.Table 2 describes the test instructions supported by the3200DX devices.

Reset

The TMS pin is equipped with an internal pull-up resistor.This allows the TAP controller to remain in or return to theTest-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMSmust be HIGH for at least five TCK cycles.

Table 2 BST Instructions

Test Mode Code Description

EXTEST 000

Allows the external circuitry andboard-level interconnections to be testedby forcing a test pattern at the output pinsand capturing test results at the inputpins.

SAMPLE/ PRELOAD 001

Allows a snapshot of the signals at thedevice pins to be captured and examinedduring device operation.

JPROBE 011 A private instruction allowing the user toconnect Actels Micro Probe registers tothe test chain.

USERINSTRUCTION 100

Allows the user to buildapplication-specific instructions such asRAM READ and RAM WRITE.

HIGH Z 101 Refer to t he IEEE Standard 1149.1specification.

CLAMP 110 Refer to t he IEEE Standard 1149.1specification.

BYPASS 111

Enables the bypass register between theTDI and TDO pins. The test data passesthrough the selected device to adjacentdevices in the test chain.

When a device is operating in BST mode, four I/O pins areused for the TDI, TDO, TMS, and TCLK signals. An activereset (nTRST) pin is not supported; however, the 3200DX contains power-on circuitry which automatically resets theBST circuitry upon power-up. The following tablesummarizes the functions of the BST signals.

JTAG BST Instructions

JTAG BST testing within the 3200DX devices is controlledby a Test Access Port (TAP) state machine. The TAPcontroller drives the three-bit instruction register, a bypassregister, and the boundary scan data registers within thedevice. The TAP controller uses the TMS signal to controlthe JTAG testing of the device. The JTAG test mode isdetermined by the bitstream entered on the TMS pin. Thetable in the next column describes the JTAG instructionssupported by the 3200DX.

Design Tool Support ActionProbe

If a device has been successfully programmed and thesecurity fuse has not been programmed, any internal logicor I/O module output can be observed in real time using the ActionProbe circuitry, the PRA and/or PRB pins, and ActelsSilicon Explorer diagnostic and debug tool kit.

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5.0V Operat ing Condi t ions

Absolute Maximum Rat ings 1

Free Air Tempera ture Range

Symbol Parameter Limits Units

VCC DC Supply Voltage 0.5 to +7.0 V

VI2 Input Voltage 0.5 to V CC +0.5 V

VO Output Voltage 0.5 to V CC +0.5 V

TSTG Storage Temperature 65 to +150 C

Notes: 1. Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greaterthan V CC + 0.5V or less than GND 0.5V, the internal protection diode will be forward biased and can draw excessive current.

Recommended Operat ing Condi t ions

Parameter Commercial Industrial Military Units

TemperatureRange 1 0 to +70 40 to +85 55 to +125 C

Power SupplyTolerance 5 10 10 %V CC

Note: 1. Ambient temperature (T A ) is used for commercial and industrial; case temperature (T C ) is used for military.

Elect r ical Speci f icat ions

Symbol Parameter

Commercial Commercial F Industrial MilitaryUnits

Min. Max. Min. Max. Min. Max. Min. Max.

VOH1 (IOH = 10 mA)

2.4 2.4 V

(IOH = 6 mA) 3.84 3.84 V

(IOH = 4 mA) 3.7 3.7 V

VOL1 (IOL = 10 mA)

0.5 0.5 V

(IOL = 6 mA) 0.33 0.33 0.40 0.40 V

VIL 0.3 0.8 0.3 0.8 0.3 0.8 0.3 0.8 V

VIH 2.0 V CC + 0.3 2.0 V CC + 0.3 2.0 V CC + 0.3 2.0 V CC + 0.3 V

Input Transition Time t R , tF 500 500 500 500 ns

C IO I/O Capacitance2 10 10 10 10 pF

Standby Current, I CC3 (typical = 1 mA) 2.0 20 10 20 mA

ICC(D) Dynamic V CC Supply Current See the Power Dissipation section on page 14.

IV Curve 4 Can be converted from IBIS model on the web.

Notes: 1. Only one output tested at a time. V CC = min.

2. Includes worst-case 176 CPGA package capacitance. V OUT = 0 V, f = 1 MHz. 3. All outputs unloaded. All inputs = V CC or GND, typical I CC = 1 mA. I CC limit includes I PP and I SV during normal operation. 4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

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3.3V Operat ing Condi t ions

Absolute Maximum Rat ings 1

Free Air Tempera ture Range

Symbol Parameter Limits Units

VCC DC Supply Voltage 0.5 to +7.0 V

VI2 Input Voltage 0.5 to V CC +0.5 V

VO Output Voltage 0.5 to V CC +0.5 V

TSTG Storage Temperature 65 to +150 C

Notes: 1. Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greaterthan V CC + 0.5V or less than GND 0.5V, the internal protection

diodes will forward bias and can draw excessive current.

Recommended Operat ing Condi t ions

Parameter Commercial Units

Temperature Range 1 0 to +70 C

Power Supply Tolerance 5 %V

Note: 1. Ambient temperature (T

A ) is used for commercial.

E lect r ical Speci f icat ions

ParameterCommercial

UnitsMin. Max.

VOH1

(IOH = 4 mA) 2.15 V

(IOH = 3.2 mA) 2.4 V

VOL1 (IOL = 6 mA) 0.4 V

VIL 0.3 0.8 V

VIH 2.0 V CC + 0.3 V

Input Transition Time t R, tF2 500 ns

C IO I/O Capacitance2, 3 10 pF

Standby Current, I CC4 (typical = 0.3 mA) 0.75 mA

ICC(D) Dynamic V CC Supply Current See the Power Dissipation section on page 14.

IV Curve 4 Can be converted from IBIS model on the web.

Notes: 1. Only one output tested at a time. V CC = min. 2. Includes worst-case 84-pin PLCC package capacitance. V OUT = 0 V, f = 1 MHz. 3. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = V CC or GND. 4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

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Package Thermal Character is t icsThe device junction to case thermal characteristic is jc,and the junction to ambient air characteristic is ja . Thethermal characteristics for ja are shown with two differentair flow rates.

Maximum junction temperature is 150C.

A sample calculation of the absolute maximum powerdissipation allowed for a PQFP 160-pin package with still airat commercial temperature is as follows:

Max. junction temp. (C) Max. commercial temp. ja (C/W)

----------------------------------------------------------------------------------------------------------------------------- 150C 70C34C/W--------------------------------- 2.4W = =

Package Type Pin Count

ja Maximum Power Dissipation

Still Air 300 ft/min Still Air 300 ft/min

Plastic Quad Flat Pack 100 42C/W 33C/W 1.9 W 2.4 W



Plastic Quad Flat Pack 208 25C/W 16.2C/W 3.2 W 4.9 W

Plastic Leaded Chip Carrier 84 37C/W 28C/W 2.2 W 2.9 W

Thin Quad Flat Pack 176 32C/W 25C/W 2.5 W 3.2 W

Power Quad Flat Pack 208 16.8C/W 11.4C/W 4.8 W 7.0 WPower Quad Flat Pack 240 16.1C/W 10.6C/W 5.0 W 7.5 W

Very Thin Quad Flat Pack 100 43C/W 35C/W 1.9 W 2.3 W

Power Dissipat ion

Genera l Power Equat ion

P = [I CCstandby + I CCactive] * V CC+ IOL* V OL* N+ IOH* (V CC V OH) * M

where:

ICCstandby is the current flowing when no inputs oroutputs are changing.

ICCactive is the current flowing due to CMOS switching.

IOL, IOHare TTL sink/source currents.

V OL, V OHare TTL level output voltages.

N equals the number of outputs driving TTL loads to V OL.

M equals the number of outputs driving TTL loads to V OH.

An accurate determination of N and M is problematicbecause their values depend on the family type, designdetails, and on the system I/O. The power can be dividedinto two components: static and active.

Sta t ic Power Component

Actel FPGAs have small static power components thatresult in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an evengreater reduction in board-level power dissipation canbe achieved.

The power dissipation due to standby current is typically a small component of the overall power. Standby power iscalculated below for commercial worst case conditions.

ICC V CC Power 2 mA 5.25 V 10.5 mW

The static power dissipation by TTL loads depends on thenumber of outputs driving HIGH or LOW and the DC load

current. Again, this number is typically small. For instance,a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW withall outputs driving LOW and 140 mW with all outputs drivingHIGH. The actual dissipation will average somewhere inbetween as I/Os switch states with time.

Active Power Component

Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component isfrequency-dependent, a function of the logic and theexternal I/O. Active power dissipation results from charginginternal chip capacitances of the interconnect,unprogrammed antifuses, module inputs, and module

outputs, plus external capacitance due to PC board tracesand load device inputs. An additional component of theactive power dissipation is the totem pole current in theCMOS transistor pairs. The net effect can be associated withan equivalent capacitance that can be combined withfrequency and voltage to represent active power dissipation.

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Equivalent Capaci tance

The power dissipated by a CMOS circuit can be expressed by Equation 1

Power (W) = CEQ * V CC2 * F (1)

where:C EQ is the equivalent capacitance expressed in picofarads(pF).V CC is power supply in volts (V).

F is the switching frequency in megahertz (MHz).

Equivalent capacitance is calculated by measuring I CCactiveat a specified frequency and voltage for each circuitcomponent of interest. Measurements have been made overa range of frequencies at a fixed value of V CC. Equivalentcapacitance is frequency-independent, so the results may be used over a wide range of operating conditions.Equivalent capacitance values are shown below.

C EQ Values for Acte l FPGAs

Modules (CEQM) 5.2Input Buffers (CEQI) 11.6

Output Buffers (CEQO) 23.8

Routed Array Clock Buffer Loads (CEQCR) 3.5

To calculate the active power dissipated from the completedesign, the switching frequency of each part of the logicmust be known. Equation 2 shows a piece-wise linearsummation over all components.

Power = V CC2 * [(m x CEQM* f m)Modules+

(n * CEQI * f n)Inputs + (p * ( CEQO+ CL) * f p)outputs +0.5 * (q

1* C

EQCR* f

q1)routed_Clk1

+ (r1

* f q1

)routed_Clk1

+0.5 * (q2 * CEQCR* f q2)routed_Clk2 + (r 2 * f q2)routed_Clk2 (2) where:

m = Number of logic modules switching at frequency f mn = Number of input buffers switching at frequency f np = Number of output buffers switching at frequency f pq1 = Number of clock loads on the first routed array

clockq2 = Number of clock loads on the second routed array

clockr1 = lFixed capacitance due to first routed array clock

r2 = Fixed capacitance due to second routed array clockCEQM = Equivalent capacitance of logic modules in pFCEQI = Equivalent capacitance of input buffers in pFCEQO = Equivalent capacitance of output buffers in pFCEQCR= Equivalent capacitance of routed array clock in pFCL = Output load capacitance in pf m = Average logic module switching rate in MHzf n = Average input buffer switching rate in MHz

f p = Average output buffer switching rate in MHzf q1 = Average first routed array clock rate in MHzf q2 = Average second routed array clock rate in MHz

Fixed Capaci tance Values for Acte l FPGAs(pF)

Table 5.

Device Typer1

routed_Clk1r2

routed_Clk2 A1225XL 106 106 A1240XL 134 134 A3265DX 158 158 A1280XL 168 168 A32100DX 178 178 A32140DX 190 190 A32200DX 230 230 A32300DX 285 285

Determining Average Switching Frequency

To determine the switching frequency for a design, the usermust have a detailed understanding of the data input valuesto the circuit. The following guidelines represent worst-casescenarios; they can be generally used to predict the upperlimits of power dissipation.

Logic Modules (m) = 80% of CombinatorialModules

Inputs Switching (n) = # of Inputs/4Outputs Switching (p) = # Outputs/4First Routed Array Clock Loads(q1)

= 40% of SequentialModules

Second Routed Array ClockLoads (q2)

= 40% of SequentialModules

Load Capacitance (CL) = 35 pF Average Logic Module SwitchingRate (f m)

= F/10

Average Input Switching Rate(f n)

= F/5

Average Output Switching Rate(f p) = F/10

Average First Routed Array Clock Rate (f q1)

= F

Average Second Routed Array Clock Rate (f q2)

= F/2

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1200XL Timing Model*

Output DelaysInternal DelaysInput Delays

tINH = 0.0 nstINSU = 0.3 ns

I/O Module

D Q

tINGL = 2.6 ns

tINYL = 1.3 ns tIRD2 = 3.2 ns

CombinatorialLogic Module

tPD = 2.6 ns

SequentialLogic Module

I/O Module

tRD1 = 0.8 nstDLH = 3.8 ns

I/O Module

ArrayClocks

FMAX = 225 MHz

Combin- atorialLogic

includedin tSUD

D Q D Q

tOUTH = 0.0 nstOUTSU = 0.3 ns

tGLH = 4.2 ns

tDLH = 3.8 ns

tENHZ = 5.4 nstRD1 = 0.8 ns

tCO = 2.6 nstSUD = 0.4 nstHD = 0.0 ns

tRD4 = 2.0 nstRD8 = 3.2 ns

PredictedRoutingDelays

tCKH = 5.7 ns

G

G

FO = 256

tRD2 = 1.3 ns

tLCO = 10.7 ns (64 loads, pad-pad)

Notes: 1. *Values shown for A1225XL-2 at worst-case commercial conditions. 2. Input Module Predicted Routing Delay

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3200DX Timing Model (Logic Funct ions using Array Clocks)*



I/O Module

D Q

tINGO = 2.8 ns

tINPY = 1.2 ns tIRD1 = 2.7 nsCombinatorial

Module

tPD = 2.1 ns


I/O Module


I/O Module

ArrayClocks

FMAX = 173 MHz

Combin- atorialLogicincludedin tSUD

D Q D Q

tLH = 0.0 nstLSU = 0.4 nstGHL= 6.5 ns

tDLH = 3.2 ns

tENHZ = 7.1 ns

tRD1 = 0.3 ns



G

G

DecodeModule

tPDD = 2.1 ns

tRDD = 0.4 ns

tRD2 = 0.7 nstRD4 = 1.2 ns

tCKH = 5.3 ns

*Values shown for A3265DX-2 at worst-case commercial conditions.

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3200DX Timing Model (Logic Funct ions using Quadrant Clocks)*



I/O Module

D Q

tINGO = 3.3 ns

tINPY = 1.4 ns tIRD1 = 1.9 nsCombinatorial

Module

tPD = 2.0 ns


I/O Module


I/O Module

QuadrantClocks

FMAX = 165 MHz

Combin- atorialLogicincludedin tSUD

D Q D Q

tLH = 0.0 nstLSU = 0.26 nstGHL= 8.9 ns

tDLH = 3.7 ns

tENHZ = 8.3 ns

tRD1 = 1.1 ns



G

G

DecodeModule

tPDD = 2.5 ns

tRDD = 0.3 ns

tRD2 = 1.7 nstRD4 = 2.6 ns

tCKH = 5.3 ns**

* Preliminary values shown for A32200DX-3 at worst-case commercial conditions.** Load-dependent.

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3200DX Timing Model (SRAM Funct ions)*


Input Delays

I/O Module

D Q

tINGO = 3.3 ns

tINPY = 1.4 ns tIRD1 = 1.9 ns

ARRAYCLOCKS

FMAX = 165 MHz

G

tGHL= 8.9 nstLSU = 0.26 ns

I/O Module

D Q

tLH = 0.0 ns

tDLH = 3.7 ns

G

WD [7:0]

WRAD [5:0]

BLKEN

WENWCLK

t ADSU = 1.5 nst ADH = 0.0 ns

tWENSU = 2.6 nstBENS = 2.6 ns

RD [7:0]

RDAD [5:0]

REN

RCLK

t ADSU = 1.5 nst ADH = 0.0 ns

tRENSUA = 0.6 ns

tRD1 = 1.1 ns


tRCO = 3.2 ns

*Values shown for A32200DX-3 at worst-case commercial conditions.

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Parameter Measurement

Output Buffer Delays

To AC test loads (shown below)PADD

E

TRIBUFF

In 50%

PADVOL

VOH1.5V

tDLH

50%

1.5V

tDHL

E 50%

PADVOL

1.5V

tENZL

50%

10%

tENLZ

E 50%

PADGND

VOH1.5V

tENZH

50%

90%

tENHZ

VCC

AC Test Loads

Load 1(Used to measure propagation delay)

Load 2(Used to measure rising/falling edges)

35 pF

To the output under testVCC GND

35 pF

To the output under test

R to V CC for t PLZ /tPZLR to GND for t PHZ /tPZHR = 1 k

Input Buffer Delays

PAD YINBUF

PAD

3V

0V1.5V

YGND

VCC50%

tINYH

1.5V

50%

tINYL

Module Delays

S AB

Y

S, A or B

Y

50%

tPLH

Y

50%

50% 50%

50% 50%tPHL

tPHLtPLH

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Sequent ia l Module Timing Character is t ics

Flip-Flops and Latches

(Positive Edge Triggered)

DE

CLK CLR

PRE Y

D1

G, CLK

E

Q

PRE, CLR

tWCLKA

tWASYN

tHD

tSUENA

tSUD

tRS

t A

tWCLKI

tCO

tHENA

Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.

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Sequent ia l Timing Character is t ics (continued)

Input Buffer Latches

G

PAD

PADCLK

DATA

G

CLK

tINH

CLKBUF

tINSU

tSUEXT

tHEXT

IBDLDATA

Output Buffer Latches

D

G

tOUTSU

tOUTH

PAD

OBDLHS

D

G

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Decode Module Timing

AG, H

Y

tPLH

50%

VCC

VCC

tPHL

Y

ABCD

EFG

H

SRAM Timing Character is t ics

WRAD [5:0]

BLKEN

WEN

WCLK

RDAD [5:0]

LEW

REN

RCLK

RD [7:0]WD [7:0]

Write Port Read Port

RAM Array

32x8 or 64x4

(256 Bits)

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Dual-Por t SRAM Timing Waveforms

3200DX SRAM Write Opera t ion

WCLK

WD[7:0]WRAD[5:0]

WEN

BLKEN Valid

Valid

tRCKHLtRCKHL

tWENSU

tBENSU

tWENH

tBENH

t ADSU t ADH

Note: Identical timing for falling-edge clock.

3200DX SRAM Synchronous Read Operation

RCLK

REN

RDAD[5:0]

RD[7:0] Old Data

Valid

tRCKHLtCKHL

tRENH

tRCO

t ADH

tDOH

t ADSU

New Data

tRENSU

Note: Identical timing for falling-edge clock.

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3200DX SRAM Asynchronous Read Opera t ionType 1

RDAD[5:0]

RD[7:0] Data 1

tRDADV

tDOH

ADDR2 ADDR1

Data 2

tRPD

(Read Address Controlled)

3200DX SRAM Asynchronous Read Opera t ionType 2

WEN

WD[7:0]

WCLK

RD[7:0] Old Data

Valid

tWENH

tRPD

tWENSU

New Data

tDOH

t ADSU

WRAD[5:0]BLKEN

t ADH

(Write Address Controlled)

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Predictable Per formance:Tight Delay Dist r ibut ions

Propagation delay between logic modules depends on theresistive and capacitive loading of the routing tracks, theinterconnect elements, and the module inputs being driven.Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of inputs increase.

From a design perspective, the propagation delay can bestatistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requiressome paths to have longer routing tracks.

The Integrator Series delivers a very tight fanout delay distribution. This tight distribution is achieved in two ways:by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path.

Actels patented PLICE antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricatedin 0.6 micron lithography, offer nominal levels of 100 ohmsresistance and 7.0 femtofarad (fF) capacitance per antifuse.

The Integrator Series fanout distribution is also tight due tothe low number of antifuses required for each interconnectpath. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses.

Timing Character is t ics

Timing characteristics for devices fall into three categories:family-dependent, device-dependent, and design-dependent.

The input and output buffer characteristics are common toall Integrator Series members. Internal routing delays aredevice-dependent. Design dependency means actual delays

are not determined until after placement and routing of theusers design is complete. Delay values may then bedetermined by using the Designer Series utility orperforming simulation with post-layout delays.

Cri t ica l Nets and Typica l Nets

Propagation delays in this data sheet apply to typical nets,

which are used for initial design performance evaluation.The abundant routing resources in the Integrator Seriesarchitecture allows for deterministic timing. UsingDirectTime, a timing-driven place and route tool in ActelsDesigner Series development software, the designer may specify timing-critical nets and system clock frequency.Using these timing specifications, the place and routesoftware optimize the design layout to meet the usersspecifications.

Long Tracks

Some nets in the design use long tracks, which are specialrouting resources that span multiple rows, columns, ormodules. Long tracks employ three and sometimes fourantifuse connections. This increases capacitance andresistance, resulting in longer net delays for macrosconnected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks contributeapproximately 3 ns to 6 ns delay, which is representedstatistically in higher fanout (FO=8) routing delays in thedata sheet specifications section.

Timing Dera t ing

A timing derating factor of 0.45 is used to reflect best-caseprocessing. Note that this factor is relative to the standard

speed timing parameters, and must be multiplied by theappropriate voltage and temperature derating factors for a given application.

Timing Derat ing Factor (Temperature and Vol tage)

Industrial Military

Min. Max. Min. Max.

(Commercial Specification) x 0.69 1.11 0.67 1.23

Timing Derat ing Factor for Designs at Typical Temperature (T J = 25C)and Vol tage

(Maximum Specification, Worst-Case Condition) x 0.85

(5 .0V)

Note: This derating factor applies to all routing and propagation delays.

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Temperature and Vol tage Derat ing Factors(Normal ized to Worst -Case Commercial , T J = 4.75V, 70C)

55 40 0 25 70 85 125

4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23

4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16

5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13

5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09

5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

4.50 4.75 5.00 5.25 5.50

D e r a

t i n g

F a c

t o r

125

85C70C

25C

0C

4055

Junction Temperature and Voltage Derating Curves(Normalized to Worst-Case Commercial, T J = 4.75V, 70C)

Note: This derating factor applies to all routing and propagation delays.

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A1225XL Timing Character is t ics (continued)

(Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C)

2 Speed 1 Speed Std Speed F Speed 3.3V StdSpeed

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

tINYH Pad-to-Y High 1.1 1.2 1.4 2.0 1.7 ns

tINYL Pad-to-Y Low 1.3 1.4 1.7 2.4 2.0 ns

tINGH G-to-Y High 2.0 2.3 2.7 3.9 3.2 ns

tINGL G-to-Y Low 2.6 3.0 3.5 5.0 4.2 ns

Input Module Predicted Routing Delays 1

tIRD1 FO=1 Routing Delay 2.9 3.3 3.9 5.6 4.7 ns





Global Clock Network

tCKH Input Low to HighFO = 32 FO = 256

5.15.7

5.86.5

6.87.6

9.710.9

8.29.1 ns

tCKL Input High to LowFO = 32 FO = 256

5.05.7

5.76.5

6.77.6

9.610.9

8.09.1 ns

tPWH Minimum Pulse Width HighFO = 32 FO = 256

2.62.7

3.03.1

3.53.6

5.05.1

4.24.3 ns

tPWL Minimum Pulse Width LowFO = 32 FO = 256

2.62.7

3.03.1

3.53.6

5.05.1

4.24.3 ns

tCKSW Maximum SkewFO = 32 FO = 256

0.80.8

0.90.9

1.01.0

1.41.4

1.21.2 ns

tSUEXT Input Latch External Set-UpFO = 32 FO = 256

0.00.0

0.00.0

0.00.0

0.00.0

0.00.0 ns

tHEXT Input Latch External HoldFO = 32 FO = 256

2.63.2

2.93.7

3.44.3

4.96.1

4.15.2 ns

tP Minimum PeriodFO = 32 FO = 256

5.45.6

6.16.3

7.27.4

10.310.6

8.68.9 ns

f MAX Maximum FrequencyFO = 32 FO = 256

225200

200180

170155

120.105

115105 MHz

Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

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TTL Output Module Timing 1

tDLH Data-to-Pad High 3.8 4.3 5.0 7.1 6.0 ns

tDHL Data-to-Pad Low 4.1 4.6 5.4 7.7 6.5 ns

tENZH Enable-Pad Z to High 3.8 4.3 5.0 7.1 6.0 ns

tENZL Enable-Pad Z to Low 4.1 4.7 5.5 7.9 6.5 ns

tENHZ Enable-Pad High to Z 5.4 6.1 7.2 10.3 8.6 ns

tENLZ Enable-Pad Low to Z 5.4 6.1 7.2 10.3 8.6 ns

tGLH G-to-Pad High 4.2 4.8 5.6 8.0 6.7 ns

tGHL G-to-Pad Low 4.7 5.4 6.3 9.0 7.6 ns

tLCO I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading 9.0 10.0 12.0 17.2 14.4 ns

t ACO Array Clock-Out (Pad-to-Pad),

64 Clock Loading 12.8 14.4 17.0 24.3 20.4 ns

dTLH Capacitive Loading, Low to High 0.04 0.04 0.05 0.06 0.06 ns/pF

dTHL Capacitive Loading, High to Low 0.05 0.06 0.07 0.08 0.08 ns/pF

CMOS Output Module Timing 1










t ACO Array Clock-Out (Pad-to-Pad), 64 Clock Loading 15.0 17.0 20.0 28.6 24.0 ns



Note: 1. Delays based on 35 pF loading.

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A1240XL Timing Character is t ics

(Wors t-Case Commercia l Condi t ions , V C C = 4.75 V, T J = 70C)

3 Speed 2 Speed 1 Speed Std Speed F Speed


Logic ModulePropagation Delays 1

tPD1 Single Module 2.6 3.0 3.5 5.0 4.2 ns

tCO Sequential Clk-to-Q 2.6 3.0 3.5 5.0 4.2 ns

tGO Latch G-to-Q 2.6 3.0 3.5 5.0 4.2 ns

tRS Flip-Flop (Latch) Reset-to-Q 2.6 3.0 3.5 5.0 4.2 ns

Predicted Routing Delays 2

tRD1 FO=1 Routing Delay 1.1 1.2 1.4 2.0 1.7 ns





Sequential Timing Characteristics 3, 4

tSUD Flip-Flop (Latch) Data Input Set-Up 0.4 0.4 0.5 0.7 0.6 ns

tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns

tSUENA Flip-Flop (Latch) Enable Set-Up 0.8 0.9 1.0 1.4 1.2 ns

tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns

tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.4 3.8 4.5 6.4 5.4 ns

tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 3.4 3.8 4.5 6.4 5.4 ns

t A Flip-Flop Clock Input Period 6.8 7.7 9.1 13.0 10.9 ns

tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input Buffer Latch Set-Up 0.3 0.4 0.4 0.6 0.5 ns

tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tOUTSU Output Buffer Latch Set-Up 0.3 0.4 0.4 0.6 0.5 ns

f MAX Flip-Flop (Latch) Clock Frequency 215 190 160 110 105 MHz

Notes: 1. For dual-module macros, use t PD1+ t RD1+ t PDn , tCO+ t RD1+ t PDn or t PD1+ t RD1+ t SUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time.

5. V CC = 3.0V for 3.3V specifications.

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tINGL G-to-Y Low 2.6 3.0 3.5 5.0 4.2 ns









5.15.7

5.86.5

6.87.6

9.710.9

8.29.1

nsns


5.05.7

5.76.5

6.77.6

9.610.9

8.09.1

nsns


2.72.9

3.13.3

3.63.9

5.15.6

4.34.7

nsns


2.72.9

3.13.3

3.63.9

5.15.6

4.34.7

nsns


0.80.8

0.90.9

1.01.0

1.41.4

1.21.2

nsns


0.00.0

0.00.0

0.00.0

0.00.0

0.00.0

nsns


2.63.2

2.93.7

3.44.3

4.96.1

4.15.2

nsns


5.66.0

6.36.8

7.48.0

10.611.4

8.99.6

nsns


215195

190170

160144

110100

10595

MHzMHz



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t ACO Array Clock-Out (Pad-to-Pad),

64 Clock Loading 12.9 14.6 17.2 24.6 20.6 nsdTLH Capacity Loading, Low to High 0.04 0.04 0.05 0.06 0.06 ns/pF

dTHL Capacity Loading, High to Low 0.05 0.06 0.07 0.08 0.08 ns/pF









tGHL G-to-Pad Low 4.7 5.4 6.3 9.0 7.6 nstLCO I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading 10.9 12.4 14.5 20.7 17.4 ns


dTLH Capacity Loading, Low to High 0.05 0.06 0.07 0.08 0.08 ns/pF

dTHL Capacity Loading, High to Low 0.05 0.05 0.06 0.07 0.07 ns/pF


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A3265DX Timing Character is t ics





Combinatorial Functions

tPD Internal Array Module Delay 2.1 2.4 2.9 3.7 3.2 ns

tPDD Internal Decode Module Delay 2.5 2.8 3.4 4.4 3.7 ns







tRDD Decode-to-Output Routing Delay 0.46 0.5 0.62 0.8 0.7 ns

Sequential Timing Characteristics 3, 4

tCO Flip-Flop Clock-to-Output 2.3 2.7 3.1 4.1 3.5 ns

tGO Latch Gate-to-Output 2.1 2.4 2.9 3.7 3.2 ns

tSUD Flip-Flop (Latch) Set-Up Time 0.35 0.4 0.47 0.6 0.5 ns

tHD Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns

tRO Flip-Flop (Latch) Reset to Output 2.3 2.7 3.1 4.1 3.5 ns





Notes: 1. For dual-module macros, use t PD1+ t RD1+ t PDn , tCO+ t RD1+ t PDn or t PD1+ t RD1+ t SUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device





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A3265DX Timing Character is t ics (continued)





tINPY Input Data Pad-to-Y 1.4 1.6 1.9 2.4 2.1 ns

tINGO Input Latch Gate-to-Output 3.3 3.7 4.4 5.7 4.8 ns

tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input Latch Set-Up 0.5 0.6 0.7 0.9 0.8 ns

tILA Latch Active Pulse Width 5.1 5.9 6.9 9.0 7.7 ns






tIRD5 FO=8 Routing Delay 6.6 7.5 8.8 11.4 9.7 nstIRDD Decode-to-Output Routing Delay 0.37 0.4 0.5 0.7 0.6 ns


tCKH Input Low to High FO=32 FO=256

6.37.4

7.18.4

8.49.9

10.912.8

9.210.9

nsns

tCKL Input High to Low FO=32 FO=256

5.96.4

6.67.3

7.88.6

10.111.2

8.69.5

nsns

tPW Minimum Pulse Width FO=32 FO=256

3.23.4

3.73.9

4.34.6

5.66.0

4.85.1

nsns

tCKSW Maximum Skew FO=32 FO=256

0.750.75

0.90.9

1.01.0

1.31.3

1.11.1

nsns

tSUEXT Input Latch External Set-Up FO=32

FO=2560.00.0

0.00.0

0.00.0

0.00.0

0.00.0

nsns

tHEXT Input Latch External Hold FO=32

FO=256 2.52.5 2.92.9 3.43.4 4.44.4 3.83.8 nsns

tP Minimum Period (1/fmax) FO=32 FO=256

5.06.0

7.28.3

8.39.5

11.913.6

9.210.6

nsns

f MAX Maximum Datapath Frequency FO=32

FO=256173151

138121

120105

8474

10895

MHzMHz



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A1280XL Timing Character is t ics

(Wors t-Case Commercia l Condi t ions , V C C = 4.75 V, T J = 70C)




tPD1 Single Module 2.6 3.0 3.5 5.0 4.2 ns

tCO Sequential Clk-to-Q 2.6 3.0 3.5 5.0 4.2 ns

tGO Latch G-to-Q 2.6 3.0 3.5 5.0 4.2 ns

tRS Flip-Flop (Latch) Reset-to-Q 2.6 3.0 3.5 5.0 4.2 ns







Sequential Timing Characteristics 3,4

tSUD Flip-Flop (Latch) Data Input Set-Up 0.4 0.4 0.5 0.7 0.6 ns

tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns





t A Flip-Flop Clock Input Period 8.0 8.7 10.0 14.0 12.0 ns

tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input Buffer Latch Set-Up 0.3 0.4 0.4 0.6 0.5 ns

tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tOUTSU Output Buffer Latch Set-Up 0.3 0.4 0.4 0.6 0.5 ns

f MAX Flip-Flop (Latch) Clock Frequency 200 167 130 90 110 MHz

Notes: 1. For dual-module macros, use t PD1+ t RD1+ t PDn , tCO+ t RD1+ t PDn , or t PD1+ t RD1+ t SUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device





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tINGL G-to-Y Low 2.6 3.0 3.5 5.0 4.2 ns









5.15.7

5.86.5

6.87.6

9.710.9

8.29.1

nsns


5.05.7

5.76.5

6.77.6

9.610.9

8.09.1

nsns


3.23.5

3.53.9

4.34.6

6.16.6

5.25.5

nsns


3.23.5

3.53.9

4.34.6

6.16.6

5.25.5

nsns


0.80.8

0.90.9

1.01.0

1.41.4

1.21.2

nsns


0.00.0

0.00.0

0.00.0

0.00.0

0.00.0

nsns


2.63.2

2.93.7

3.44.3

4.96.1

4.15.2

nsns


6.57.2

7.48.0

8.79.6

12.413.7

10.411.5

nsns


200180

167150

143130

10090

120110

MHzMHz



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A1280XL Timing Character is t ics (continued)(Worst-Case Commercial Conditions V CC = 4.75 V, T J = 70C)






























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3 Speed 2 Speed 1 Speed Std Speed F Speed 3.3V StdSpeed

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic ModulePropagation Delays


tPD Internal Array Module Delay 2.2 2.6 3.0 3.5 5.2 4.1 ns

tPDD Internal Decode Module Delay 2.4 2.7 3.1 3.7 5.7 4.3 ns

Predicted Module Routing Delays

tRD1 FO=1 Routing Delay 1.0 1.1 1.3 1.5 3.3 1.7 ns





tRDD Decode-to-Output Routing Delay 0.3 0.37 0.4 0.5 0.4 0.6 ns

Sequential Timing CharacteristicstCO Flip-Flop Clock-to-Output 2.2 2.6 3.0 3.5 5.0 4.1 ns

tGO Latch Gate-to-Output 2.2 2.6 3.0 3.5 5.0 4.1 ns

tSU Flip-Flop (Latch) Set-Up Time 0.3 0.37 0.4 0.5 0.7 0.6 ns

tH Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 ns

tRO Flip-Flop (Latch) Reset to Output 2.2 2.6 3.0 3.5 5.0 4.1 ns

tSUENA Flip-Flop (Latch) Enable Set-Up 0.6 0.75 0.9 1.0 1.4 0.85 ns

tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 0.0 ns

tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.1 3.7 4.2 4.9 7.0 5.7 ns

tWASYN Flip-Flop (Latch) Asynchronous PulseWidth 4.1 4.8 5.4 6.4 7.0 7.5 ns

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Logic Module Timing

Synchronous SRAM Operations

tRC Read Cycle Time 6.4 7.5 8.5 10.0 14.3 11.7 ns

tWC Write Cycle Time 6.4 7.5 8.5 10.0 14.3 11.7 ns

tRCKHL Clock High/Low Time 3.2 3.8 4.3 5.0 7.1 5.9 ns

tRCO Data Valid After Clock High/Low 3.2 3.8 4.3 5.0 7.1 5.9 ns

t ADSU Address/Data Set-Up Time 1.5 1.8 2.0 2.4 3.4 2.8 ns

t ADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 ns

tRENSU Read Enable Set-Up 0.6 0.7 0.8 0.9 1.3 1.0 ns

tRENH Read Enable Hold 3.2 3.8 4.3 5.0 7.1 5.9 ns

tWENSU Write Enable Set-Up 2.6 3.0 3.4 4.0 5.7 4.7 ns

tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 0.0 nstBENS Block Enable Set-Up 2.6 3.1 3.5 4.1 5.8 4.8 ns

tBENH Block Enable Hold 0.0 0.0 0.0 0.0 0.0 0.0 ns

Asynchronous SRAM Operations

tRPD Asynchronous Access Time 7.7 9.0 10.2 12.0 17.2 14.1 ns

tRDADV Read Address Valid 8.3 9.8 11.1 13.0 18.6 15.2 ns

t ADSU Address/Data Set-Up Time 1.5 1.8 2.0 2.4 3.4 2.8 ns

t ADH Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 ns

tRENSUA Read Enable Set-Up to Address Valid 0.57 0.7 0.8 0.9 1.3 1.0 ns

tRENHA Read Enable Hold 3.2 3.8 4.3 5.0 7.1 5.9 ns

tWENSU Write Enable Set-Up 2.6 3.0 3.4 4.0 5.7 4.7 ns

tWENH Write Enable Hold 0.0 0.0 0.0 0.0 0.0 0.0 nstDOH Data Out Hold Time 1.1 1.35 1.5 1.8 2.6 2.1 ns

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tDLH Data-to-Pad High 3.7 4.3 4.9 5.8 8.2 6.8 ns

tDHL Data-to-Pad Low 4.5 5.3 6.0 7.1 10.1 8.3 ns

tENZH Enable-Pad Z to High 4.8 5.6 6.4 7.5 10.7 8.8 ns

tENZL Enable-Pad Z to Low 5.1 6.0 6.8 8.0 11.4 9.4 ns

tENHZ Enable-Pad High to Z 8.3 9.8 11.1 13.0 18.5 15.2 ns

tENLZ Enable-Pad Low to Z 8.3 9.8 11.1 13.0 18.5 15.2 ns

tGLH G-to-Pad High 8.3 9.8 11.1 13.0 18.5 15.2 ns

tGHL G-to-Pad Low 9.0 10.5 12.0 14.1 20.1 16.4 ns

tLSU I/O Latch Output Set-Up 0.26 0.3 0.34 0.4 0.6 0.6 ns

tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 0.0 ns

tLCO

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 8.4 9.8 11.1 13.1 18.7 15.3 ns

t ACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 11.8 13.8 15.7 18.5 26.5 21.7 ns

dTLH Capacitive Loading, Low to High 0.03 0.037 0.04 0.05 0.07 0.06 ns/pF

dTHL Capacitive Loading, High to Low 0.04 0.05 0.06 0.07 0.10 0.08 ns/pF

tWDO Hard-Wired Wide-Decode Output 0.04 0.045 0.05 0.06 0.09 0.07 ns


tDLH Data-to-Pad High 4.5 5.3 6.0 7.1 10.1 8.3 ns

tDHL Data-to-Pad Low 3.7 4.3 4.9 5.8 8.2 6.8 ns

tENZH Enable-Pad Z to High 4.8 5.6 6.4 7.5 10.7 8.8 ns

tENZL Enable-Pad Z to Low 5.1 6.0 6.8 8.0 11.4 9.4 ns

tENHZ Enable-Pad High to Z 8.3 9.8 11.1 13.0 18.5 15.2 nstENLZ Enable-Pad Low to Z 8.3 9.8 11.1 13.0 18.5 15.2 ns

tGLH G-to-Pad High 8.3 9.8 11.1 13.0 18.5 15.2 ns

tGHL G-to-Pad Low 9.0 10.5 12.0 14.1 20.0 16.4 ns

tLSU I/O Latch Set-Up 0.26 0.3 0.3 0.4 0.6 0.6 ns

tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 0.0 ns

tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 9.9 11.0 13.2 15.5 22.3 18.2 ns

t ACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 13.9 16.4 18.5 21.8 30.0 25.6 ns

dTLH Capacitive Loading, Low to High 0.04 0.052 0.05 0.07 0.10 0.08 ns/pF

dTHL Capacitive Loading, High to Low 0.04 0.045 0.05 0.06 0.09 0.07 ns/pF

tWDO Hard-Wired Wide-Decode Output 0.04 0.045 0.05 0.06 0.09 0.07 ns



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Logic Module Propagation Delays 1


tPD Internal Array Module Delay 1.8 2.3 2.8 3.6 3.2 ns

tPDD Internal Decode Module Delay 1.9 2.5 3.0 3.8 3.5 ns







tRDD Decode-to-Output Routing Delay 0.5 0.7 0.78 1.0 0.91 ns

Sequential Timing Characteristics3, 4

tCO Flip-Flop Clock-to-Output 2.1 2.8 3.3 4.3 3.9 ns

tGO Latch Gate-to-Output 1.8 2.3 2.8 3.6 3.2 ns

tSU Flip-Flop (Latch) Set-Up Time 0.3 0.4 0.47 0.6 0.55 ns

tH Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns

tRO Flip-Flop (Latch) Reset to Output 2.1 2.8 3.3 4.3 3.9 ns





Notes: 1. For dual-module macros, use t PD1+ t RD1+ t PDn , tCO+ t RD1+ t PDn , or t PD1+ t RD1+ t SUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device


the DirectTime Analyzer utility. 4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time.

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tINPY Input Data Pad-to-Y 1.2 1.6 1.9 2.4 2.2 ns

tINGO Input Latch Gate-to-Output 2.3 3.1 3.7 4.7 4.3 ns

tINH Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input Latch Set-Up 0.3 0.4 0.47 0.6 0.55 ns

tILA Latch Active Pulse Width 3.1 4.2 4.9 6.4 5.7 ns






tIRD5 FO=8 Routing Delay 5.6 7.5 8.8 11.4 10.3 nstIRDD Decode-to-Output Routing Delay 0.3 0.4 0.5 0.7 0.6 ns


tCKH Input Low to High FO=32 FO=486

6.26.8

8.39.1

9.710.7

12.713.9

11.412.5

nsns

tCKL Input High to Low FO=32 FO=486

6.126.7

8.28.9

9.610.5

12.513.6

11.312.3

nsns

tPW Minimum Pulse Width FO=32 FO=486

2.72.9

3.73.9

4.34.6

5.66.0

5.05.41

nsns

tCKSW Maximum Skew FO=32 FO=486

0.60.6

0.90.9

1.01.0

1.31.3

1.171.17

nsns

tSUEXT Input Latch External Set-Up FO=32

FO=4860.00.0

0.00.0

0.00.0

0.00.0

0.00.0

nsns

tHEXT Input Latch External Hold

FO=32

FO=486 2.22.2 2.92.9 3.43.4 4.44.4 4.04.0 nsns

tP Minimum Period (1/fmax) FO=32 FO=486

5.76.6

7.68.3

8.39.5

11.913.6

9.011.1

nsns

f MAX Maximum Datapath Frequency FO=32

FO=486173151

138121

120105

8474

10290

MHzMHz



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Parameter Descriptio

1200xl actel

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