Scuola Nazionale di Legnaro29/3/2007

Single Event Effects: SRAM

Alessandro Paccagnella

Dipartimento di Ingegneria dell’InformazioneUniversità di Padova

alessandro.paccagnella@unipd.it

A. Paccagnella

OUTLINE

IntroductionThe first SEE observations on RAMs’: DRAMSingle Event impact on CMOS inverter and SRAM cell: flipping the bitSRAM SEU:

mapping cross sectioncritical charge

Scaling issues in SRAM SEUNon-volatile memoriesConclusions

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Why SEE’s on SRAM’s?The Static Random Access Memory (SRAM) is a benchmark to evaluate the SEE sensitivitySRAM is the easiest latch to be fabricated in standard CMOS technology (DRAM or FLASH need dedicated process steps)SRAM’s are widely used in all logic circuitsSRAM cell size scales with Moore’s lawSRAM cells can be simulated in detailMemories are easier to test than logic (such as DSP)SEE measurements are straightforward even on commercial parts

Introduction

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SEE’s in memories typically refer to the loss of information from a memory cell caused by a single ionizing particle: Single Event Upset (SEU)In a Flip-Flop (Latch) the information corruption is associated to the bit flip : 0 � 1 or 1 � 0 and is reversible : the right bit can be rewrittenMemory arrays are organized in words and more than one SEU may affect a single word:

Single Bit Upset (SBU)Multiple Bit Upset (MBU)

Soft Error Rate (SER)First report on memories: a bipolar flip-flop circuit (Binder et al., 1975) affected by cosmic rays in satellitesRAMs may be affected also by permanent SE effects (i.e., stuck bits )

Early reports of SEE’s in memories

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SEU in early DRAMs: no effect on “0”

T.C. May and M.H. Woods, IEEE-TED26, 1979

“0” “0”

“0” “0”

The DRAM case: SEU’s observed at sea level in Intel 16K DRAM’s (1979) generated by alpha particles produced by radioactive contaminants

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“1” “1”

“1” “0”

SEU in early DRAMs: “1” flips

T.C. May and M.H. Woods, IEEE-TED26, 1979

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Critical Charge in DRAM’s

Usually the Critical Charge is defined as Qcrit = Vc

. Cs, where Cs is storage capacitanceCritical voltage, Vc, is typically half the power supply voltageIn SRAM cells things may be substantially different…

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6-Transistor (6T) CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ

J.Rabey, Digital Integrated Circuits, Prentice Hall, 1996

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SE in CMOS inverter: OUT = 1

N+N+

VSS

VDD

PMOS0

A current isobserved

ION

P substrate

in out

0 1•The output node out isdischarged•A current isinjected by thePMOSFET into the outnode to restore theinitial charge and logicvalueP. Fouillat, EWRHE 2004

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SE in CMOS inverter: OUT = 0

N+ N+

VSS

VDD

PMOS1

P substrate

No current isobserved

ION

in out

1 0

P. Fouillat, EWRHE 2004

Only reversed biased junctions of off-state MOSFET drains may effectively collect charge and affect the out node voltage

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SEU in SRAM cell

0 1

1 0

VDD

VSS

VDD

VSS

ION

Upsetting a memory cell

P. Fouillat, EWRHE 2004

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6T-SRAM — Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6

J.Rabey, Digital Integrated Circuits, Prentice Hall, 1996

PMOSFETs

NMOSFETs

CMOS INVERTERS:

Pass-Transistors toBit Lines

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10pJ

Red points=

Single-Event Upset=

flip of the logical state inducedby a single laser pulse

Basic SRAM Test Vehicle(6 transistors)

10 µm

SEU mapping in an SRAM cell

Laser Pulse Energy

30pJ

49pJ

120pJ

177pJ

305pJ

588pJ

891pJ

1193pJ

SEU sensitivity map

�SEU mechanisms�Rate prediction�Design optimisationP. Fouillat, EWRHE 2004

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SEU Laser cross section in SRAM

0 200 400 600 800 1000 1200

1E-9

1E-8

1E-7

1E-6

1E-5

Cro

ss s

ectio

n (c

m²)

Incident energy (pJ)10pJ

30pJ

49pJ

120pJ

177pJ305pJ 588pJ 891pJ 1193pJ

P. Fouillat, EWRHE 2004

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Testing SRAMs: heavy ions vs. laser

0 500 1000 1500 2000 2500 3000 35001E-5

1E-4

1E-3

0,01

0,1

1

10

Lase

r SE

U c

ross

sec

tion

(cm

2 /dev

ice)

Laser energy (pJ)

Hitachi HM628512A NEC µPD431000A

0 10 20 30 40 50 60 70 801E-5

1E-4

1E-3

0,01

0,1

1

10

SE

U c

ross

-sec

tion

(cm

2 /dev

ice)

LET (MeV.cm 2.mg -1)

Hitachi HM628512A NEC µPD431000A

Laser Tests Heavy ion Tests

HITACHI A 4Mbits 0.5µm versus NEC 1Mbits 0.8µm

P. Fouillat, EWRHE 2004

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Increasing SEU resistance of SRAM cells

Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells:Enhance storage capacitance (STMicroelectronics)Use 6T cell design with TFT load devices

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Thin Film Transistor for 6T SRAM cell

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Increasing SEU resistance of SRAM cells

Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells:Enhance storage capacitance (STMicroelectronics)Use 6T cell design with TFT load devicesUse retrograde wells, i.e., highly doped implanted layers in order to reduce charge collection at the drain nodes

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Retrograde well doping profile

R.D. Rung et al., IEEE-TED28, 1981

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Increasing SEU resistance of SRAM cells

Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells:Enhance storage capacitance (STMicroelectronics)Use 6T cell design with TFT load devicesUse retrograde wells, i.e., highly doped implanted layers in order to reduce charge collection at the drain nodesEliminate 10B from the external passivation layers and internal p-doped B rich regions: nuclear reactions from thermal neutrons are suppressed Use plastic packaging instead of ceramic, reducing the amount of radioactive alpha emitters around the Si chip

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Critical charge in SRAM: status of the art

Usually, critical charge: Qcrit = Vc

. Cs

Vc ~ VG [/2]Cs ~ W . L . εox / tox

Qc ~ L2

Collected charge:Qcoll ~ L

However in SRAM:Qcrit = Vc

. Cs + Irestore. Τflip

Further, parasitic capacitance from Local Interconnections (LIC) may strongly increase Cs thus improving SEU immunity (Samsung, IEDM2002)

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SRAM/Logic Scaling Trends

R. Baumann, RADECS Short Course, 2001

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SRAM SER evolution

P. Dodd, et al., IEEE-TNS50, 2003

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Logic is going to affect SER

R. Baumann, IEEE-TDMR, 2005

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Multiple bit upset

A single ion may flip two bits or more inside the same memory word: MBU Identify safe locations for other bit cells

Optimize layout aspect ratio and critical node locationsDetermine minimum spacing of bits in word line

D.G. Mavis, EWRHE 2004

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Time

Rel

ativ

e E

vent

Rat

es p

er B

it or

Dev

ice

Feature size shrinkage1994 2004

Speed kills – SETs drive increase

SEL –Single Event

Latchup

SEFI –Single EventFunctionalInterrupt

Changes in technology vs. SRAM SEU

*Electronics manufacturersare concerned with soft error

rates (SER) on the ground and are beginning to insertmeans of reducing SER

Notion

al gr

aph of

RAM

SEU Tre

nds BER -Bit Error Rate*

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Floating Gate memories overview

Electrons stored in the FG �VTH growsWriting (Flash):

Channel Hot Electron tunnelling

Erasing (Flash): Fowler-Nordheim tunnelling

Main reliability issues:- Endurance (W/R/E cycles)- Data retention

(CG)

(FG)

Tunnel Oxide

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∆VTH spatial distribution

After 2x107 Iodine ions/cm2

All cells programmed to “1”Multiple Hits on a cell (~1.5% of hit cells)

Arrows: |∆VTH|>2V3 bits with VTH<4V

-∆V

TH

G. Cellere et al., IEEE TNS48, 2001

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Retention properties of Floating Gate memories

FG cells should ensure a data retention time of 10 yrs at room temperature : low leakage from FGAccelerated electrical stresses are customarily performed in order to verify that Write/Erase electrical operations at high fields do not endanger the long time retention propertiesAppearance of single failing bits is a big concern!Data retention properties of irradiated FG cells: an open question

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VTH statistical distribution

0.15µm2 FG devicesI ion irradiationA secondary peak appears at ~6VThe very low VTHtail is probably due to double hits (1.5% of hit cells at this fluence)

1

10

100

1000

10000

100000

4 5 6 7 8VTH (V)

Num

ber

of c

ells

FreshAfter 2x107 I ions /cm2

No known mechanism can explain this large charge lo ss

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Data retention in hit FG cells

Hit devicesonly were re-programmed

After only30min a cleartail appears……whichincreasesmore and more withtime After 20 days, ∆VTH ~ 4V

3 4 5 6 7 8

VTH (V)

Cum

ulat

ive

prob

abili

ty

0.002%

0.012%

0.09%

0.67%

4.8%

30.7%

93.4%

99.99%

After program

After 30 min

After 20 days

0.04µm2 (small) devices

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Model vs. experimental data

Experimental data obtained from 0.04µm2 device irradiated with I previously shownBars � variance (spread) of experimental data Lines �calculations

FOX (MV/cm)

I G (

A)

ExperimentalSimulated

0.8 1 1.2 1.4 1.6 1.8

10-18

10-19

10-20

10-21

10-22

10-23

10-24

10-25

10-26

FOX (MV/cm)

I G (

A)

ExperimentalSimulated

0.8 1 1.2 1.4 1.6 1.8

10-18

10-19

10-20

10-21

10-22

10-23

10-24

10-25

10-26

With 20 defects, good agreement on:Mean valueExtreme values (spread)

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Conclusions

Reversed biased junctions of off-state MOSFET drains collect charge produced by a single ionizing particle, possibly leading to SRAM cell bit flipIn SRAM SEU cross section saturates at high LETCritical charge for upset decreases with CMOS minimum feature size, but it may be enhanced by parasitic capacitances coming from interconnectionsSBU’s can be compensated by EDAC ; MBU’s are much less likely but more dangerousSEU rate of SRAM cell array is not increasing with memory generation, but new problems may come from upsets in the circuit external to the memory array and SE TransientsPermanent damage may affect RAM and non-volatile memories as well