11/1/2004 EE 42 fall 2004 lecture 26 1

Lecture #26 Gate delays, MOS logic

Today:

• Gate delays

• Another look at CMOS logic transistors

11/1/2004 EE 42 fall 2004 lecture 26 2

Controlled Switch Model of Inverter

What is the gate delay D for this simple inverter?

RN

+

--

VDD = 3V

VSS = 0V

VIN =3V

VOUT

+

--

VDD = 3V

VSS = 0V

VIN =0V RP

VOUT

VIN jumps from 0V to 3V

VIN jumps from 3V to 0V

VOUT

t

3

0

Output when:

If we define D as the time to go halfway to the asymtotic limit, D = 0.69RC . To get equal delays we will need to set RP = RN.

D

11/1/2004 EE 42 fall 2004 lecture 26 3

Simple model for logic delays (slide 2 again)We model actual logic gate as an ideal logic gate fed by

an RC network which represents the dominant R and C in the gate.

t

vIN

VX

D = 0. 69 RC

vOUT

)t(vOUT

)t(v INR

C

Ideal Logic gate

Model of Actual Logic Gate

Ideal Logic gate

VX

)t(vOUT

etc.

This model is very close to real physics: the transistors are inherently extremely fast, but are slowed by the need to charge up (or discharge) the capacitance at the various nodes.

11/1/2004 EE 42 fall 2004 lecture 26 4

CMOS Logic Gate

A

B

C

A

B C

VDD

VOUT

NMOS conduct when input is high.

PMOS only in pull-up

NMOS and PMOS use the same set of input signals

PMOS conduct when input is low

NMOS only in pull-down

NMOS conduct for A + (BC)

PMOS do not conduct when A +(BC)

Logic is Complementary and produces F = A + (BC)

11/1/2004 EE 42 fall 2004 lecture 26 5

CMOS Logic Gate: Example Inputs

A

B

C

A

B C

VDD

VOUT

NMOS do not conduct

Logic is Complementary and produces F = 1

A = 0B = 0C = 0

PMOS all conduct

Output is High

= VDD

11/1/2004 EE 42 fall 2004 lecture 26 6

CMOS Logic Gate: Example Inputs

A

B

C

A

B C

VDD

VOUT

NMOS B and C conduct; A open

Logic is Complementary and produces F = 0

A = 0B = 1C = 1

PMOS A conducts; B and C Open

Output is High

= 0

11/1/2004 EE 42 fall 2004 lecture 26 7

Switched Equivalent Resistance Network

A

B

C

A

B C

VDD

VOUT

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RDSwitches close when input is high.

Switches close when input is low.

11/1/2004 EE 42 fall 2004 lecture 26 8

Logic Gate Propagation Delay: Initial State

The initial state depends on the old (previous) inputs.

The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

Example: A=0, B=0, C=0 for a long time.

These inputs provided a path to VDD

for a long time and the capacitor has charged up to VDD = 5V.

11/1/2004 EE 42 fall 2004 lecture 26 9

Logic Gate Propagation Delay: Transient

At t=0, B and C switch from low to high (VDD) and A remains low.

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

COUT discharges through the pull-down resistance of gates B and C in series.

t = 0.69(RDB+RDC)COUT = 0.69(20k)(50fF) = 690 ps

The propagation delay is two times longer than that for the inverter!

This breaks the path from VOUT to VDD

And opens a path from VOUT to GND

11/1/2004 EE 42 fall 2004 lecture 26 10

Logic Gate: Worst Case Scenarios

What combination of previous and present logic inputs will make the Pull-Down the fastest?

What combination of previous and present logic inputs will make the Pull-Down the slowest?

What combination of previous and present logic inputs will make the Pull-Up the fastest?

What combination of previous and present logic inputs will make the Pull-Up the slowest?

Fastest overall?

Slowest overall?

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

11/1/2004 EE 42 fall 2004 lecture 26 11

MOS transistors

• The heart of digital logic is the MOS transistor, both NMOS and PMOS

• In the next couple of lectures, we will learn more about how CMOS logic works at the circuit level,

• starting with a review of the NMOS transistor

11/1/2004 EE 42 fall 2004 lecture 26 12

NMOS TRANSISTOR STRUCTURE

• An insulated gate is placed above the silicon

• Its purpose is to control the current between n-type regions (by inducing a “channel” of electrons when a positive V is applied).

•NMOS = N-channel Metal Oxide Silicon Transistor

nP-type Silicon

oxide insulatorgaten

“Metal” gate (Al or Si)

11/1/2004 EE 42 fall 2004 lecture 26 13

DEVICE IN CROSS-SECTIONMOS TRANSISTOR STRUCTURE

“Metal” “Semiconductor”“Oxide”

• The “gate” electrode is just a conductor to act as the capacitor top plate

• The lower “body” electrode is silicon with almost no electrons present (essentially an insulator)

• Thus no current can flow between the D and S electrodes which contact the silicon

n

P

oxide insulatorgate

n

“Metal” gate (Al or Si)D

S

G

11/1/2004 EE 42 fall 2004 lecture 26 14

DEVICE with + Gate VoltageMOS TRANSISTOR STRUCTURE

• Here the 5V across the capacitor induces + charge on the gate and – charge on the surface of the semiconductor, according to Q=CV.

• The charge in the semiconductor is really just free electrons which can carry current (just like the electrons in a metal can carry current).

• Thus by applying a voltage to the gate we have provided a conduction path for current if a voltage is applied from D to S.

n

P

oxide insulatorn

“Metal” gate (Al or Si)D

S

G+- 5V

+ + + + + + + + + + + +_ _ _ _ _ _ _ _ _ _ _ _

11/1/2004 EE 42 fall 2004 lecture 26 15

MOS Transistor as a controlled switch

But the device is not fundamentally ON/OFF. As VGS increases, the switch resistance decreases (slope becomes steeper).

VGS

S

Sioxide

+

+

G

VDS

Di

tox

iD Zero if VGS is small

iD

VDS

VGS > VT

VGS >> VT

Thus we have a “family of I-V curves” which describe the current into D as a function of both VDS and VGS

11/1/2004 EE 42 fall 2004 lecture 26 16

VDS

ID A)

10

(V)1 2

Three-Terminal Device Graphs

We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS of 2V)

3-Terminal Device

ID

DG

S

VGS

+-

ID versus VDS for VGS = 2V.

Concept of 3-Terminal Device Graphs:

So we can now plot the two-terminal characteristic (here ID versus VDS).

and conceptually draw a box around the device with only two terminals emerging

11/1/2004 EE 42 fall 2004 lecture 26 17

VDS

ID A)

10

(V)1 2

Three-Terminal Parametric Graphs

Concept of 3-Terminal Parametric Graphs:

We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS)

and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here ID versus VDS).

3-Terminal Device

ID

DG

S

VGS

+ -

VGS = 3

VGS = 2

VGS = 1

But we can do this for a variety of values of VGS with the result that we get a family of curves.

11/1/2004 EE 42 fall 2004 lecture 26 18

NMOS I vs V Characteristics

Example of experimental I-V characteristics. (You can do in the 43 Lab)

VGS

SG

VDS

iD

+ +

D

For low gate voltages, no drain current flows. As VGS is increased

above threshold, e.g. 1V, the nonlinear “saturating” I-V curve is

obtained. Increasing VGS causes ID to increase, as the family of curves

indicates.

ID

VDS

VGS

VGS = 0

VGS = 1

VGS = 1.5

VGS = 2

11/1/2004 EE 42 fall 2004 lecture 26 19

The Family of ID vs VGS Curves

For short-channel devices used in digital logic, the ID vs VDS curves are decidedly nonlinear! Curves which start out as simple linear resistors saturate as shown on this and the previous slide.

We can approximate the I-V characteristics as two straight lines.

a) the linear “resistance” region at low VDS and

b) the saturation region (almost horizontal) at larger VDS. 0 0.5

VDS

ID(mA)

4321

V1VV TGS

0.5

0.75

1.25

11/1/2004 EE 42 fall 2004 lecture 26 20

The circuit symbol

NMOS Summary

ID for VGS = maximum (VDD)

If VGS = 0.

G

S

DID

N ChIDS

ID

VDS

VDD

A value for RDN is chosen to give the correct timing delay.

Electrical Model

D

S

G

RDN

11/1/2004 EE 42 fall 2004 lecture 26 21

Remember the Role of the SwitchThe NMOS transistor conducts the charge out of the capacitor to ground when its input (VGS) is high (VDD).

RN

+

--

VDD = 3V

VSS = 0V

VIN =3V

VOUT

We cover up the non-useful parts of the circuit for simplicity.

Now lets draw the I-V characteristics of the NMOS

DG

S

The capacitor was initially at 3V (VDD), and goes toward zero. We define one stage delay by the time for VOUT = VDS to reach 1.5V (VDD /2).

VGS = VDD

IDS

ID

VDS

VGS = 0

VDDVDD/2

When VGS jumps to VDD, the current

jumps from zero to this value. As the capacitor discharges, V decreases

and the current follows the IDS vs VDS

curve. As a first approximation we will assume that =0

11/1/2004 EE 42 fall 2004 lecture 26 22

Computing the stage delayThe stage delay is the time for VOUT to decrease from VDD to VDD /2.

The capacitor is initially charged to 3V, and we want to see how long it takes to reach 1.5V. That is the delay.

As V goes from VDD to VDD /2, the average current IAV IDS( 1+X(3/4)VDD) ( IDS if is close to zero; consider this case first).We integrate the capacitor equation

dtdVCI to find the time:

/2)VI(C)dVI(CτDDAVAV

=CVDD/2IDS for = 0

VOUTRN

+

--

VIN =3V D

G

S

C+ -

IDS

ID

VDS

VGS = VDD

VGS = 0As the capacitor discharges, V decreases and the current

follows the IDS vs VDS curve.VDDVDD/2

11/1/2004 EE 42 fall 2004 lecture 26 23

Computing the stage delay (for 0)The stage delay is the time for VOUT to decrease from VDD to VDD /2.

Thus = CVDD/2IDS for = 0

That is = 0.52 CVDD/IDS which is only 4% larger than the value we found by doing the actual integration.

Now suppose we had instead assumed a resistance which averaged VDD/IDS and VDD/2IDS ,that is 3VDD/4IDS , shown as the blue line in the figure below.

VOUTRN

+

--

VIN =3V D

G

S

C+ -

IDS

ID

VDS

VGS = VDD

VGS = 0Here we approximate = 0 so the slope is zero

VDDVDD/2

We would compute = 0.69RC = 0.69 (3VDD/4IDS )C

11/1/2004 EE 42 fall 2004 lecture 26 24

Computing the stage delay (for >0)

Since IAV IDS( 1+X(3/4)VDD) we have =0.5C VDD / IDS( 1+X(3/4)VDD). Now lets compare with the value we would get using an averaged-value resistor (blue line below)

As VOUT goes from VDD to VDD /2, the average resistance is (3/4) VDD / IDS( 1+X(3/4)VDD) thus our time constant (0.69RC) equals

=0.69 C (3/4) VDD / IDS( 1+X(3/4)VDD) = 0.52 C VDD / IDS ( 1+X(3/4)VDD)

Again, this is only 4% different from the answer obtained by direct integration

VOUTRN

+

--

VIN =3V D

G

S

C+ -

We found by integration that /2)VI(C)dVI(CτDDAVAV

As the capacitor discharges, VOUT decreases

and the current follows the IDS vs VDS curve.

IDS

ID

VDS

VGS = VDD

VGS = 0

VDDVDD/2

11/1/2004 EE 42 fall 2004 lecture 26 25

Computing the stage delay - Summary

During the discharge of C through the NMOS transistor, we have shown that we can compute the stage delay by using the switch model with an effective resistance RDN = (3/4) VDD / IDS( 1+X(3/4)VDD)

Thus we can compute the stage delay, 0.69RDNC,

VOUTRN

+

--

VIN =3V D

G

S

C+ -

IDS ( 1+VDD)

IDS

ID

VDS

VGS = VDD

VGS = 0

VDDVDD/2 Electrical Model

D

S

G

RDN