11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan...
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Transcript of 11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan...
![Page 1: 11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan Hall 03/03/2005.](https://reader036.fdocuments.us/reader036/viewer/2022062305/5697c02a1a28abf838cd7d3b/html5/thumbnails/1.jpg)
11
Wireless Sensor Networks (WISeNET) CPU Group
Second Presentation Almir DavisYong Zhang
Halligan Hall 03/03/2005
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Agenda
Project Description
Sensor Card Diagram
Sensor & Transceiver
CPU Design
CPU Open Issues
Questions from the Preliminary Presentation
Current Questions
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Project Description
The project’s objective is to design a network of independent sensors that would be able to sense the chemical structure of air’s particles and communicate the findings to the base computing station.
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WSN Block Diagram
TRANCEIVERCPU
BASE STATIONFIXED LINE NETWORK
WIRELESS SENSOR
NETWORK
SENSOR CARD
TRANCEIVERCPU
SENSOR CARD
TR
AN
CE
IVE
RC
PUS
EN
SO
R C
AR
D
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Sensor Card
TRANCEIVER CPU
SENSOR CARD
TIO SIO
Sensor
I/O to WSN
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Biochemical Sensors:
A device incorporating a biochemical sensing element either intimately connected to or integrated within a transducer.
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Biochemical Sensors Principles:
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Current Sensors’ Detection Techniques
Surface wave acoustic detection
Ion mobility spectroscopy
Mass spectroscopy
Gas chromatography
Smart dust
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CPU Block Diagram
CPU
SENSOR 2
SENSOR 1
TRANSCEIVER
ALIVE1
READY1
DATA1
ALIVE2
READY2
DATA2
CLOCK RESET
RX_CTRL[1:0]
DATA_IN
TX_CTRL[1:0]
DATA_OUT
ADDR[2:0] RCV_DATA[8:0]
9
DV
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CPU Receive
sleep active sleep
valid
ADDR+DATAADDR+DATApreamblepreamble
value = 010000111
CLOCK
RX_CTRL[1:0]
DATA_OUT
DV
RCV_DATA[8:0]
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1111
CPU Transmit (part a)
000111
CLOCK
ALIVE1
READY1
DATA1
READY_I
DATA_I[5:0]
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CPU Transmit (part b)
valid
sleep active sleep
010
ADDR+DATAADDR+DATApreamblepreamble
value = 000111
CLOCK
READY_I
DATA_I[5:0]
TX_CTRL[1:0]
DATA_OUT
ADDR[2:0]
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WSN CPU Arbitration
011011 011100
receiving 011100receiving 011100
receiving 011011receiving 011011
CLOCK
ALIVE1
ALIVE2
READY1
READY2
DATA1
DATA2
DATA_I[5:0]
READY_I
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Open Issues
Shared sensor data bus
Clock frequency
“Active”, “Sleep” duty cycles
Internal CPU registers programmable wirelessly
In-Band Hot reset
Preamble size
Piggy-backed multi-sensor packets
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Questions from the Preliminary Presentation Can you put the CPU to sleep as well as the transceiver?
– Transceiver can be put to sleep. CPU cannot.
In transceiver design you might want to separate RX & TX paths with different antennas to avoid collision.
– Good observation. We will have separate control/data paths for the RX and TX side (reflected in the CPU design)
For power efficiency: A lot has to do with MOSFET scaling, voltage level, logic style, I/O pins. Will you address these issues?
– We address the issue by reducing the number of IO pins, reducing the internal CPU memory size, and reducing the gate count by reducing the number of features. We will also address the issue of MOSFET scaling by choosing the vendor with a power efficient chip technology.
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Questions from the Preliminary Presentation Ambitious project, well thought through out, but will the
end-product work?
Warning! If everyone communicates to the base station it may lead to congestion, dropped messages etc… Need to clarify this transfer of data early on.
– Na Wang, PH.D. student and the member of Professor’s Chang project team is assigned to deal with network related issues including the congestion issues.
Automatic power optimization after behavioral HDL code.
– Good point. We do it at the RTL level but would appreciate your help if we are doing something wrong.
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Questions from the Preliminary Presentation
How are you going to test the CPU before you build the CPU?
– We will present the portion of the test right now …
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