11-memory management and paging - Compatibility Mode · 40 Managing TLB: Process Initialization &...
Transcript of 11-memory management and paging - Compatibility Mode · 40 Managing TLB: Process Initialization &...
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Course Outline
Processes CPU Scheduling Synchronization & Deadlock Memory Management
File Systems & I/O Distributed Systems
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Today: Memory Management
Terminology Uniprogramming Multiprogramming
Contiguous memory allocation Fragmentation, compaction, swapping
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Memory Management
Where in memory is executing process? How do we allow multiple processes to share
main memory? What’s an address and how is one interpreted?
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Background:Computer Architecture
Executable program on disk OS loads program into memory CPU fetches instructions & data from
memory while executing program
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Where Do Addresses Come From?Instruction & data addresses Compile-time:
Exact physical location in memory starting from fixed position k
Load-time: OS determines process’s
starting position, fixes up addresses
Execution time: OS can place address
anywhere in physical memory
Used by most general-purpose OS
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Memory Management:Terminology
Segment: chunk of memory assigned to process
Physical address: real address in memory
Virtual address: address relative to start of process’s address space
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Uniprogramming
Only one program at a time: memory management is easy
OS gets fixed region of memory (e.g., highest) One process at a time
Load at address 0 Executes in contiguous memory
Compiler generates physical addresses Max address = memory size – OS size OS protected from process by checking addresses
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Example: Uniprogramming
Simple – but no overlap of I/O, computation
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Multiprogramming Requirements
Transparency No process aware memory is shared Process has no constraints on physical memory
Safety Processes cannot corrupt each other or OS
Efficiency Performance not degraded due to sharing
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Contiguous memory allocation
Put OS in high memory Process starts at 0
Max addr = memory size – OS size
Load process by allocating contiguous segment for process
Smallest addr = base, largest = limit
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Address Translation
Hardware adds relocation register (base) to virtual address to get physical address
Hardware compares address with limit register Test fails → trap
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Properties
Transparency Processes largely unaware of sharing
Safety Each memory reference checked
Efficiency Memory checks fast if done in hardware But: if process grows, may have to be moved
(SLOW)
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Pros & Cons
Advantages Simple, fast hardware
Two special registers, add & compare
Disadvantages Process limited to physical memory size Degree of multiprogramming limited
All memory of active processes must fit in memory
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Allocating “holes”
As processes enter system, grow & terminate, OS must track available and in-use memory
Can leave holes OS must decide where to put new processes
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Memory Allocation Policies
First-fit: Use first hole in which process fits
Best-fit: Use smallest hole that’s large enough
Worst-fit: Use largest hole
What’s best? First-fit and best-fit comparable, better than worst-fit in speed and memory utilization
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Fragmentation
Fragmentation = % memory unavailable for allocation, but not in use
External fragmentation: Large # of small holes s.t. even the total size satisfies a
request; no contiguous chunk can be found Caused by repeated unloading & loading
Internal fragmentation: Space inside process allocations
Unavailable to other processes
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Compaction
Can make space available by shuffling process space Eliminate holes Place free memory together Cannot move a process if addresses are
determined at compile or load time
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Compaction Example
Issues Amount of
memory moved Size of created
block Other choices?
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Alternative: Swapping
Swapping = copy process to disk, release all memory When process active, must reload Static relocation: same position(!) Dynamic relocation: ok
Drawback?
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Summary
Processes must reside in memory to execute Generally use virtual addresses
Translated to physical addresses before accessing memory
Contiguous memory allocation: Allows processes to share memory Pros and cons
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Paging
Motivation Page Tables Hardware Support Benefits
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Problems with Continuous memory allocation
Processes don’t (usually) use its entire space in memory all the time
Fragmentation problematic Compaction expensive
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Alternative: Paging
Divide logical memory into fixed-sized pages (4K, 8K)
Divide physical memory into fixed-sized frames Pages & frames same size OS manages pages
Moves, removes, reallocates Disk space: blocks same size as
frames Pages copied to and from disk
to frames
A
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Example: Page Layout
How does this help?
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Paging Advantages
Most programs obey 90/10 “rule” 90% of time spent
accessing 10% of memory
Exploiting this rule: Only keep “live” parts
of process in memory
A
B
AB
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Paging Advantages
“Hole-fitting problem” vanishes! Logical memory contiguous Physical memory not required to be
Eliminates external fragmentation But not internal (why not?)
But: Complicates address lookup...
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Example: Page Layout
So how do we resolve addresses?
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Paging
Motivation Page Tables Hardware Support
Benefits
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Paging Hardware
Processes use virtual addresses Addresses start at 0 or other known address OS lays process down on pages
MMU (memory-management unit): Hardware support for paging Translates virtual to physical addresses Uses page table to keep track of frame assigned
to memory page
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Paging Hardware: Diagram
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Paging Hardware: Intuition
Paging: form of dynamic relocation Virtual address bound by paging hardware to physical
address Page table: similar to a set of relocation registers Mapping – invisible to process
OS maintains mapping H/W does translation
Protection – provided by same mechanisms as in dynamic relocation
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Paging Hardware: Nitty-Gritty
Page size (= frame size): Typically power of 2 between 512 & 8192 bytes Linux, Windows: 4K; Solaris: 8K Support for larger page sizes varies (e.g., 128K)
Use of powers of 2 simplifies translation of virtual to physical addresses
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Address Translation
Powers of 2: Virtual address space:
size 2m
Page size 2n
High-order m-n bits of virtual address select page
Low order n bits select offset in page
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Address Translation: Example
Assume 1 byte addressing, each page contains 4 bytes: Length of p, d? Given virtual
address 0, 4, 10, 13, do virtual to physical translation
each entry uses 1 byte
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Making Paging Efficient
Where should the page table go? Registers:
Pros? Cons?
Memory: Pros? Cons?
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Translation Lookaside Buffer (TLB)
Small, fast-lookup hardware cache TLB sizes: 8 to 2048 entries
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TLB: Diagram
v = valid bit: entry is up-to-date
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Effectiveness of TLB
Processes exhibit locality of reference Temporal locality: processes tend to reference
same items repeatedly Spatial locality: processes tend to reference
items near each other (e.g., on same page) Locality in memory accesses →
locality in address translation
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Benefits from TLB
Example: Hit ratio: 0.8; on average: search TLB: 20 nanosec; search
memory: 100 nanosec What is the average cost to access/read an item
in memory? What if no TLB is used?
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Managing TLB:Process Initialization & Execution
Process arrives, needs k pages If k page frames free, allocate;
else free frames that are no longer needed OS:
puts pages in frames puts frame numbers into page table marks all TLB entries as invalid (flush) starts process loads TLB entries as pages are accessed,
replaces entries when full
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Managing TLB:Context Switches
Extend Process Control Block (PCB) with: Page table Copy of TLB (optional)
Context switch: Copy page table to PCB Copy TLB to PCB, Flush TLB (optional) Restore page table Restore TLB (optional)
Use multilevel paging if tables too big (see text)
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Paging
Motivation Page Tables Hardware Support Benefits
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Benefits: Compared to Contiguous-Memory Allocation
Eliminates external fragmentation (thus avoiding need for compaction)
Enables processes to run when only partially loaded in main memory
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Benefits: Allow Sharing
Paging allows sharing of memory across processes Shared pages –different virtual addresses,
point to same physical address Compiler marks “text” segment (i.e., code) of
applications (e.g., emacs) - read-only OS: keeps track of such segments
Reuses if another instance of app arrives Can greatly reduce memory requirements
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Paging Disadvantages
Paging: some costs Translating from virtual addresses to physical
addresses efficiently requires hardware support Larger TLB → more efficient, but more expensive
More complex operating system required to maintain page table
More expensive context switches (why?)
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Demand-Paged VM
Reading pages Writing pages
Swap space Page eviction Cost of paging Page replacement algorithms
Evaluation
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Demand-Paging Diagram
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Key Policy Decisions
Two key questions: When do we read page from disk? When do we write page to disk?
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Reading Pages
Read on-demand: OS loads page on its first reference May force an eviction of page in RAM Pause while loading page = page fault
Can also perform pre-paging: OS guesses which page will next be needed, and
begins loading it Advantages? Disadvantages?
Most systems just do demand paging
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Demand Paging
On every reference, check if page is in memory (valid bit in page table)
If not: trap to OS OS checks address validity, and
Selects victim page to be replaced Begins loading new page from disk Switches to other process (demand paging =
implicit I/O) Note: must restart instruction later
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Demand Paging, Continued
Interrupt signals page arrival, then: OS updates page table entry Continues faulting process
Stops current process
We could continue currently executing process – but why not?
And where does the victim page go?
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Demand Paging, Continued
Interrupt signals page arrival, then: OS updates page table entry Continues faulting process
Stops current process
We could continue currently executing process – but why not? Page just brought in could get paged out…
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Virtual Memory Locations
VM pages can now exist in one or more of following places: Physical memory (in RAM) Swap space (victim page) Filesystem (why?)
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Page Replacement
Process is given a fixed memory space of npages
Question: process requests a page page is not in memory, all n pages are used which page should be evicted from memory?
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Page Replacement: Cost of Paging
Worst-case analysis Easy to construct adversary example:
every page requires page fault Not much you can do, paging useless
A, B, C, D, E, F, G, H, I, J, A...
size of available memory
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Page Replacement: Cost of Paging, cont’d
But: processes exhibit locality,so performance generally not bad Temporal locality: processes tend to reference
same items repeatedly Spatial locality: processes tend to reference
items near each other (e.g., on same page)
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Metric: Effective Access Time
Let p = probability of page fault (0 ≤ p ≤ 1)ma = memory access time
Effective access time =(1 – p) * ma + p * page fault service time Memory access = 200ns, page fault = 25ms:
effective access time = (1-p)*200 + p*25,000,000
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Evaluating Page Replacement Algorithms
Average-case: Empirical studies – real application behavior
Theory: competitive analysis Can’t do better than optimal How far (in terms of faults) is algorithm from
optimal in worst-case? Competitive ratio
If algorithm can’t do worse than 2x optimal,it’s 2-competitive
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Page Replacement Algorithms
MIN, OPT (optimal) RANDOM
evict random page FIFO (first-in, first-out)
give every page equal residency LRU (least-recently used) MRU (most-recently used)
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MIN/OPT
Invented by Belady (“MIN”), now known as “OPT”: optimal page replacement Evict page to be accessed furthest in the future
Provably optimal policy Just one small problem...
Requires predicting the future Useful point of comparison
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MIN/OPT example
Page faults: 5
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RANDOM
Evict any page Works surprisingly well Theoretically: very good Not used in practice:
takes no advantage of locality
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LRU
Evict page that has not been used in longest time (least-recently used) Approximation of MIN if recent past is good
predictor of future A variant of LRU used in all real operating
systems Competitive ratio: n, (n: # of page frames)
Best possible for deterministic algs.
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LRU example
Page faults: ?
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LRU example
Page faults: 5
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LRU, example II
Page faults: ?
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LRU, example II
Page faults: 12
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FIFO
First-in, first-out: evict oldest page Also has competitive ratio n
But: performs miserably in practice! LRU takes advantage of locality FIFO does not
Suffers from Belady’s anomaly: More memory can mean more paging!
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FIFO & Belady’s Anomaly
Request sequenceA B C D A B E A B C D E Q1: # of page faults when n=3? Q2: # of page faults when n=4? Q3: what are the results under LRU?
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FIFO & Belady’s Anomaly
• When n=3, 9 page faults• When n=4, 10 page faults
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LRU: No Belady’s Anomaly
• When n=3, 10 page faults• When n=4, 8 page faults
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Why no anomaly for LRU?
“Stack” property: Pages in memory for memory size of n are also in
memory for memory size of n+1
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MRU
Evict most-recently used page Shines for LRU’s worst-case: loop that
exceeds RAM size
What we really want: adaptive algorithms(e.g., EELRU – Kaplan & Smaragdakis)
A, B, C, D, A, B, C, D, ...
size of available memory
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Summary
Reading pages Writing pages
Swap space Page eviction Cost of paging Page replacement algorithms
Evaluation