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2012-1480

(Reexamination No. 95/001,166)

___________________________________________

UNITED STATES COURT OF APPEALS

FOR THE FEDERAL CIRCUIT

___________________________________________

RAMBUS, INC.,Appellant

v.

DAVID J. KAPPOS, DIRECTOR,

UNITED STATES PATENT AND TRADEMARK OFFICE,Appellee.___________________________________________

Appeal from the United States Patent and Trademark Office,

Board of Patent Appeals and Interferences.

___________________________________________

BRIEF FOR APPELLEE DIRECTOR OF THE

UNITED STATES PATENT AND TRADEMARK OFFICE

RAYMOND T. CHEN

Solicitor

NATHAN K. KELLEY

Deputy Solicitor

COKE MORGAN STEWART

WILLIAM LAMARCA

Associate Solicitors

Office of the Solicitor

U.S. Patent and Trademark OfficeMail Stop 8, P.O. Box 1450

Alexandria, Virginia 22313-1450

571-272-9035

Attorneys for the Director of the

United States Patent and Trademark Office

November 29, 2012

Case: 12-1480 Document: 28 Page: 1 Filed: 11/29/2012

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Representative Claim

1. A method of controlling a memory device having a

memory core, wherein the method comprises:

providing control information to the memory device, wherein

the control information includes a first code which specifies that a

write operation be initiated in the memory device;

providing a signal to the memory device, wherein the signalindicates when the memory device is to begin sampling write data,

wherein the write data is stored in the memory core during the write

operation;

providing a first bit of the write data to the memory deviceduring an even phase of a clock signal; and

providing a second bit of the write data to the memory device

during an odd phase of the clock signal.

JA74-75.


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i

TABLE OF CONTENTS

I. STATEMENT OF THE ISSUE ........................................................................ 1

II. STATEMENT OF THE CASE ......................................................................... 2

III. STATEMENT OF THE FACTS ....................................................................... 3

A. DRAM Technology in General ................................................................... 3

B. The 109 Patent ............................................................................................ 4

C. The Prior Art: Farmwald (the 037 Patent).................................................. 6

D. The Boards Decision .................................................................................. 7

IV. SUMMARY OF THE ARGUMENT ................................................................ 10

V. ARGUMENT ..................................................................................................... 11

A. Standard of Review ...................................................................................... 11

B. A Reasonable Claim Construction and Substantial Evidence

Support the Rejection of Claims 1-25 for Anticipation .......................... 12

1. The Board Properly Construed the Term Signal ....................... 12

2. Rambuss Alleged Errors as to the Boards

Interpretation Have No Merit ........................................................ 13

a. The Term Signal is not Limited to a TransmissionThat Incites Immediate Action ........................................... 13

b. The Claimed Signal Does Not Have to be SentSeparate from or After the Write Command ...................... 14

c. The Delay Value Embodiment is not Unclaimed ........... 20

d. The 109 Patent Does Not Exclude theDelay Value Embodiment Simply Because


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the Parent Patent Includes It ............................................... 22

e. The Board Did Not Improperly Rely on a Dictionary

Definition of the Term Signal ......................................... 25

3. Substantial Evidence Supports the Boards Finding that

Farmwald Anticipates Claims 1-25 .............................................. 27

4. Rambuss Alleged Errors Regarding Anticipation Have NoMerit .............................................................................................. 29

a. Farmwalds Delay Value Is Not Used Before

the Write Operation ............................................................ 29

b. Farmwalds Delay Value is Flexible and Variable ......... 30

c. Substantial Evidence Supports the Boards Findings that

There are Four Possible Ways that Farmwalds Delay

Value Can Function as a Signal .................................... 33

d. Farmwalds Signal Originates Outside the MemoryDevice ............................................................................... 35

VI. CONCLUSION .................................................................................................. 40


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iii

TABLE OF AUTHORITIES

Cases

Alonso,In re, 545 F.3d 1015 (Fed. Cir. 2008) .........................................................25

Altiris, Inc. v. Symantec Corp., 318 F.3d 1363 (Fed. Cir. 2003) ...................... 19, 21

American Acad. of Sci. Tech Ctr.,In re, 367 F.3d l359 (Fed. Cir. 2004) ................12

Baldwin Graphic Sys., Inc. v. Siebert, Inc., 512 F.3d 1338 (Fed. Cir. 2008) ..........19

Baxter Travenol Labs., In re, 952 F.2d 388 (Fed. Cir. 1991). .................................11

Consol. Edison Co. v.NLRB, 305 U.S. 197 (1938) .................................................12

Dance,In re, 160 F.3d 1339 (Fed. Cir. 1998)..........................................................13

Gartside, In re, 203 F.3d 1305 (Fed. Cir. 2000) ......................................................11

Helmsderfer v. Bobrick Washroom Equip., Inc.,

527 F.3d 1379 (Fed. Cir. 2008) .....................................................................28

ICON Health & Fitness, Inc.,In re, 496 F.3d l374 (Fed. Cir. 2007) ......................12

Invitrogen Corp. v. Biocrest Mfg., L.P., 327 F.3d 1364 (Fed. Cir. 2003) ...............24

Jolley, In re, 308 F .3d 1317 (Fed. Cir. 2002) .........................................................12

Kotzab, In re, 217 F.3d 1365 (Fed. Cir. 2000) ........................................................11

Morris,In re, 127 F.3d 1048 (Fed. Cir. 1997) .........................................................13

Mantech Envtl. Corp. v. Hudson Envtl. Servs. Inc.,

152 F.3d 1368 (Fed. Cir. 1998) .....................................................................19


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iv

Oatey Co. v. IPS Corp., 514 F.3d 1271 (Fed. Cir. 2008) ........................................24

Para-Ordnance Mfg., Inc. v. SGS Imps. Intl, Inc.,

73 F.3d 1085 (Fed. Cir. 1995) .......................................................................11

Rolls-Royce, PLC v. United Technologies Corp.,

603 F.3d 1325 (Fed. Cir. 2010) .....................................................................24

Semitool, Inc. v Dynamic Micro Sys. Semiconductor Equip. GMBH,

444 F.3d 1337 (Fed. Cir. 2006) .....................................................................38

SRAM Corp. v. AD-II Engg,Inc., 465 F.3d 1351 (Fed. Cir. 2006) ........................18

Watts, In re, 354 F.3d 1362 (Fed. Cir. 2004) .............................................. 11, 25, 28

Statutes

35 U.S.C. 102(e) ..................................................................................................... 2

Other Authorities

Dictionary.com Unabridged (Random House, Inc.), ...............................................26

Merriam-Webster.com .............................................................................................26

Websters Third New Intl Dictionary (2002)..........................................................26


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v

STATEMENT OF RELATED CASES

No other appeal from the Board of Patent Appeals and Interferences (Board)

in connection with the patent on appeal has previously been before this or any

other court.

The Director is aware of other cases involving the patent on appeal that may

be directly affected by the Courts decision in this appeal, including: Rambus Inc.

v. LSI Corporation, No. 3:10-cv-05446 (N.D. Cal.),Rambus Inc. v.

STMicroelectronics NV, et al., No. 3:10-cv-05449 (N.D. Cal.), and Certain

Semiconductor Chips and Products Containing Same, Inv. No. 337-TA-753

(USITC).


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I. STATEMENT OF THE ISSUE

The 109 patent, owned by Rambus, broadly claims a method of storing

information in dynamic random access memory (DRAM). The claimed method

stores (writes) data to a memory device based on certain instructions.

Specifically, representative claim 1 requires (1) providing control information to

the memory device, wherein the control information includes a first code which

specifies that a write operation be initiated and (2) providing a signal to the

memory device, wherein the signal indicates when the memory device is to begin

sampling write data. The providing a signal element of claim 1 is the focus of

this appeal. In a lengthy specification, the 109 patent describes the provision of

the claimed signal in numerous embodiments, including one that discloses a delay

value that indicates to the DRAM when the data specified in the request packet

will begin to be sent.

Farmwald, a prior art patent also owned by Rambus, describes a method of

storing information in DRAM that mirrors the delay value embodiment in the

109 patent. Farmwald refers to the provision of its signal as outputting a value to

the memory device, wherein the value is representative of the delay time. The

Board found that Farmwalds delay value embodiment anticipates the 109 patents

claim 1, and therefore affirmed the Examiners rejections of all the claims on

appeal.


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2

The issue on appeal is whether the Board reasonably construed the

providing a signal element of claim 1 and whether substantial evidence supports

the Boards finding that Farmwald teaches that element, and therefore anticipates

claims 1-25 of the 109 patent under 35 U.S.C. 102(e).

II. STATEMENT OF THE CASE

The 109 patent, entitled Method of Controlling a Memory Device Having

a Memory Core, issued to Barth, et al., on October 23, 2007. JA31-76.1 It is the

tenth patent in a large and heavily litigated patent family addressing data storage

techniques.

On May 15, 2009, the United States Patent and Trademark Office (PTO)

granted a request by a third-party, NVIDIA, for reexamination of all 25 claims of

the 109 patent. On May 15, 2009, the Examiner rejected, inter alia, claims 1-25

as anticipated by Farmwald. On November 14, 2009, the Examiner issued an

action closing prosecution that, inter alia, finally rejected claims 1-25 as

anticipated by Farmwald. Following responses from Rambus and NVIDIA, on

February 26, 2010, the Examiner issued a right of appeal notice, maintaining the

rejection of claims 1-25 as anticipated by Farmwald. JA10975-11060. Rambus

appealed to the Board of Patent Appeals and Interferences (the Board), NVIDIA

responded, and the Examiner answered. JA13973-14008; JA15088-15106;

1Citations to Appellants Brief will be denoted as Br. _, and citations to the Joint

Appendix as JA_.


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JA15663-65; JA15682-15694. On May 4, 2011, the Board held an oral hearing.

JA17440-17480. On September 1, 2011, the Board affirmed the Examiners

rejection of claims 1-25 as anticipated by Farmwald. JA1-24. On October 3,

2011, Rambus submitted a request for rehearing. While that request was pending,

NVIDIA withdrew from the proceedings. On March 22, 2012, after considering

Rambuss rehearing request, the Board refused to alter its decision. JA17519-

17535. This appeal followed.

III. STATEMENT OF THE FACTS

A. DRAM Technology in General

This case concerns the way computers store information in memory. At a

fundamental level, a computer stores (writes) information in and retrieves

(reads) information from the computers memory. Br. 4. As part of the process,

the computer stores information in memory cells. JA33, Figs. 1A and 1B. To read

from and/or write to these memory cells, such read/write operations often involve a

memory controller and a processing device of a computer such as a central

processing unit (CPU). For example, the memory device can communicate with

the memory controller, which in turn can communicate with the CPU. The

communication path between the memory device and memory controller is called a

bus. See Br. 4; JA55, col. 4, ll. 8-26.


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B. The 109 Patent

The 109 patent broadly claims a method of controlling data transfers to and

from a memory device. Claim 1 is representative:

A method of controlling a memory device having a memory core,

wherein the method comprises:

providing control information to the memory device, wherein the

control information includes a first code which specifies that a write

operation be initiated in the memory device;

providing a signal to the memory device, wherein the signal

indicates when the memory device is to begin sampling write data,wherein the write data is stored in the memory core during the write

operation;

providing a first bit of the write data to the memory device during an

even phase of a clock signal; and

providing a second bit of the write data to the memory device during

an odd phase of the clock signal.

JA74-75 (emphasis added).2

Simply stated, the method of claim 1 tells the

memory device whatto do (write data) and whento do it (when the signal tells

it to). Per the claim language, an instruction to write data happens through

control information. Id. And the timing of when to write data is determined by

providing a signal. Id.

The 109 patents specification explains these elements in more detail. First,

it distinguishes the prior art systems, which it characterizes as inflexibly

2The last two elements of claim 1 are not at issue here.


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determining the timing ofa data transfer . . . by the timing of the request for the

data transfer. JA58, col. 10, ll. 27-28. In these prior art systems, a data transfer

request is sent and the transfer has to begin a predetermined number of clock

cycles after the request. JA58, col. 10, ll. 32-34. The inventors of the 109 patent

asserted that this renders prior art systems inflexible with respect to how control

and data signals may be interleaved to maximize the use of the transmission path.

JA58, col. 10, ll. 36-39.

In contrast, in the 109 patent, the timing of the request and the actual

transfer of data can vary. JA58, col. 10, ll. 44-51. The timing can be dictated by a

strobe signal, which occurs at various times depending on the transaction. Id.

Or the timing can be varied without the use of strobe and terminate signals.

JA58, col. 10, ll. 55-56, 64-67. In the non-strobe embodiment, timing is controlled

by the provision of a delay value, which tells the memory when the data

specified in the request packet will begin to be sent relative to the time at which the

request packet is sent. JA58, col. 10, ll. 57-60.

The 109 patent has been widely litigated by Rambus in at least seven causes

of action.3

3See Certain Semiconductor Chips Having Synchronous Dynamic Random Access

Memory Controllers and Products Containing the Same,Inv. No. 337-TA-661

(USITC); Certain Semiconductor Chips and Products Containing Same, Inv. No.

337-TA-753 (USITC); see also Rambus Inc. v. NVIDIACorporation, 3:08-cv-

03343-SI (N.D. Cal);Rambus Inc. v. LSI Corporation, No. 3:10-cv-05446 (N.D.


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JA17603, col. 6, ll. 40-45; see also JA17603,col. 6, ll. 46-48, 54-58; JA17605, col.

9, ll. 23-25; JA17605, col. 9, l. 64 to col. 10, l. 3; JA17606, col 11, ll. 27-47.

D. The Boards Decision

In a detailed 23-page decision, the Board affirmed the Examiners rejection

of all claims of the 109 patent as anticipated by Farmwald. The Board focused on

claim 1, which requires (1) providing control information to the memory device,

wherein the control information includes a first code which specifies that a write

operation be initiated and (2) providing a signal to the memory device, wherein

the signal indicates when the memory device is to begin sampling write data.4

The Board made findings as to which embodiments in the 109 patents

specification are encompassed by claim 1.

The Board found that the 109 patent describes at least two embodiments

for operating a DRAM, which the Board referred to as strobe and non-strobe

embodiments. JA3. The Board found that [i]n both embodiments, a memory

device (e.g., a DRAM) receives command control information causing it to begin a

process for reading data from, or writing data to, the memory core. JA3-4. The

Board further found that in the strobe embodiment, a strobe signal tells the

memory when to write information. JA4. In the non-strobe embodiment, a

delay value tells the memory when to write information. JA3, 5. The Board

4The Board also discussed claim 7. JA7. However, that claim has not been

separately argued on appeal.


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found that both embodiments allow the timing of the write operation to vary,

offering a level flexibility not found in the prior art. JA4-5. In the inflexible

prior art, the data transfer timing [is] based on a fixed number of clock cycles

after the clock cycle on which a request packet arrives. JA6.

With these findings in mind, the Board applied the prior art patent,

Farmwald, to claim 1. As to the first element of claim 1, providing a write

instruction via control information, the Board found that Farmwald discloses a

request packet that contains control data that in turn includes control

operations such as writing data. JA8. As to the second element of claim 1,

providing a signal to indicate when to start writing, the Board found that, in

Farmwald, the request packet controls the timing of the write operation either by

directly select[ing] a certain register in the slave DRAM memory device which

stores the (delay value) timing information or indirectly by indicat[ing] pre-

selected (delay value) access times. JA8. The Board further found, with respect

to the second element of claim 1, that Farmwalds claim 28 recites this feature:

outputting a value to the memory device, wherein the value is representative of

the delay time; and outputting a second operation to the memory device, wherein

the second operation code instructs the memory device to internally store the

value. JA8. In sum, the Board found that Farmwald discloses using request

packets which can vary the data block transfer time in [a] manner which is similar


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to the alternate (delay value/non-strobe) embodiment of the 109 patent (D3), to

determine when to read or write data from a memory device. JA7-8. For these

reasons, the Board affirmed the Examiners rejection of all claims of the 109

patent as anticipated by Farmwald.5

Rambus requested that the Board rehear its appeal because Rambus alleged

that the Board entered a new ground of rejection by relying on a different aspect of

Farmwald than the Examiner relied on to support its anticipation finding.

JA17483. While that request was pending, NVIDIA withdrew from the

proceedings. JA17513-15. After considering Rambuss request forrehearing, the

Board denied the request, stating that its initial decision tracks the Examiners

reliance on the delay value signal in Farmwald. JA17527. Rambus does not

appeal this aspect of the Boards decision, and thus no longer contends that the

Boards decision includes a new ground of rejection.

5The Board also reversed the Examiners non-statutory double-patenting

rejections. JA21-23. The Board further stated that its affirmance of the rejection

of all claims as anticipated by Farmwald renders it unnecessary to reach other

issues, such as the Examiners decision to refuse to adopt the Requestor NVIDIAsremaining proposed rejections. JA23.


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IV. SUMMARY OF THE ARGUMENT

Rambuss arguments boil down to a few key points. First, Rambus asserts

claim 1 must be given a narrow construction that requires that the signal

immediately incite a write operation. Second, Rambus asserts that the providing a

signal element of claim 1 must be given a narrow construction that requires that

the signal be sent separately from and subsequent to the write request. And,

third, Rambus asserts that claim 1 must be given a narrow construction that

excludes the alternate delay value embodiment found in its own specification.

Rambuss arguments fail, however, because claim 1 does not include any of these

limitations, and there is nothing in the specification that requires that they be read

into the claim. In fact, the terms signaland providing a signal are not defined

in the specification, but are simply used in an ordinary and customary way.

Without Rambuss extraordinarily narrow claim interpretation, which the

Board properly rejected, Rambus cannot avoid its own prior art patent, Farmwald.

Farmwald teaches a method of storing information in a memory device that not

only facially meets all of the elements of claim 1, but also precisely mirrors the

alternate delay value embodiment found in the 109 patent. Given the close

resemblance of Farmwald to the 109 patent, the Board properly affirmed the

Examiners rejection of the claims of the 109 patent based on anticipation.


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V. ARGUMENT

A. Standard of Review

Rambus has the burden to show that the Board committed reversible error.

In re Watts, 354 F.3d 1362, 1369 (Fed. Cir. 2004). Anticipation is a question of

fact. In re Baxter Travenol Labs., 952 F.2d 388, 390 (Fed. Cir. 1991). What a

reference teaches is a question of fact. Para-Ordnance Mfg., Inc. v. SGS Imps.

Intl, Inc., 73 F.3d 1085, 1088 (Fed. Cir. 1995).

This Court upholds the Boards factual findings unless those findings are not

supported by substantial evidence. In re Gartside, 203 F.3d 1305, 1316 (Fed. Cir.

2000). Substantial evidence is something less than the weight of the evidence but

more than a mere scintilla of evidence,In re Kotzab, 217 F.3d 1365, 1369 (Fed.

Cir. 2000), and means such relevant evidence as a reasonable mind might accept

as adequate to support a conclusion.Consol. Edison Co. v.NLRB, 305 U.S. 197,

229 (1938). Further, ifthe evidence in [the] record will support several

reasonable but contradictory conclusions, then this Court will not find the

Boards decision unsupported by substantial evidence simply because the Board

chose one conclusion over another plausible alternative. In re Jolley, 308 F.3d

1317, 1320 (Fed. Cir. 2002).

During reexamination, as with original examination, the [USPTO] must

give claims their broadest reasonable construction consistent with the


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specification. In re ICON Health & Fitness, Inc., 496 F.3d l374, 1379 (Fed. Cir.

2007) (citingIn re American Acad. of Sci. Tech Ctr., 367 F.3d l359, l364 (Fed. Cir.

2004)). This Court thus reviews the USPTOs interpretation of disputed claim

language to determine whether it is reasonable. In re Morris, 127 F.3d 1048,

1055 (Fed. Cir. 1997).

B. A Reasonable Claim Construction and Substantial Evidence

Support the Rejection of Claims 1-25 for Anticipation

1. The Board Properly Construed the Term Signal

Claim 1 requires providing a signal to the memory device, wherein the

signal indicates when the memory device is to begin sampling write data.6 JA74.

The Board reasonably construed the term signal to encompass various kinds of

indicators that tell the memory when to begin a write operation. Looking to the

specification for guidance, the Board found that the specification neither provided

a definition for signal nor a disclaimer precluding other generally understood

signals from being included in the patents claimed signal.Id. Rather, the Board

properly found that the patent uses the term signalbroadly, using signal and

information interchangeably when discussing similar operations of starting and

ending the reading, writing, or transmission of data. JA21. In addition,

referencing an IEEE dictionary definition, which Rambus itself had relied on in

6Rambus offers no separate argument regarding dependent claims 2-25.

Therefore, all of the claims stand or fall together with claim 1. In re Dance, 160

F.3d 1339, 1340 n.2 (Fed. Cir. 1998).


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other litigation and which NVIDIA pointed to as support for the plain meaning of

the term signal (see A15095 n.5), the Board found that the specifications broad

use of the term signal is consistent with the understood meaning of the term in the

relevant art, the physical representation of data. See JA10, 14, 21.

2. Rambuss Alleged Errors as to the Boards Interpretation

Have No Merit

a. The Term Signal is not Limited to a Transmission

That Incites Immediate Action

Rambus asserts that the term signal should be limited to a transmission

that incites action. Br. 21 (emphasis added). Rambus further argues that the

claimed signal must incite immediate action (i.e., start now). Br. 30, 34.

Rambuss argument conflicts with the plain language of the claim. Claim 1 simply

states that the signal indicates when the memory device is to begin storing data:


indicates when the memory device is to begin sampling write data,


operation;

JA74 (emphasis added). Claim 1 does not require that the write operation begin

after a particular amount of time after the signal, never mind immediately. If such

a limitation were meant to be included in claim 1, the drafter of claim 1, who

repeatedly used wherein to limit the claim, could have included it. Instead, there

is not even a suggestion of the limitation that Rambus argues applies.


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Without any support in the claim for the limitation, the specification would

have had to limit the claim language explicitly. As the Board noted, to limit the

meaning of a claim, the patentee must demonstrate[] a clear intention to limit the

claim scope using words of manifest exclusion or restriction. JA9. There are no

such words here. To the contrary, even in the so-called strobe signal

embodiment, cited by Rambus as the proper reading of claim 1, the read or write

operation does not immediately follow the signal, as there is some delay before the

write operation occurs. See, e.g., JA58, col. 9, ll. 37-51 (discussing the slight

delay between the strobe signal and the transmission of data). Similarly, the read

or write operation does not immediately terminate after a signal. JA58, col. 9, ll.

60-62 ([d]ue to intrinsic circuit delays, the DRAM does not instantly terminate

data transmission upon receipt of a terminate signal.).

b. The Claimed Signal Does Not Have to be Sent

Separately or After the Write Command

Rambus also argues that the claimed signal must be decoupled from the

write command, which it argues means that the signal must be sent separate from

and subsequent to the write command. See, e.g., Br. 21. While it is true that one

object of the invention (among many) is to provide a mechanism to decouple

control timing from data timing (JA55, col. 3, ll. 33-34), nothing in the claims

requires decoupling. Claim 1 does not recite the term decouple, nor does it

recite separate or subsequent to or otherwise require that the signal and write


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command be performed separately or in a certain order. Rather, claim 1 simply

recites a plurality of steps including providing control information to the memory

device and providing a signal to the memory device.

The only specific discussion of decoupling timing information occurs in a

briefsection of the specification called Decoupled Data Transfer Control

Information. JA58, col. 10, l. 25. This section addresses the specifications

delay value embodiment, which Rambus inexplicably asserts is not decoupled

(or even claimed in the 109 patent). As the brief discussion in this section of the

specification indicates, decoupling of timing information does not require that

various types of control information be sent separately; it merely requires that the

timing of the data control information be flexible so that the timing between the

request to begin a write operation and the actual data transmission vary. JA58, col.

10, ll. 25-67. What is also clear from this discussion in the specification is that

there are multiple ways in which the invention can be structured to be flexible over

the prior art, either by sending data transfer control information (timing

information) separately from the command control information (write instructions)

as described in the strobe signal embodiment orby using a variety of delay

values to vary the latency between the request packet (with the write instruction)

and the actual data transmission. Id.


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A discussion in the specification immediately following the decoupling

section sheds further light on the meaning of decoupling. There, the

specification provides:

As mentioned above, the fixed timing between requests and data

transmissions renders prior art systems inflexible with respect to how

control and datasignals may be interleaved. . . .

* * *

The ability to vary the timing between the transmission of a

request packet and the transmission of the data specified in the

command control information makes it possible to interleave the

information . . . in variations that were not previously possible.

JA59, col. 11, ll. 1-6, 22-26 (emphasis added). Thus, it is the fixed timing of the

prior art systems, not whether the control and data instructions are sent separately

from each other or in a particular order, that determines how flexible the system is.

Significantly, the specification here refers to control and data information as

signals. Id.

Regarding the separate from and subsequent to language from the

specification cited by Rambus as a requirement of claim 1, this is simply another

attempt by Rambus to import a limitation from the specification into the claim. In

discussing one strobe signal embodiment, the specification does state that data

transfer control information is sent separate from and subsequent to command

control information. JA57-58, col. 8, l. 63 to col. 9, l. 2. However, because data

transfer control information can be sent separate from and subsequent to


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command control information in one embodiment, does not mean that it mustbe.

That is, simply because a particular embodiment has the capability to send

information in a particular way does not mean that it is required by the claims.

Limitations from parts of the written description, such as details of an embodiment,

cannot be read into the claims absent a clear intention by the patentee to do so.

See, e.g.,SRAM Corp. v. AD-II Engg, Inc., 465 F.3d 1351, 1359 (Fed. Cir. 2006)

(holding it is error to narrow a claim by reading in a limitation). There is no clear

intention here.

Moreover, the mere fact that the providing a signal element is written after

the providing control information element in claim 1 does not mandate that the

elements be performed in that order. This Court has held that although a method

claim necessarily recites the steps of the method in a particular order, as a general

rule the claim is not limited to performance of the steps in the order recited, unless

the claim explicitly or implicitly requires a specific order. Baldwin Graphic Sys.,

Inc. v. Siebert, Inc., 512 F.3d 1338, 1345 (Fed. Cir. 2008); see also Altiris, Inc. v.

Symantec Corp., 318 F.3d 1363, 1371 (Fed. Cir. 2003) (holding that ordering in the

preferred embodiment cannot be imported into the claims when there is not any

statement that this order is important, any disclaimer of any other order of steps, or

any prosecution history indicating a surrender of any other order of steps.). Here,

the claim language does not require a specific order.


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Rambus citesMantech Envtl. Corp. v. Hudson Envtl. Servs. Inc., 152 F.3d

1368, 1376 (Fed. Cir. 1998) for the proposition that elements one and two of the

109 patent must be performed in order. However, inMantech, the order was

required for the claim to make sense; each step simply could not be performed

before the prior step had occurred. For example, inMantech, step 1 required wells

for monitoring groundwater. Id. at 1375-76. Step 2 required that acid be

introduced into the wells. Id. at 1376. Acid could not be introduced without the

wells first being provided. Step 3 introduced an aqueous solution of ferrous ion

into the already acidified groundwater.Id. The claimed solution could not be

provided to the acidified groundwater without the groundwater already having the

acid. Step 4 introduced a hydrogen peroxide solution into the groundwater that

undergoes a reaction in the presence of said acidic conditions and said ferrous

ion.Id. Obviously then, the hydrogen peroxide solution must be added after the

acid and the ferrous ion. As a result of this claim language, the Court inMantech

held that the sequential nature of the claim steps is apparent from the plain

meaning of the claim language. Id. Here, in contrast, the plain meaning of claim

1 does not require such ordering.

In fact, elements one and two of claim 1 are written in a fashion that actually

confounds ordering. They contain a first code without identifying a second code

and contain a write operation step that is clearly out of order:


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providing control information to the memory device, wherein

the control information includes afirst code which specifies that a

write operation be initiated in the memory device;


indicates when the memory device is to begin sampling write data,


operation;

A74 (claim 1).

In light of the lack of clarity regarding the ordering of elements one and two,

Rambus relies on elements three and four of claim 1 to imply an overall ordering

scheme. Br. 27-28. However, elements three and four clearly occur in order and

are written quite differently from elements one and two:

providing a first bit of the write data to the memory device

during an even phase of a clock signal; and

providing a second bit of the write data to the memory device

during an odd phase of the clock signal.

A74 (claim 1). In any event, this Court has held that the ordering of some steps

does not compel the ordering of others. See, e.g.,Altiris, 318 F.3d at 371 (holding

that certain steps were grammatically and logically required to be performed in

order while others were not). Thus, Rambus cannot successfully argue that the

claim language or specification requires that the write operation instruction

occur before the claimed signal that merely indicates when the operation is to

happen.


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c. The Delay Value Embodiment is not Unclaimed

Rambus argues that the term signal cannot be interpreted to include the

specifications delay value, and therefore that the delay value embodiment is

unclaimed. Br. 21-22. In support of this point, Rambus argues thatdecoupling

(which Rambus defines as the signal being sent separate from and subsequent to

the write command) represents the essence of the 109 patents advance, and that

the delay value embodiment of the specification is not decoupled. Br. 42. As

explained above, decoupling is not defined as the signal being sent separate from

and subsequent to the write command. Rather, decoupling refers to varying the

timing between the write command and the actual transfer of data. Thepatents

delay value embodiment varies this timing and is explicitly discussed in the only

section of the specification discussing decoupling. JA58, col. 10, ll. 25-67.

Thus, if the essence of the invention is decoupling, the delay value embodiment is

consistent with the essence of the invention, which supports the Boards reading of

the claims.

Rambus also argues that the alternate [delay value] embodiment is

described as operating without signals, and, therefore, since signals are

required by claim 1, the delay value embodiment cannot be encompassed by the

claims. Br. 22. The premise is incorrect. The delay value embodiment is

described as varying the timing of data transfer without the use ofstrobe or


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terminate signals, not without the use ofa signal generally. JA58, col. 10, ll.

55-56 (emphasis added).

Lastly, Rambus asserts that the delay value is only discussed in the

specification in terms of the prior art. Br. 45, 50. This argument makes no sense.

If the delay value embodiment were only in the prior art, it would not be explicitly

identified as an alternate embodiment. JA58, col. 10, ll. 52-56. Moreover, even

a cursory reading of column 10 of the patent, which discusses the prior art, shows

that the discussion of the delay value embodiment is completely separate from and

distinguished from the discussion of the prior art. The discussion of the prior art

identifies situations in which the timing of data transfer is dictated by the timing

of the request for data transfer by a predetermined value. Id., col. 10, ll. 27-39.

The delay value embodiment, by contrast, discloses how the controller may vary

the latency between the write request and the data transmission using a delay

value. Id., col. 10, ll. 52-67. Thus, while certain predetermined values might be

discussed as being used in the prior art, the particular variable delay value

discussed in the 109 patents alternate embodiment is not.

All that claim 1 requires of its signal is that it indicate to the memory

device when the memory device is to begin sampling write data. JA58 (claim 1).

The 109 patents delay value meets this limitation because it indicates when the

data will be sent to the memory device:


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In this embodiment, the [request] packet contains a delay value that

indicates to the DRAM when the data specified in the request packet

will begin to be sentrelative to the time at which the request packet is

sent.

JA58, col. 10, ll. 57-60 (emphasis added). Thus, by its plain language, the delay

value embodiment mirrors the language of claim 1, supporting the conclusion that

it is encompassed by the claims. Courts are reluctant to exclude an embodiment

unless, for example, [a] claim construction that embraced both alternative

embodiments would be unreasonable. Rolls-Royce, PLC v. United Technologies

Corp., 603 F.3d 1325, 1335 (Fed. Cir. 2010).7

Given the disclosures in the

specification, it is certainly not unreasonable to claim the delay value embodiment,

which explicitly tells the memory device when to begin sampling data just like the

claimed signal.

d. The 109 Patent Does Not Exclude the Delay Value

Embodiment Simply Because the Parent Patent

Includes It

For the first time on appeal, Rambus argues that because the parent of the

109 patentthe 914 patentexpressly claims the alternate delay value

7 See also Oatey Co. v. IPS Corp., 514 F.3d 1271, 1276 (Fed. Cir. 2008)(absent

disclaimer or estoppel, claims should normally be interpreted to include disclosed

embodiments); Verizon Servs. Corp. v. Vonage Holdings Corp., 503 F.3d 1295,1305 (Fed. Cir. 2007) (rejecting a proposed claim interpretation that would exclude

disclosed examples in the specification);Invitrogen Corp. v. Biocrest Mfg., L.P.,

327 F.3d 1364, 1369 (Fed. Cir. 2003) (finding the district courts claim

construction erroneously excluded an embodiment described in an example in the

specification, where the prosecution history showed no such disavowal of claim

scope).


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embodiment, the 109 patent clearly cannot. Br. 46; JA17615-17659 (914 patent).

This argument is waived and does not warrant any consideration because it was

never made to the Board. In re Watts, 354 F.3d at 1367 ([I]t is important that the

applicant challenging a decision not be permitted to raise arguments on appeal that

were not presented to the Board.); see also In re Alonso, 545 F.3d 1015, 1022

(Fed. Cir. 2008) (refusing to consider Appellants newly minted argument).

Nevertheless, even if Rambuss so-called claim differentiation argument

were to be considered, it fails on the merits. There is nothing precluding Rambus

from incorporating similar features into claimed inventions of different family

members in a patent tree. Some iteration of the delay value embodiment is

certainly encompassed by the claims of the 914 patent: [t]he method of claim 6

wherein the step of transmitting a start indicator is performed by transmitting a

delay value in the control information. JA17658 (claim 7). And some iteration of

the strobe signal embodiment is also encompassed by the claims of the 914 patent:

[t]he method of claim 6 wherein the step of transmitting a start indicator is

performed by transmitting a strobe signal a selected number of clock cycles after

transmitting the control information.Id. (claim 8). That does not mean that the

strobe signal and delay value embodiments in the specification are not claimed

by the 109 patent that recites abroader signal,not a strobe signal or delay

value. Were Rambuss argument as to the delay value correct, the claimed


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signal in the 109 patent could also not encompass any of the strobe signal

embodiments in the specification because they were already claimed in the 914

patent.

Moreover, as discussed above, by reciting the term signal, rather than

strobe signalor delay value, claim 1 of the 109 patent is broader than the

claims in the 914 patent that specifically recite strobe signal and delay value.

This supports an argument that the 109 patent, which only refers generally to

signals,includes, rather than excludes, the delay value embodiment.

In fact, rather than support Rambuss argument, the claim language in the

914 patent actually advances the Directors position. In the 914 patent, both a

strobe signal and a delay value are described as a start indicator. . . that

specifies when the data transfer opertation is to begin. JA17658 (claims 6-8)

(emphasis added). Given that the 914 parent patent describes its delay value as

a start indicator. . . that specifies when the data transfer operation is to begin,

and claim 1 recites a signal indicat[ing] when the memory device is to begin

sampling write data, Rambus is hard pressed to argue that the delay value is

encompassed by the 914 patents start indicator, but not also encompassed by

the 109 patents signal.

Accordingly, Rambuss claim differentiation argument, even if considered,

fails.


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e. The Board Did Not Improperly Rely on a Dictionary

Definition of the Term Signal

Finally, Rambus argues that the Board improperly began with the IEEE

dictionary definition of signal and essentially ignored the use of the term in the

specification, equating it with other generic terms such as code, data, and

value. Br. 38-39. This is a remarkable argument given the limited attention the

Board paid to the IEEE definition. See JA10, 14, 21. In any case, the Board did

not begin with a dictionary definition. Rather, the Board began by looking to the

language of the claims, then by making detailed findings regarding the use of the

term signal in the 109 patents specification, and then only referenced the

dictionary to show that the use of the term in the specification was consistent with

the meaning of the term in the art. Id. This Court has held, [w]hen the intrinsic

evidence is silent as to the plain meaning of a patent claim term, it is entirely

appropriate for the district court to look to dictionaries or other extrinsic sources

for context, and aid it in arriving at theplain meaning of a claim term.

Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1382 (Fed. Cir.

2008). It is equally appropriate for the Board to look at such an extrinsic source

when determining the meaning of a term.

For the first time on appeal, Rambus cites a lay dictionary, Websters Third

New Intl Dictionary 2401 (2002), to rebut the IEEE definition and to support its

narrow construction of signal as something that incites immediate action. Br.


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31; see also Br. 54 (citing Websters Third New Intl Dictionaryfor the term to).

This evidence was not before the Board and should not be raised here in the first

instance. In re Watts, 354 F.3d at 1367. However, even if one were to look at a

lay dictionary, one must consider other definitions it provides in the relevant

context of electrical engineering. Even the lay dictionaries recognize that signals

have a special meaning, i.e., an electronic impulse that transmits or conveys

information.8

As to Rambuss related argument that signal deserves a narrower

interpretation from other terms of claim 1 of the 109 patent, such as code,

data, and value, in light of the specification (Br. 21, 39-41), this is another

misreading of the Boards opinion. The Board did not equate signal with code,

data, and value, but it equated it with another term of art in the specification,

delay value. The Board found that a strobe signal and a delay value both

function as signals that indicate when a write operation is to take place.

In sum, Rambus has failed to demonstrate that the Board erred in its

construction of the term signal. The Board properly gave the claims their

8See, e.g., Merriam-Webster.com, http://www.merriam-webster.com/dictionary/ signal (last viewed Nov. 19. 2012) (a detectable physical quantity or

impulse . . . by which messages or information can be transmitted);Dictionary.com Unabridged (Random House, Inc.), http://dictionary. reference.

com/ browse/ signal (last viewed Nov. 19. 2012) (Electronics. an electrical

quantity or effect, as current, voltage, or electromagnetic waves, that can be varied

in such a way as to convey information.).


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broadest reasonable interpretation consistent with the specification. In re Bond,

910 F.2d 831, 833 (Fed. Cir. 1990) (quotingIn re Sneed, 710 F.2d 1544, 1548

(Fed. Cir. 1983)).

3. Substantial Evidence Supports the Boards Finding that

Farmwald Anticipates Claims 1-25

The Boards anticipation findings are supported by substantial evidence and

should be affirmed. As the Board found, and the Examiner enumerated in his

answer, Farmwald discloses each claimed element of the 109 patent. JA10-21.

As to the first element of claim 1, providing control information to the

memory device, wherein the control information includes a first code which

specifies that a write operation be initiated in the memory device, the Board found

that Farmwald discloses a request packet that contains control data that in turn

includes control operations such as writing data. JA8. This finding is supported

by the express teachings of Farmwald, which explicitly provide control

information that tells the memory device that it will be storing (writing) data.

JA17605, col. 9, ll. 32-57 (. . . a request packet 22 contains 6 bytes of data . . . .

The first byte contains two 4 bit fields containing control information . . . . The

AccessType field specifies whether the requested operation is a read or a write . . .

.) (emphasis added).

As to the second element of claim 1, providing a signal to the memory

device, wherein the signal indicates when the memory device is to begin sampling


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write data, the Board found that Farmwald discloses a request packet that controls

the timing of writing data either by directly select[ing] a certain register in the

slave DRAM memory device which stores the (delay value) timing information or

indirectly by indicat[ing] pre-selected (delay value) access times. JA8 (citing

col. 9, 1. 46 to col. 10, l. 5). Again, this finding is based on Farmwalds explicit

disclosure of a delay time indicating to the memory device when it is to begin

storing (writing) data. JA17605, col. 9, ll. 18-30 (The data block transfer occurs

later at a time specified in the request packet control information . . . . The time

after which a data block is driven onto the bus lines is selected from values stored

in the slave access-time registers.).

Further, as the Board noted, Farmwalds claim 28 recites outputting a

value to the memory device, wherein the value is representative of the delay time;

and outputting a second operation to the memory device, wherein the second

operation code instructs the memory device to internally store the value. JA8;

JA17614 (claims 25 and 28). Farmwalds claim 28 further demonstrates how

Farmwalds delay value operates in the same manner as claim 1.


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4. Rambuss Alleged Errors Regarding Anticipation

Have No Merit

a. Farmwalds Delay Value Is Not Used Before the

Write Operation

Rambus argues for a particular sequence of the steps in claim 1, that the

sequential nature of the claim steps that implement that method . . . is apparent

from the plain meaning of the claim language and its structure. Br. 26-27.

Rambus posits that with respect to the second and separate step of providing a

signal . . . .[,] [t]hat signal is distinct from the first code . . . and necessarily comes

after the first code. Br. 27. According to Rambus, Farmwald begins with

delay values and is different: it stores delay values that set the time for data

transfer relative to the devices receipt of the command control information. Br.

33.

As discussed, there is no requirement in the claim that the steps be

performed in a certain order. However, even if this were a requirement, substantial

evidence supports a finding that Farmwald provides a signal at least when the write

operation is requested, not before by statically storing a predetermined delay value.

Farmwald specifically says the slave device (e.g., a DRAM or memory

device) carries out requests sent by the master device (e.g., a CPU) at the

time requestedor specified by the master device:

The bus architecture of this invention connects master or bus

controller devices, such as CPUs, Direct Memory Access devices


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(DMAS) or Floating Point Units (FPUs), and slave devices, such as

DRAM, SRAM or ROM memory devices. A slave device responds to

control signals; a master sends control signals. . . .

* * *

All information sent between master devices and slave devices is sent

over the external bus . . . . This is accomplished by defining a protocol

whereby a master device, such as a microprocessor, seizes exclusive

control of the external bus (i.e., becomes the bus master) and initiates

a bus transaction by sending a request packet(a sequence of bytes

comprising address and control information) to one or more slave

devices on the bus. . . . The slave that the packet is directed to must

then begin any internal processes needed to carry out the requested

bus transactionat the requested time. The requesting mastermay alsoneed to transact certain internal processes before the bus transaction

begins.After a specified access time the slave(s) respond by returning

one or more bytes (8 bits) of data or by storing information made

available from the bus.

A17603-17604, col. 6, l. 19 to col. 7, l. 14. Therefore, the fact that certain delay

values are stored within the memory device, before an instruction (e.g., a write

operation) is sent, does not mean that the signal indicating when to begin the write

instruction is provided before the operation. When to do something is

determined by the master CPU, not by the DRAM or memory device, which is a

slave.

b. Farmwalds Delay Value is Flexible and Variable

Rambus argues that Farmwalds delay value system is inflexible and

therefore does not meet the limitations of claim 1. Br. 34-35. However, claim 1

does not recite or otherwise require flexibility or variability. Moreover, even


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if claim 1 of the 109 patent did require flexibility or variability, there is no

specific level of flexibility or variability required by the claim. Certainly, there is

no particular degree of flexibility or variability required by claim 1 that excludes

Farmwald.

In light of this, Rambus argues that the 109 specification expressly

distinguishes Farmwalds method as prior art. Id. This is simply incorrect. The

passage of the 109 specification cited by Rambus (JA58, col. 10, ll. 2539) is a

discussion of the prior art, it makes no mention of Farmwald, and is immediately

followed by a non-prior artdiscussion of an alternate embodiment of the 109

patents invention, which, as the Board found, mirrors Farmwald. JA58, 10:5267;

JA14-15.

Moreover, like the embodiments of the 109 patent, which are flexible

because, as stated, they can vary the amount of time (latency) between a request

packet and the corresponding data transmission, Farmwald allows the delay value

to be varied by the controller by providing multiple delay value choices. For

example, as the Board found, Farmwald demonstrates flexibility by sending a

request packet having a code for selecting different access-time registers each

storing a different delay value, by otherwise programming and storing different

values in such access-time registers, or by sending different operation codes

representing different delay values. JA16. This finding is supported by the


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explicit language of Farmwald, which states: In a preferred implementation,

semiconductor devices connected to the bus contain registers . . . which store a set

of one or moredelay times at which the device can or should be available to send

or receive data. JA17603, col. 6, ll. 40-45; see also JA17603, col. 6, ll. 54-55

(Each slave may have one or several access-time registers (four in a preferred

embodiment).); JA17604, col. 7, ll. 12-14 (More than one access time can be

provided to allow different types of responses to occur at different times.).

Given that Farmwald teaches multiple delay value choices, Rambus

alternatively argues that Farmwald is relatively inflexible in comparison the 109

patent. Rambus bases this argument on two points: (1) Farmwald does not teach a

decoupled write instruction and delay value, and (2) Farmwald has a confined set

of delay value choices determined by a limited number of access-time registers and

operation codes. Br. 49.

In response to Rambuss first point, the Director has already demonstrated

that claim 1 simply does not require the type of decoupling defined by Rambus.

Regarding Rambuss second point, as stated above, nothing in the claim 1 of the

109 patent requires a particular degree of variability of signal times, let alone the

narrow conception of variability asserted by Rambus. Rather, the patent

distinguishes prior art that is totally inflexible, i.e., art where the delay time is

predetermined and dictated by the timing of the request for the data transfer.


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JA58, col. 10, ll. 27-33. Here, Farmwalds ability to vary its delay time, shows

that it is not totally inflexible, and therefore it can fall within claim 1.

c. Substantial Evidence Supports the Boards Findings

That There are Four Ways that Farmwalds Delay

Value Can Function as a Signal

Rambus argues that the Board improperly advanced several unsupported

hypothetical delay value teachings of Farmwald to satisfy the providing a

signal step of claim 1. Br. 51. Contrary to Rambuss assertion, the Board did not

advance unsupported hypotheticals.

On page 12 of the Boards decision (JA13), the Board states that the delay

value itself can be found or accessed in four ways in Farmwald: in the request

packet, in the access-time register, when a comparison to the computer clock

happens, and/or when the delay value expires, i.e., the match of the expiration of

the delay value and the beginning of an operation. This should be uncontroversial

as a delay value is stored in an access-time register and then used by the master

and slave to determine when to initiate an operation.

On page 13 of the Boards decision (JA14), the Board specifically identifies

how Farmwald meets the providing a signal element of claim 1. The Board

found that skilled artisans reasonably would have considered . . . transmitting or

otherwise providing additional control information (i.e., additional to the first

code) within a request packet, such as the variable delay value signal as meeting


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the providing a signal element of claim 1. JA14. In other words, the Board held

that Farmwald provides a signal when the master device tells the slave memory

device in the request packet when to begin an operation: The data block transfer

occurs at a later time specified in the request packet control information.

JA17605, col. 9, ll. 18-19 (emphasis added). As discussed above, it is the master

that requestsand specifies what the memory does, and thus, as the Board

finds, transmits the timing signal. This is not a hypothetical and is supported by

substantial evidence.

In addition to its principal findingand undoubtedly in response to

Rambuss numerous asserted possible limitations on the claimthe Board also

found that, [a]lternatively, skilled artisans would have considered either 1) storing

the delay value in the access register, 2) retrieving it, or 3) comparing it to a clock

value and generating another implicit signal, as Farmwald provides, as also

constituting providing a signal, as recited in claim 1. JA14. The Boards

enumerated options were not unsupported hypotheticals, but were discussed and

substantiated throughout the Boards decision. See, e.g., JA12-13, JA7-9 (Findings

of Fact); see alsoJA17528-17529 (Decision on Request for Rehearing). By

referring to four options, the Board is simply reiterating, as discussed throughout

its decision, that depending how one defines providing a signal (e.g., inciting

immediate action or sent separate and apart from the write command as


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Rambus asserts) Farmwald meets those definitions. For example, Farmwalds

signal may be provided separately when it is programmed into the access time

register, separately when it is retrieved in response to a request packet, and/or

immediately when it is compared to the clock to determine that the delay time has

expired and that the write operation must commence. The Board cannot be

criticized for simply articulating how Farmwald meets the myriad possible

limitations that Rambus advances.

d. Farmwalds Signal Originates from Outside theMemory Device

Finally, Rambuss argues that claim 1 requires that the signal originate from

outside the memory device and that Farmwalds signal, as found by the Board,

allegedly does not. Br. 55-56. Again, Rambus attempts to read limitations from

the specific embodiments in the specification into the claims. But claim 1 does not

require that the signal originate from outside the memory device. It simply says

that the claimed signal is provided to the memory device. Thus, it is reasonable

to interpret the signal as being provided from outside the memory device or as

simply being provided from one component of the memory device to another.9

Indeed, Farmwald discloses both options.

9Rambus cites Semitool, Inc. v Dynamic Micro Sys. Semiconductor Equip. GMBH,

444 F.3d 1337, 1348 (Fed. Cir. 2006) for the proposition that if the claimed

signal is provided to the memory device, it must originate from outside the entirememory device. Br. 54. Semitool is distinguishable based on specific facts


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In Farmwald, the signal can come from outside the memory device by being

included in the request packet sent by the master device to the memory device:

The data block transfer occurs at a later timespecified in the request packet

control information. JA17605, col. 9, ll. 18-19 (emphasis added); see also

JA17604, col. 7, ll. 5-7 (The slave that the packet is directed to must then begin

any internal processes needed to carry out the requested bus transaction at the

requested time.) (emphasis added). The master device requests the time value,

then sends the request packet with the timing information to the memory device.

Indeed, it is the master device (located outside the memory device) that generally

controls all actions of the slave memory device. See, e.g., JA17603, col. 6, ll. 19-

24 (The bus architecture of this invention connects master or bus controller

devices, such as CPUs, Direct Memory Access devices (DMAS) or Floating Point

Units (FPUs), and slave devices, such as DRAM, SRAM or ROM memory

devices.A slave device responds to control signals; a master sends control

signals.).

Alternatively, the choice of the delay value can be determined by the

memory device itself. This approach is demonstrated by a discussion in Farmwald

relating to the architecture of a semiconductor wafer carrier cleaning system that

required an outside supply of drying gas to a process chamber. Semitool cannot

support a more general proposition that whenever a claim term says something is

provided to a device, be it a machine, hardware, or a software device, that theitem provided must originate from outside the device.


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that sets out both a direct (outside) option and an indirect (inside) option: The

choice of access-time register can be selected directly by having a certain op code

select that register, or indirectly by having a slave respond to selected op codes

with pre-selected access times (see table below). JA17605, col. 9, l. 66 to col. 10,

l. 3 (emphasis added). Thus, whether the claimed signal originates from outside

the memory device, as Rambus asserts, or inside the memory device, Farmwald

meets the limitation.

In sum, substantial evidence supports the Boards findings that Farmwald

provides the claimed signal, and therefore that claim 1 is anticipated.


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VI. CONCLUSION

Because the Boards decision is supported by substantial evidence and is in

accordance with the law, this Court should affirm.

Respectfully submitted,

/s/ Coke Morgan Stewart

RAYMOND T. CHEN

Solicitor

NATHAN K. KELLEY

Deputy Solicitor

COKE MORGAN STEWART

WILLIAM LAMARCA

Associate Solicitors


U.S. Patent and Trademark Office

Mail Stop 8, P.O. Box 1450

Alexandria, Virginia 22313-1450

571-272-9035

Attorneys for the Director of the

United States Patent and Trademark Office

November 29, 2012


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RULE 32(a)(7)(C) CERTIFICATE OF COMPLIANCE

I certify pursuant to FRAP 32(a)(7) that the foregoing brief complies with

the type volume limitation. The total number of words in the foregoing brief,

excluding the table of contents and table of authorities, is 8,871, as calculated by

Microsoft Word 2010 program.


Coke Morgan StewartOffice of the Solicitor


Mail Stop 8, P.O. Box 1450

Alexandria, VA 22313-1450

571-272-9035


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CERTIFICATE OF SERVICE

I hereby certify that on November 29, 2012, I electronically filed the

foregoing BRIEF FOR APPELLEE DIRECTOR OF THE UNITED STATES

PATENT AND TRADEMARK OFFICE with the Courts CM/ECF filing system,

which constitutes service, pursuant to Fed. R. App. P.25(c)(2), Fed. Cir. R. 25(a),

and the Courts Administrative Order Regarding Electronic Case Filing 6(A) (May

17, 2012).


Coke Morgan Stewart



Mail Stop 8, P.O. Box 1450Alexandria, VA 22313-1450

571-272-9035


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