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ideasdesign

Edited by Bill Travis

Modern microprocessor- or FP-GA-based circuits require separateand independent power-supply

voltages for the core and the I/O circuits.

Some devices require stringent control ofthe turn-on characteristics and sequenc-ing of these multiple power supplies toavoid internal parasitic current flows andconsequent latch-ups. Although regula-tors exist with specific soft-start andshutdown inputs, it may be more cost-ef-fective to use regulators that do not in-herently provide these features and toadd these features with external discretedevices. This Design Idea shows how touse an inexpensive Linear Technology(www.linear.com) LTC3701 dual switch-

ing regulator to provide a sequenced, and

standby-controlled, power supply for anEquator Technologies (www.equator.com) broadband-signal processor. Youcan also adjust the circuit for FPGA or

generic microprocessor applications.Thefeatures of the circuit in Figure 1 increasethe regulators stability beyond what youcan achieve with the standard LinearTechnology application-note circuit.

The LTC3701 switching regulator, IC1,

provides two independently adjustableoutput voltages with very high voltage ac-curacy at a cost compatible with con-sumer-type applications. Because of costconstraints, it does not provide the soft-start or shutdown features present in oth-er switching regulators. This design adds

three discrete transistors to the conven-

tional regulator circuitry to provide botharbitrary power-on-sequencing controland a simultaneous-shutdown feature.

Q3, Q4, and Q5 are inexpensive discrete

R475k

08050.1%

R1=37.4k = 1.20VVCORE.R1= 47.5k = 1.30VVCORE.R1= 66k = 1.50VVCORE.R1= 93.1k = 1.80VVCORE.R1= 160k = 2.50VVCORE.

VCORE

VCORE

KELVIN SENSING

161514

123

47

1156

8

SENSE 1

ITH/RUN

VFB1SGND

PLLLPF

PGOOD

VFB2ITH/RUN2

SENSE 2

SENSE 1+VIN

PGATE1

SENSE 2+

EXTCLK/MODE

PGND

PGATE2

13

12

10

9

KELVIN SENSING

LTC3701EGN

5VVIN

VIN5V

5

6

2

2

1

1

3

4

5VVIN

D2ONMBRS130T3

D1ONMBRS

320T3

+

+

C10220 F6.3V

C3220 F6.3V

C1580 pF0603

C422 F 10V

1210

C922 F10V

1210

C8580 pF0603

IC1C2

47 pF0603

C6

060347 pF

C7580 pF0603

C5

580 pF0603

L2

2.2 H2.3A IRMS

COILCRAFTDO1608C-222

COILCRAFTDO3316P-332

L13.3 H

5.4A IRMS

5

6

2

4

3

1

1

2

1%R8

232k0805

1%R1

37.4k0805

R70.015

R933k

R510k

PACK4

R610k

R310k

Q2FAIRCHILDFDC638P

Q42N3904-

SMD1

3

SLEEP

SLEEP

8 7 6 5

1 2 3 4

2

3

2

Q5BSN20

Q3BSN20

Q1FAIRCHILD

FDC638P

0.1%R1075k

0805

R20.015

3.3V1

F igure 1

Scheme adds sequencing andshutdown control to regulatorSaid Jackson, Equator Technologies Inc, Campbell, CA

Adding a few transistors to a switching regulator adds power-sequencing and shutdown control to a power supply.

Scheme adds sequencing and

shutdown control to regulator....................89

MathCAD functions perform

log interpolation ............................................90

Scheme improves on

ow-cost keyboard ..........................................94

ADC interface conditions

high-level signals............................................96

Two op amps provide

averaged absolute value..............................98

Publish your Design Idea in EDN. See theWhat s Up sect ion a t www.edn .com.

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ideasdesign

devices that control the voltageon the regulators I

TH/Run pins.

The ITH

/Run pins of IC1

pro-vide an external compensation

to the internal feedback loops;they can also serve to shutdown the device when you pullthem to ground. A micro-processors TTL/CMOS-com-patible input signal (Sleep)controls the power state of thecircuit. You can put the circuitinto shutdown mode by eitherletting the Sleep pin float highor pulling it higher than ap-proximately 1.5V. Q

3then con-

nects the ITH

/Run1 pin to

ground, which causes theVCORE

core-voltage supply toshut off.The V

COREvoltage then

drops toward ground, and Q4

stops conducting when VCORE

falls belowapproximately 0.8V. The gate of Q

5pulls

to the 5V unregulated input voltage, andQ

5shorts the I

TH/Run2 pin to ground,

which turns off the 3.3V regulator. Thecircuit is now in standby mode, and bothpower supplies are off.

Pulling the Sleep pin lower than ap-proximately 0.8V turns on the power

supply and sequences the voltages in thefollowing manner: Q

3stops conducting,

and the voltage on the ITH

/Run1 pin canrise, thanks to internal current sources inIC

1. The V

COREvoltage regulator then

starts to operate, and VCORE

rises to its setvoltage, 1.2V by default. Q

4starts con-

ducting as soon as VCORE

rises above ap-

proximately 0.8V. This action turns off Q5

and allows the ITH

/Run2 pin voltage tostart rising. The 3.3V power supply thusturns on.The combined effect of drivingQ

4and Q

5from the V

COREvoltage is that

the 3.3V I/O voltage always turns on onlyafter the V

COREvoltage attains an estab-

lished level. The end result is to sequencethe power supplies over a period of 4

msec (Figure 2).The circuit is symmetric, and changing

the base drive of Q4

and interchangingthe drain signals of Q

3and Q

5reverses the

sequencing order of the power suppliesfor chips that require the I/O voltage torise before the core voltage. You can ad-just the value of R

1to generate any core

voltage above approxi-mately 1V. You may needto adjust the value of R

9if

your design requires core

voltages below approxi-mately 1V.You can replaceQ

3and Q

5by potentially

cheaper industry-stan-dard 2N2007 devices atthe expense of slightlyhigher capacitive loadingon the I

TH/Run pins of

IC1. C

2and C

6are com-

pensation capacitors thatthe Linear Technology lit-erature does not mentionbut that are highly effec-

tive in preventing subhar-monic oscillation arisingfrom dynamic currentloading on the outputs.

(See the Linear Technology Web site forinformation on subharmonic oscilla-tion.)

The gate-drain-source capacitance ofQ

3and Q

5also add to the stability of the

loop filter.Note that sequencing the turn-on ramps of the power supplies also hasthe benefit of reducing the inrush currentinto the power supply by staggering this

current and preventing simultaneouscurrent loading of the primary bypass ca-pacitors by both power supplies. The se-lected component values allow for morethan 2A of current on the 3.3V line andmore than 3.5A of current on the V

CORE

line.

F igure 2

The 3.3V supply turns on several milliseconds after VCORE

attains an estab-

lished level.

1 500 mV/DIV 1.49V3 1V/DIV 75 mV 1 (1)=800 mV

2 (3)=5.880V=6.680V

349.96 SEC3.88004 mSEC4.23000 mSEC236.406 Hz1/X=

Y X

ACQUISITION IS STOPPED100k SAMPLES/SEC

MathCAD provides a number ofinterpolation and curve-fittingfunctions, so that, given a set of X-

Y data points, you can estimate the Y val-ue for any given X coordinate. Unfortu-nately, these functions work poorly withdata that is to be displayed in a nonlinear(logarithmic) manner. Examples of thesefunctions are: Log-Lin: phase/magnitude-versus-

frequency (Bode plots); Log-Log: impedance-versus-fre-

quency (reactance plots); and Lin-Log: impedance-versus-tem-

F igure 1

MathCAD functions perform log interpolationJames Bach, Delphi Delco Electronics Systems, Kokomo, IN

At X coordinates between data points, MathCADs linterp function creates abulging effect.

(continued on pg 94)

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perature (thermistor data).Using the built-in linterp function,

MathCAD estimates and plots the data(Figure 1). As you can see, at X coordi-

nates between the original data points,the linterpfunction creates a bulgingeffect. The following trio of simple in-terpolation functions allows the correctinterpolation of nonlinear data on its ap-propriate scale. These routines functionby prewarping the incoming-data matri-ces before feeding them into the ex-isting linterpfunction; for logarith-mic Y-axis functions, you raise 10 tothe result of the linterp function to re-store the values to the proper decade:

Using the newly created LogLogInterp

function, the straight-line data is displayed(Figure 2).

94 edn | O ctob er 30 , 2003 www.edn.com

ideasdesign

F igure 2 Using the LogLogInterp function, the bulges in Figure 1 disappear.

Y

ou can easily im-prove on a previous

Design Idea to pro-duce a slightly simpler re-sistor arrangement withbetter timing balance be-tween switches, using asingle resistor value(Reference 1, Figure 1).The use of a single resistorvalue, R

S, in a series chain

for the switch resistorsgives the timing parameters a simplerformat and should reduce bill-of-mate-

rials cost. The timing balance betweenswitches should now also be more even.

The improved balance eases

extending the keyboard foradding key inputs. The addi-tional benefit of this arrange-ment is to make the circuit eas-ier to adapt for faster or slowermicroprocessors, because youcan easily adapt the circuit bychanging the single switch re-sistor or capacitor values to al-ter the charge-discharge char-acteristics (Figure 2). It canalso make building the circuitinto a keypad housing easier,

especially if you use mem-brane keys. The entire circuit is

an SMD assembly with just two compo-nent types: switch and resistor. In theoriginal idea, in cases of multiple keys

being pressed, the timing is some oddmultiple of parallel resistors and couldaccidentally represent a key that was notselected. With the arrangement ofFig-ure 1, the lowest order key dominates;hence, the keypad has hard-wired pri-ority setting and always results in a se-lected key timing, and no intermediatetiming period should occur.

Reference

1. Thevenin, Jean-Jacques,Novel ideaimplements low-cost keyboard, EDN,

April 3, 2003, pg 69.

SX

1k1k 1k1k1kR11k

R2 R3 R4 R5 RX

S1 S2 S3 S4 S5

C147 nF

RC

100

MICROCONTROLLER

F igure 1

Scheme improves on low-cost keyboardMartin OHara, Telematica Systems Ltd, Cranfield, Bedfordshire, UK

This simple keypad arrangement uses a single resistor value to select the switches.

A 400-kHz square wave from the

microprocessor shows no key, key 1,and key 5 pressed.

F igure 2

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ideasdesign

The common mode input (top) measures 20V p-p. The common-mode

error of the differential output (middle) is 200 V p-p. The error of the

common-mode output (bottom) is 80 V p-p.

The topmost waveform is a 10V, com-mon-mode input signal. The middle

waveform, measuring 150 V, is the

common-mode error measured, differ-entially, from the output of the two

AD628s. The bottom waveform, meas-

uring 80 V, is the resultant common-mode error.

F igure 3

The circuit in Figure 1 has an 85-dBV SNR.

INPUT20V p-p

COMMON-MODE

ERROR OFDIFFERENTIALOUTPUT

COMMON-MODE

ERROR OFCOMMON-MODEOUTPUTF igure 4

The circuit in Figure 1 is usefulwhen you need amplitude demodu-lation or an averaged absolute-val-

ue conversion. The circuit comprises twostages, the first of which, IC

1A, is a dif-

ferential-output absolute-value convert-er. The second stage, IC

1B, is a tradition-

al differential amplifier. Thecombination of the two stages performssingle-ended absolute-value conversionbut only if R

3R

2. The C

1capacitors

integrate the current flow and yield av-eraged voltages V

Aand V

B. In addition,

the capacitors ensure low ac-impedancepoints at nodes V

Aand V

Bwhen the out-

put diodes are reverse-biased.The additional C

2capacitors in

parallel with R4

resistors impart a sec-ond-order-lowpass-filter characteristicto the circuit and remove the remainingac signal.From a practical point of view,you can choose R

3to be five to 10 times

higher than R2. The gain of the circuit is

(R2||R

3/R

1)(R

4/R

3). In most applications,

you would choose the filter time con-

stants 1R

2||R

3C

1and

2R

4C

2to be

equal. The circuit in Figure 1 is simple,symmetrical, and cost-effective. It alsomakes it easy to calculate and adjust the

gain using one resistor, R1. Other advan-

tages are that the circuit has equal delayfor positive- and negative-going signalsand that it doesnt need matcheddiodes.

IC1ATL082

IC1BTL082

C1470 nF

VIN

VOUT

R222k

R120k

R3220k

VA

VB

R4220k

R222k

R3220k

R4220k

C247 nF

C1470 nF

C247 nF

D1BAV99

+

__

+

Two op amps provide averaged absolute valueDobromir Dobrev, Jet Electronics, Sofia, Bulgaria

This single-ended, averaged absolute-value converter is useful for amplitude demodulation.

F igure 1