10 July 2003

Matthew Warren - Trigger Module Update 1

CALICE ‘FEDROB’ BE-FPGATrigger Module Update

Matthew Warren

University College London

10 July 2003

10 July 2003

Matthew Warren - Trigger Module Update 2

Trigger Logic Block Diagram (v3 - 25/6/2003)

4x PreTrigger

1x BeamOn

4x Activity

1x Veto

8x Trigger

Delayed Trig 1

Delayed Trig 8

‘Sequencer and Sink’Seq (8 bit) + Sink (24 bit) RAM

= 32KByte RAM

‘Digitiser’32bit Shift Registers, Storage

Registers (x9)

Edge Detect

Beam OnSync

+ Enable

6x Spare

1x Spare

SEQ

VME

VME

VetoSync

+ Enable

Pre-TriggerSync

+ Enables

InternalTrig Osc + Random +

Timer

ActivitySync

+ Enables 4x SR

SEQ

VME

4x SR

SEQ

VME

SR

VMEVME

TriggerWindow + Timer

VME

IRQ

IRQ

SEQ

VME

VME

Width/Delay

TriggerSync

IRQ

SINK

SINK

SINKVME

TriggerEnable,Latch,

Shaper,Veto

START

STOP

START

STOP

J2

EXTNIM

16 In

J0LVDS5 In

VME

VME

J0LVDS

2 Out

1x Trigger

1x Clock

3x Spare

J2

BPLVDS

8 Out

EXTNIM

16 Out

4x Trigger

1x Clock

VME

8 xCounter Delays(16 bit)

ClockControl

BE FPGA - Trigger Module

4x Spare

TTS_J0_READY

10 July 2003

Matthew Warren - Trigger Module Update 3

Trig skew test 0

All signal in Bank 6, fed from a common OR block.

10 July 2003

Matthew Warren - Trigger Module Update 4

Internal Schema ...

EN

Trigs In

delayin EN

progdelay

funcSEL

TrigTrig En On

Trig En OffTrig En

VME - Registers

10 July 2003

Matthew Warren - Trigger Module Update 5

More Thinking

- Async Latency Tests – requirements/procedures?- Actual functionality- Delays – sub-clock period needs/possibilities?- Integration with main BE-FPGA code?- Interface with Data RAM for easy readout- Register List- Names?

10 July 2003

Matthew Warren - Trigger Module Update 6

TimelineWeek Starting (Monday):14 July : UCL/HEP Stuff, CALICE Trigger Block Diag21 : Holiday28 : ATLAS (New TIM Arrives from manufacture/RAL)

4 Aug : ATLAS11 : ATLAS / CALICE – Async Trig test18 : CALICE – Main Functional Code 25 : CALICE – ditto 1 Sept : CALICE – Integration with BE-

FPGA 8 : CALICE / ATLAS 15 : ATLAS / As required22 : ATLAS / As required29 : As required …