1

Status of the V0 electronics

Tests of photomultipliers

Signal treatment Electronics Milestones

V0A

V0C

2

Photo-multiplier

from T0 R5505 R5946 R7761

Tube/cathode Ø/length32/20/6

525/17.5/4

038/27/50 39/27/50

Number of stages 15 15 16 19

HVmax 2500 2300 2300 2300

Gain2000 V at 0 T/0.5 T2/1.6 105 5/2.3 105 106/4.3 105 107/3 106

Rise/transit (ns) 1.5/6 1.5/5.6 1.9/7.2 2.6/7.5

Dark current (typ/max) (nA)

5/20 5/30 5/30 15/100

Pulse linearity (2%) (mA) ? 180 360 500

3

Charge, gain, time resolution

1916 19

16

15

Signal x 10 + 25 m cable

4

Pulse treatment

PM Anodesignal

50 ohms

50 ohms

50 ohms

G=5

G=5

Signal amplitude3 mV – 3 V

(5 mV – 5 V)

Signal amplitude3 mV – 3 V

(5 mV – 5 V)

Signal amplitude15 mV – 300 mV

(25 mV – 300 mV)

Signal amplitude75 mV – 1.5 V

(125 mV – 1.5 V)

To TRDwake-up

To V0 FEEthreshold disri.

To V0 FEEQDC

G=5

G=1

Signal charge0.6 pC - 600 pC(1 pC - 1000 pC)

shaper NINO (0.1 – 2 pC) 2 ns

OR

Signal charge15 pC - ~2500 pC

(25 pC - ~2500 pC)

Signal charge15 pC - ~2500 pC

(25 pC - ~2500 pC)

5

FEE data from V0C

V0ABBA (BBC)

BGA (BBC)BBA (BGC)

X 4 HPTDC (8 ch/chip)

dataL1 buff

buffer

data from V0A

L2

DAQ

L0

hit

ADC

ADC

NINO

NINO

THR

buffer

buffer

buffer

buffer

individual offsetcompensation

adjustable windows(step of 20 ps, range of 10 ns)

adjustable windows (.5 to 12 ns, step of .5 ns)

programmableintegration gate width

(from 3 ns to 36 ns, step of 3 ns)

+1 sum foreach ring

+

+

FPGA4

4

from V0C

1 sum for

each ring4

4from V0C

1 sum for

each ring4

4from V0C

programmable thresholds

BC

4

5 triggers, eg :- minimum bias- beam/gaz (right)- beam/gaz (left)- centrality- multiplicity

x 3

2 a

nodes

time

BB MB triggers

centrality triggers

THRcharge

THRmult

.

BGA BGC(V0C)

11 (3)+-

-

++

+BG MB triggers

multiplicity triggers

charge

6

Timing for BB and BG

C

C

C

A

A

A

7

Minimum-bias triggers Starting from the discriminator or the NINO signal BB signal detected in time windows centered at +11 ns (V0A) and +3 ns (V0C)

V0A

NINO

NINO

THR

buffer

buffer

adjustable windows(step of 20 ps, range of 10 ns)

adjustable windows (.5 to 12 ns, step of .5 ns)

BGA

BBA

+

+1 sum for

each ring4

1 sum for

each ring4

x 3

2 a

nodes

l t

BGC

BBC

+

+

-11 ns

+11 ns

V0C

-3 ns

+3 ns

A

C&

BB

BGCBGA BGA signal detected in time

windows centered at -11 ns (V0A) and +3 ns (V0C) BGC signal detected in time windows centered at +11 ns (V0A) and -3 ns (V0C)

bbc

bba

8

V0 mechanics milestones• Fall 2004: • End 2004: • March 2005: sector ‘0’ of V0A (Mexico) and V0C (Lyon) PRR submission• Fall 2005: V0C ready for commissioning,… PMT characterization (Lyon) (MIP from each channel,… noise, gain of each PMT)

• End 2005: V0A ready for commissioning,… PMT characterization (Mexico)

(MIP from each channel,… noise, gain of each PMT)• Spring 2006: • June 2006: V0C ready for installation in ALICE (array + fibre bundles + PMT mechanics)• End 2006: V0A ready for installation in ALICE (array + fibre bundles + PMT mechanics)

Responsibles: Mechanics: J.Y. Grossiord (Lyon), XXXX (Mexico)

9

V0 electronics milestones• Fall 2004: electronics concept finalization• End 2004: CIU design prototype test (charge, time, pre-process of

triggers)• March 2005: • Fall 2005: (final trigger signal, collection of the data, …interface TTC/FEE) CCIU and TTCIU design prototype test PRR submission• End 2005: CIU, CCIU, TTCIU electronic design, setting• Spring 2006: electronics design ready for realization• June 2006: electronics construction• End 2006: electronics test, calibration electronics ready for installation in ALICE

Responsibles: Electronics: Y. Zoccarato

10

V0 milestones• Fall 2004: electronics concept finalization• End 2004: CIU design prototype test • March 2005: sector ‘0’ of V0A (Mexico) and V0C (Lyon) PRR submission• Fall 2005: V0C ready for commissioning, PMT characterisation (Lyon) CCIU and TTCIU design prototype test PRR submission• End 2005: V0A ready for commissioning (Mexico) CIU, CCIU, TTCIU electronical scheme• Spring 2006: electronics design ready for realization• June 2006: V0C ready for installation in ALICE electronics construction• End 2006: V0A ready for installation in ALICE electronics test, calibration electronics ready for installation in ALICE

Responsibles: Electronics: Y. Zoccarato Mechanics: J.Y. Grossiord (Lyon), XXXX (Mexico)

11

V0 cost for 64 channels (R5946)

label unit spar

e unit price total pricePM R5946 64 - 1712 109568

HV SY2527/A1733P 1/6 -8812/292

9 26386VME 1 - 9000 9000

Electronics 64 2 70000Mechanics PM +

boxes 2 - 1000 2000Scint. V0A/V0C (m2) 2 x .6 - 1500 1500

WLS F. V0A/V0C (m) 2 x 346 - 3.3 2284

Clear F. V0A/V0C (m)

2 x 3456 - 1.0 6912

Total in € 227650Total in SF 341475

HV cab. V0A/V0C (m) 270 - 5.8 1566

HV con. V0A/V0C (448) - 4756Sig. cab. V0A/V0C

(m)2 x

1600 - 2.0 6400

Sig. con. V0A/V0C(2 x 576) - 11136

Total in SF 365333