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Transcript of 1 Sequential Logic Circuits Sunday, 20 July DIGITAL ELECTRONICS WORKSHOP Pn. Norina Idris, PPK...
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Sequential Logic CircuitsSequential Logic Circuits
Sunday, 20 JulySunday, 20 July
DIGITAL ELECTRONICS DIGITAL ELECTRONICS WORKSHOPWORKSHOP
Pn. Norina Idris, PPK Mikroelektronik, UniMAP
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““Combinational” vs Combinational” vs “Sequential”“Sequential”
Combinational – outputs depend only on Combinational – outputs depend only on the inputs.the inputs.– Do not have memory.Do not have memory.– Cannot store state.Cannot store state.
Sequential – outputs depend on inputs and Sequential – outputs depend on inputs and past behavior.past behavior.– Require use of storage elements.Require use of storage elements.– Contents of storage elements is called “state”.Contents of storage elements is called “state”.– Circuit goes through sequence of states as a Circuit goes through sequence of states as a
result of changes in inputs.result of changes in inputs.
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Overview of Sequential Overview of Sequential CircuitsCircuits
Storage Elements and AnalysisStorage Elements and Analysis
– Introduction to sequential circuitsIntroduction to sequential circuits– Types of sequential circuitsTypes of sequential circuits– Storage elementsStorage elements
LatchesLatches Flip-flopsFlip-flops
– Sequential circuit analysisSequential circuit analysis State tablesState tables State diagramsState diagrams
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Block Diagram of a Sequential Block Diagram of a Sequential CircuitCircuit
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Sequential Circuit - Basic Sequential Circuit - Basic FunctionFunction
The data stored in the “storage The data stored in the “storage elements” defines the “state” of the elements” defines the “state” of the sequential circuit at that time, i.e. sequential circuit at that time, i.e. present state.present state.
The The inputsinputs, together with the , together with the present present statestate of the storage elements, of the storage elements, determinedetermine the the outputsoutputs and the and the next next statestate of the storage elements. of the storage elements.
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Types of Sequential CircuitsTypes of Sequential Circuits Depends on the Depends on the timetimes at which:s at which:
– storage elements observe their inputs, and storage elements observe their inputs, and – storage elements change their state storage elements change their state
SynchronousSynchronous– Behavior defined from knowledge of its signals at Behavior defined from knowledge of its signals at discretediscrete
instances of timeinstances of time– Storage elements observe inputs and can change state only Storage elements observe inputs and can change state only
in relation to a timing signal (in relation to a timing signal (clock pulsesclock pulses from a from a clockclock)) AsynchronousAsynchronous
– Behavior defined from knowledge of inputs an any instant of Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs time and the order in continuous time in which inputs changechange
– If clock just regarded as another input, all circuits are If clock just regarded as another input, all circuits are asynchronous!asynchronous!
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Synchronous Clocked Synchronous Clocked Sequential CircuitSequential Circuit
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Simple Memory StructureSimple Memory Structure
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Another Structure for Another Structure for MemoryMemory
Reset
Set Q
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The Most Common Memory Elements The Most Common Memory Elements UsedUsed
Latches Latches
Flip-flops Flip-flops
– The basic single-bit memory elements, The basic single-bit memory elements, – With one or two inputs/outputs, With one or two inputs/outputs, – Designed using individual logic gates and Designed using individual logic gates and
feedback loops.feedback loops.– Both are referred to as “bistable Both are referred to as “bistable
elements” or “multivibrator”, i.e. having elements” or “multivibrator”, i.e. having two stable states.two stable states.
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Latches & Flip-flopsLatches & Flip-flops
Part IPart I
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Latch vs Flip-flopLatch vs Flip-flop
““The The inputsinputs, together with the , together with the present statepresent state of the storage of the storage elements, elements, determinedetermine the the outputsoutputs and the and the next statenext state of the of the storage elements.”storage elements.”
LatchLatch– Asynchronous. Asynchronous. – Change of stateChange of state can happen at can happen at any time,any time,
whenever whenever its inputs changeits inputs change. .
Flip-FlopsFlip-Flops– Synchronous.Synchronous.– Change of stateChange of state occurs only at occurs only at specific timesspecific times
determined by a determined by a clock pulse inputclock pulse input..– Flip-flops are constructed from latches!!Flip-flops are constructed from latches!!
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Types of Types of LatchesLatches
SR Latch S R Latch Gated D Latch
S Q
Q
C
R
Gated SR Latch (with control)
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S R LatchS R Latch
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SR Latch with NOR GatesSR Latch with NOR Gates
Reset
Set Q
Re-drawn …
Q
Q
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SR Latch Function TableSR Latch Function Table
Hold
Hold
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… … SR Latch OperationSR Latch Operation
If S=R=0 => the latch is either SET If S=R=0 => the latch is either SET or reSET..or reSET..
If S=R=1 => both Q and NQ = 0.If S=R=1 => both Q and NQ = 0.
– Undefined State!! … violation of Q vs Undefined State!! … violation of Q vs NQ.NQ.
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Simulation of SR Simulation of SR LatchLatch
.. with delay
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S-R Latch vs S-R LatchS-R Latch vs S-R Latch
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S R LatchS R Latch
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S R Latch with NAND GatesS R Latch with NAND Gates
Q
Q
Active-LOW SR Latch …
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SR Latch Function TableSR Latch Function Table
Hold
Hold
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S R Latch Function Table
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Assume that Q is initially LOW
1 3 4 5 6 72
S R Latch Waveform
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Gated SR Gated SR LatchLatch
= SR latch with Control input= SR latch with Control input
= SR latch with Enable input= SR latch with Enable input
= Clocked SR Latch= Clocked SR Latch
S Q
Q
C
R
C or Enable or CLock
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A gate input is added to the S-R latch to:
- Act as a “control” input.
- Make the latch synchronous.
Control=1 => Latch can change state
Control =0 => Latch “holds” previous
value
Gated S-R Latch - Basic Operation
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Gated SR Latch Function Gated SR Latch Function TableTable
Where is the additional circuit?
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R
C
Q
Q
S
1
0
1
0
1
0
1
0
1
0
Time
?
?
S Q
Q
C
R
Gated SR Latch SimulationGated SR Latch Simulation
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Gated D LatchGated D Latch
D Q
Q C
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Gated D LatchGated D Latch
Add inverter to the SR latch…
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Gated D Latch Function Gated D Latch Function TableTable
Note: There are no “indeterminate states” …
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Gated D Latch SimulationGated D Latch Simulation
t 1
t 2
t 3
t 4
Time
Clk
D
Q
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State Change in LatchState Change in Latch
Change in latch state => TriggerChange in latch state => Trigger
The D latch with clock pulses on its The D latch with clock pulses on its Control, C, input is triggered every Control, C, input is triggered every time a pulse to logic-1 level occurs.time a pulse to logic-1 level occurs.
As long as the pulse remains at the As long as the pulse remains at the logic-1 level, any changes in the data logic-1 level, any changes in the data input will change the state of the input will change the state of the latch.latch. “Level” triggered
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Edge-Triggered Flip-flopsEdge-Triggered Flip-flops
Flip-flops are Flip-flops are synchronoussynchronous bistable devices. bistable devices.
Synchronous: because the output changes Synchronous: because the output changes state ony at a certain point on a triggering state ony at a certain point on a triggering input, i.e. CLK, which is the control input.input, i.e. CLK, which is the control input.
Edge-triggered flip-flop: changes state at Edge-triggered flip-flop: changes state at either the either the positive edge positive edge (rising edge) or at (rising edge) or at the the negative edgenegative edge (falling edge) of the cock (falling edge) of the cock pulse.pulse.
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Clock Signals & Synchronous Sequential CircuitsClock Signals & Synchronous Sequential Circuits
A clock signal is a periodic square wave that A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals. at fixed intervals.
Rising edges of the clock
(Positive-edge triggered)
Falling edges
of the clock
(Negative-edge triggered)
Clock signal
Clock Cycle
Time
1
0
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Edge-triggered Flip-flop SymbolsEdge-triggered Flip-flop Symbols
Positive edge triggered and Negative edge-Positive edge triggered and Negative edge-triggeredtriggered
• All the above flip-flops have the triggering input called clock (CLK/C)
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Edge-Triggered Flip-flopsEdge-Triggered Flip-flops
SR flip-flopSR flip-flop
JK flip-flopJK flip-flop
D flip-flopD flip-flop
T flip-flopT flip-flop
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Timing DiagramTiming Diagram
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Negative-Edge Triggered D Flip-Negative-Edge Triggered D Flip-FlopFlop
The edge-triggered The edge-triggered D flip-flop is theD flip-flop is thesame as the master-same as the master-slave D flip-flop.slave D flip-flop.
It can be formed by:It can be formed by:– Replacing the first clocked S-R latch with a clocked D latch orReplacing the first clocked S-R latch with a clocked D latch or– Adding a D input and inverter to a master-slave S-R flip-flopAdding a D input and inverter to a master-slave S-R flip-flop
The delay of the S-R master-slave flip-flop can be The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present avoided since the 1s-catching behavior is not present with D replacing S and R inputswith D replacing S and R inputs
The change of the D flip-flop output is associated with The change of the D flip-flop output is associated with the negative edge at the end of the pulse.the negative edge at the end of the pulse.
It is called a It is called a negative-edge triggerednegative-edge triggered flip-flop flip-flop
C
S
R
Q
QC
Q
QC
D QD
Q
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Positive-Edge Triggered D Flip-FlopPositive-Edge Triggered D Flip-Flop Formed byFormed by
adding inverteradding inverterto clock inputto clock input
Q changes to the value on D applied at the positive Q changes to the value on D applied at the positive clock edge within timing constraints to be specified.clock edge within timing constraints to be specified.
The The standard flip-flopstandard flip-flop used for most sequential circuits. used for most sequential circuits.
C
S
R
Q
QC
Q
QC
D QD
Q
D Q
Q
Clock
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D
Clock
P4
P3
P1
P2
5
6
1
2
3
(a) Circuit
D Q
Q
(b) Graphical symbol
Clock
Q
Q
4
Positive-Edge-Triggered D Positive-Edge-Triggered D Flip-FlopFlip-Flop
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A positive edge-triggered D flip-flop formed A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverterwith an S-R flip-flop and an inverter
D CLK/C Q Q’_________________
1 ↑ 1 0 SET (stores a 1)
0 ↑ 0 1 RESET (stores a 0)
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Timing DiagramTiming Diagram
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Positive-Edge Triggered JK Flip-Positive-Edge Triggered JK Flip-FlopFlop
Not used Not used much much anymore in anymore in VLSIVLSI
AdvantageoAdvantageous only if us only if using FF using FF chipschips
D Q
Q
Q
Q
J
Clock
(a) Circuit
J Q
Q
K
01
Q t 1+ Q t 0
(b) Truth table (c) Graphical symbol
K
J
00
0 11
1 Q t 1K
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Function Table for JK Flip FlopFunction Table for JK Flip Flop
J K CLK Q Q’
0 0 Q0 Q0’ Hold
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q0’ Q0 Toggle (opposite state)
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Timing Diagram: Positive-Edge Timing Diagram: Positive-Edge Triggered Triggered
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Timing Diagram: Negative-Edge Timing Diagram: Negative-Edge Triggered Triggered
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D Q
Q
Q
Q T
Clock
(a) Circuit
T
0
1
Q t 1 +
Q t
Q t
(b) Truth table
T Q
Q
(c) Graphical symbol
T Flip-FlopT Flip-Flop Useful in countersUseful in counters Not available in IC formNot available in IC form T Latches do not existT Latches do not exist
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4949
T Flip-Flop T Flip-Flop
Clock
T
Q
(d) Timing diagram
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5050
D latch D latch vs vs
D flip-flopD flip-flop
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5151Comparison of level-sensitive and edge-triggered devices
D Q
Q
D Q
Q
D Q
Q
D
Clock Q a
Q b
Q c
Q c
Q b
Q a
(a) Circuit
Clk
(b) Timing diagram
D
Clock
Q a
Q b
Q c
D Latch versus D Flip-FlopD Latch versus D Flip-Flop
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5252
Standard Graphic Symbols for Standard Graphic Symbols for Latch and Flip-FlopsLatch and Flip-Flops
TT
Complete the list !!
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5353
Direct InputsDirect Inputs
Preset (Set) Preset (Set) & &
Clear (ReSet)Clear (ReSet)
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5454
D
Clock
(a) Circuit
Q
Q
Clear
Preset
Preset
Clear
(b) Graphical symbol
D Q
Q
Clear and Preset InputsClear and Preset InputsSet/Reset independent of clock
Direct set or presetDirect reset or clear
Often used for power-up reset
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5555
Example: D-FF with Direct Set and Example: D-FF with Direct Set and ResetReset
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5656
Direct InputsDirect Inputs At power up or at reset, all or partAt power up or at reset, all or part
of a sequential circuit usually isof a sequential circuit usually isinitialized to a known state beforeinitialized to a known state beforeit begins operationit begins operation
This initialization is often doneThis initialization is often doneoutside of the clocked behavioroutside of the clocked behaviorof the circuit, i.e., asynchronously.of the circuit, i.e., asynchronously.
Direct R and/or S inputs that control the state Direct R and/or S inputs that control the state of the latches within the flip-flops are used for of the latches within the flip-flops are used for this initialization. this initialization.
For the example flip-flop shown For the example flip-flop shown – 0 applied to R resets the flip-flop to the 0 state0 applied to R resets the flip-flop to the 0 state– 0 applied to S sets the flip-flop to the 1 state0 applied to S sets the flip-flop to the 1 state
D
C
S
R
Q
Q
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5757
J-K flip-flop with active-LOW J-K flip-flop with active-LOW Preset and Clear inputsPreset and Clear inputs
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5858
Timing DiagramTiming Diagram
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5959
State Diagram,State Diagram,
Function Table, Function Table,
Excitation Table,Excitation Table,
Characteristic EquationCharacteristic Equation
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6060
State DiagramsState Diagrams The sequential circuit function can be The sequential circuit function can be
represented in graphical form as a represented in graphical form as a state state diagramdiagram with the following components: with the following components:– A A circlecircle with the state name in it for each state with the state name in it for each state– A A directed arcdirected arc from the from the Present StatePresent State to the to the Next Next
StateState for each for each state transitionstate transition– A label on each A label on each directed arcdirected arc with the with the InputInput values values
which causes the which causes the state transitionstate transition, and, and– A label: A label:
On each On each circlecircle with the with the outputoutput value produced, value produced, oror
On each On each directed arcdirected arc with the with the outputoutput value value produced.produced.
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6161
State Diagram State Diagram ExampleExample
4- bit Binary Counter4- bit Binary Counter
Counts from Counts from
0000 (00000 (0HH) to 1111 (F) to 1111 (FHH))
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6262
Q
SR Latch SR Latch Detailed Detailed Function Function
TableTable
SS RR QQ Q+Q+
00 00 00 00
00 00 11 11
00 11 00 00
00 11 11 00
11 00 00 11
11 00 11 11
11 11 00 XX
11 11 11 XX
0000 0101 1111 1010
00 00 00 XX 1111 11 00 XX 11
SR
Excitation Excitation TableTable
QQ QQ++
SS RR
00 00 00 XX
00 11 11 00
11 00 00 11
11 11 XX 00Excitation Table: What are the necessary inputs to cause a particular kind of change in state?
State Transition Diagram:
The excitation table in graphical form
Characteristic Equation:Q+ = S + R’Q
0
1
SR0X
10
X0
01
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6363
Q
D Latch D Latch Detailed Detailed Function Function
TableTable
DD QQ Q+Q+
00 00 00
00 11 00
11 00 11
11 11 11
00 11
00 00 1111 00 11
D
Excitation Excitation TableTable
QQ Q+Q+ DD
00 00 00
00 11 11
11 00 00
11 11 11
Characteristic EquationQ+ = D
State Transition Diagram
0
1
0
1
1
0
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6464
Q
JK Flip-JK Flip-FlopFlop
Detailed Detailed Function Function
TableTable
JJ KK QQ Q+Q+
00 00 00 00
00 00 11 11
00 11 00 00
00 11 11 00
11 00 00 11
11 00 11 11
11 11 00 11
11 11 11 00
0000 0101 1111 1010
00 00 00 11 11
11 11 00 00 11
JK
Characteristic EquationCharacteristic Equation
Q+ = JQ’ + K’QQ+ = JQ’ + K’Q
Excitation Excitation TableTable
QQ Q+Q+ JJ KK
00 00 00 XX
00 11 11 XX
11 00 XX 11
11 11 XX 00State Transition
Diagram
0
1
JK0X
1X
X0
X1
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6565
Q
T Flip-FlopT Flip-Flop
Detailed Detailed Function Function
TableTable
TT QQ Q+Q+
00 00 00
00 11 11
11 00 11
11 11 00
00 11
00 00 1111 11 00
T
State Transition State Transition DiagramDiagram
Excitation Excitation TableTable
QQ Q+Q+ DD
00 00 00
00 11 11
11 00 11
11 11 00
Characteristic EquationQ+ = T’Q + TQ’ = T Q
0
1
0
1
0
1
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6666
Which Flip-flop to use Which Flip-flop to use ..?..?
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6767
Choosing a Flip-FlopChoosing a Flip-Flop SR Clocked Latch:SR Clocked Latch:
– used as storage element in narrow width clocked systemsused as storage element in narrow width clocked systems– its use is not recommended!its use is not recommended!– however, is the fundamental building block of other flip-flop however, is the fundamental building block of other flip-flop
typestypes D Flip-flop:D Flip-flop:
– minimizes wires, much preferred in VLSI technologiesminimizes wires, much preferred in VLSI technologies– simplest design techniquesimplest design technique– best choice for storage registersbest choice for storage registers
JK Flip-flop:JK Flip-flop:– versatile building block: can be used to implement D and T FFsversatile building block: can be used to implement D and T FFs– usually requires least amount of logic to control Q+usually requires least amount of logic to control Q+– however, has two inputs with increased wiring complexityhowever, has two inputs with increased wiring complexity
T Flip-flop:T Flip-flop:– doesn't really exist, constructed from J-K FFsdoesn't really exist, constructed from J-K FFs– usually best choice for implementing countersusually best choice for implementing counters
Preset and Clear inputs highly desirable!!Preset and Clear inputs highly desirable!!
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6868
Characteristic Equation & Excitation Table Summary
Device Device TypeType
Characteristic Characteristic EquationEquation
SR latchSR latch Q+ = S + R’QQ+ = S + R’Q
D latchD latch Q+ = DQ+ = D
JK flip-flopJK flip-flop Q+ = JQ’ + K’QQ+ = JQ’ + K’Q
T flip-flopT flip-flop Q+ = TQ’ + T’QQ+ = TQ’ + T’Q
QQ Q+Q+ SS RR DD JJ KK TT
00 00 00 XX 00 00 XX 00
00 11 11 00 11 11 XX 11
11 00 00 11 00 XX 11 11
11 11 XX 00 11 XX 00 00
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6969
Let’s Recap…Let’s Recap…
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7070
Standard Graphic Symbols for Standard Graphic Symbols for Latch and Flip-FlopsLatch and Flip-Flops
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7171
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7272
Flip-Flop Characteristic Flip-Flop Characteristic TableTable
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7373
Flip-Flop Excitation TablesFlip-Flop Excitation Tables
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7474
Flip-flop ApplicationsFlip-flop Applications
1.1. Parallel Data StorageParallel Data Storage2.2. Frequency DividerFrequency Divider3.3. CounterCounter4.4. Shift RegistersShift Registers
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7575
Parallel Data Storage –using Parallel Data Storage –using RegistersRegisters
4-bit REGISTER
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7676
Frequency Divider: Divide-by-2 Frequency Divider: Divide-by-2
Q is one-half the frequency of CLKQ is one-half the frequency of CLK
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7777
Frequency Divider: Divide-by-4Frequency Divider: Divide-by-4
2n
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7878
Counter : 00, 01, 10, 11Counter : 00, 01, 10, 11
2-bit Counter
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7979
Shift RegistersShift Registers
Part IIPart II
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8080
Basic shift register functionBasic shift register function Serial in / serial out shift registersSerial in / serial out shift registers Serial in / parallel out shift registersSerial in / parallel out shift registers Parallel in / serial out shift registersParallel in / serial out shift registers Parallel in / parallel out shift Parallel in / parallel out shift
registersregisters Bidirectional shift registersBidirectional shift registers Shift register applicationsShift register applications
Shift Registers TopicsShift Registers Topics
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8181
rEgIStERs…rEgIStERs…
What are they?What are they?
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8282
Registers … deFiniTioNRegisters … deFiniTioN
Registers – used for storing & Registers – used for storing & manipulating data.manipulating data.
– Register = DaftarRegister = Daftar– Shift Register = Daftar AnjakanShift Register = Daftar Anjakan
Loading (Pembebanan) – is the Loading (Pembebanan) – is the transfer of information into a transfer of information into a register.register.
– Load = BebanLoad = Beban
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8383
A register is a memory device that can A register is a memory device that can be used to store more than one-bit of be used to store more than one-bit of information.information.
A register is usually realized as several A register is usually realized as several flip-flops with common control signals flip-flops with common control signals that control the movement of data to that control the movement of data to and from the register.and from the register.
Registers.. deFiniTioNRegisters.. deFiniTioN
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8484
n-bit n-bit RegisterRegister
An n-bit register is a collection of An n-bit register is a collection of nn D D flip-flops with a common clock used to flip-flops with a common clock used to store store n n related bits.related bits.
D 1QCLR
Q
Q /1Q1D
D 2QCLR
Q
Q /2Q2D
D 3QCLR
Q
Q /3Q3D
D 4QCLR
Q
Q /4Q4D
CLK
/CLR
74LS175Example: 74LS175 4-bit register
CLKCLR
4Q4Q3Q3Q2Q2Q1Q1Q
74LS175
1D
2D
3D
4D
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8585
Shift Registers …?Shift Registers …?
A register capable of shifting its A register capable of shifting its stored data, in both directions.stored data, in both directions.
Consists of a chain of FFs in cascade.Consists of a chain of FFs in cascade.– The output of one FF goes into the input The output of one FF goes into the input
of the next FF.of the next FF. The shift from one stage to the next The shift from one stage to the next
is dependent on a common clock is dependent on a common clock pulse. pulse.
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8686
Serial output So
A 4-Bit Shift Register …A 4-Bit Shift Register …
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8787
… … 4-bit Shift Register4-bit Shift Register
SI, serial input, is the input to the SI, serial input, is the input to the leftmost FF during the shift.leftmost FF during the shift.
SO, serial output, is taken from the SO, serial output, is taken from the rightmost FF.rightmost FF.
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8888
Shift RegistersShift Registers
Multi-bit register that moves stored data bits left/right ( 1 bit Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)position per clock cycle)
0 1 1 1 LSI
Q3 Q2 Q1 Q0
1 1 1 LSI
Q3 Q2 Q1 Q0
RSI 0 1 1 1
Q3 Q2 Q1 Q0
RSI 0 1 1
Q3 Q2 Q1 Q0
– Shift Right (or Shift ?Up? ) is towards LSBShift Right (or Shift ?Up? ) is towards LSB
– Shift Left is towards MSBShift Left is towards MSB
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8989
Basic Shift Register FunctionsBasic Shift Register Functions
Consist of an arrangement of flip-flops Consist of an arrangement of flip-flops Important in applications involving Important in applications involving
storage and transfer of data (data storage and transfer of data (data movement) in digital systemmovement) in digital system
Used for storing and shifting data (1s Used for storing and shifting data (1s and 0s) entered into it from an and 0s) entered into it from an external source and possesses no external source and possesses no characteristic internal sequence of characteristic internal sequence of states.states.
D flip-flops are use to store and move D flip-flops are use to store and move datadata
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9090
The flip-flop as a storage elementThe flip-flop as a storage element
Still remember the truth table for D flip flop?
D CLK/C Q Q’_________________
1 ↑ 1 0 SET (stores a 1)
0 ↑ 0 1 RESET (stores a 0)
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9191
The flip-flop as a storage elementThe flip-flop as a storage element
When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state
When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state
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9292
Types of Shift RegisterTypes of Shift Register
1.1. Serial In / Serial Out Shift Registers (SISO)Serial In / Serial Out Shift Registers (SISO)2.2. Serial In /Parallel Out Shift Registers (SIPO)Serial In /Parallel Out Shift Registers (SIPO)3.3. Parallel In / Serial Out Shift Registers Parallel In / Serial Out Shift Registers
(PISO)(PISO)4.4. Parallel In / Parallel Out Shift Registers Parallel In / Parallel Out Shift Registers
(PIPO)(PIPO)
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Basic data movement in shift Basic data movement in shift registersregisters
(Four bits are used for illustration. The (Four bits are used for illustration. The bits move in the direction of the bits move in the direction of the
arrows.)arrows.)
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Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register(SISO)(SISO)
D Q
CLK
D Q
CLK
D Q
CLK
SERIN
CLOCK
SEROUT
For a n-bit SRG:Serial Out = Serial In delayed by n clock period
4-bit shift register example:serin: 1 0 1 1 0 0 1 1 1 0serout: - - - - 1 0 1 1 0 0clock:
SRG n>SI SO
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Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register(SISO)(SISO)
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Four bits (1010) being entered serially into the register.
1010
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Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register(SISO)(SISO)
FF0FF0 FF1FF1 FF2FF2 FF3FF3
CleaClearr
00 00 00 00
10110100
00 00 00 00
101101 00 00 00 00 00
1010 11 00 00 00 0000
11 00 11 00 00 000000
CleaClearr
11 00 11 00 00000000
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Four bits (1010) beingserially shifted out of the register and replaced by all zeros.
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Serial In, Parallel Out Shift registerSerial In, Parallel Out Shift register (SIPO)(SIPO)
D Q
CLK
D Q
CLK
D Q
CLK
SERIN
CLOCK
nQ
2Q
1Q
Serial to Parallel Converter
Example: 4-bit shift register serin: 1 0 1 1 0 0 1 1 1 01Q: - 1 0 1 1 0 0 1 1 12Q: - - 1 0 1 1 0 0 1 13Q: - - - 1 0 1 1 0 0 14Q: - - - - 1 0 1 1 0 0clock:
SRG n>SI 1Q
2Q
nQ (SO)
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Can u see the difference?Can u see the difference?
D Q
CLK
D Q
CLK
D Q
CLK
SERIN
CLOCK
nQ
2Q
1Q D Q
CLK
D Q
CLK
D Q
CLK
SERIN
CLOCK
SERIALOUT
PARALLELOUT
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Serial In, Parallel Out Shift register Serial In, Parallel Out Shift register (SIPO)(SIPO)
• Data bits entered serially (right-most bit first)
• Difference from SISO is the way data bits are taken
out of the register – in parallel.
• Output of each stage is available
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ExampleExample : :
The states of 4-bit register (SRG 4) for the The states of 4-bit register (SRG 4) for the data input and clocks waveforms. data input and clocks waveforms.
Assume the register initially contains all 1s
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4-bit parallel in/serial out shift 4-bit parallel in/serial out shift register (PISO)register (PISO)
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4-bit parallel in/serial out shift 4-bit parallel in/serial out shift register (PISO)register (PISO)
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Parallel In, Serial Out Shift Register Parallel In, Serial Out Shift Register (PISO)(PISO)
SERIN
CLOCK
D Q
CLK
D Q
CLK
D Q
CLK
SEROUT
LOAD/SHIFT
1D
2D
ND
S
L
S
L
S
L
1Q
2Q
NQ
Parallel to Serial Converter
Load/Shift=1 Di Qi
Load/Shift=0 Qi Qi+1
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Parallel In, Parallel Out Shift Register Parallel In, Parallel Out Shift Register (PIPO)(PIPO)
Immediately following simultaneous entry of all data bits, it appear on parallel output.
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Parallel In, Parallel Out Shift Register Parallel In, Parallel Out Shift Register (PIPO)(PIPO)
SERIN
CLOCK
D Q
CLK
D Q
CLK
D Q
CLK
LOAD/SHIFT
1D
2D
ND
1Q
2Q
NQ
S
L
S
L
S
L
General Purpose:Makes any kind of (left) shift register
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Bi-directional Shift RegistersBi-directional Shift Registers
Data can be shifted left AnD right Data can be shifted left AnD right ……
A parallel load may be possibleA parallel load may be possible
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Bi-directional Universal Shift RegistersBi-directional Universal Shift Registers
4-bit Bi-directional Universal (4-bit) PIPO
CLK CLR S1 S0
LIN D QDC QCB QBA QARIN
11
1
10
9
7
6
4
5
3
2
12
13
14
15
74x194Modes:HoldLoadShift RightShift Left
R L
Mode Next state
Function S1 S0 QA* QB* QC* QD*
Hold 0 0 QA QB QC QDShift right/up 0 1 RIN QA QB QCShift left/down 1 0 QB QC QD LINLoad 1 1 A B C D
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Shift Register Shift Register ApplicationsApplications
1.1. Counter – Johnson, RingCounter – Johnson, Ring2.2. State RegistersState Registers3.3. Serial Interconnection of Serial Interconnection of
SystemsSystems4.4. Bit Serial OperationsBit Serial Operations5.5. Time-delay DeviceTime-delay Device
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Four-bit Johnson countersFour-bit Johnson counters Serial output
connected back toserial input
The complement of the output (Q’) is fedback into
1st FF.
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A 10-bit ring counter A 10-bit ring counter Assume initial state : 0000000101
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More Shift Register ApplicationsMore Shift Register Applications
State RegistersState Registers– Shift registers are often used as the state Shift registers are often used as the state
register in a sequential device. Usually, the register in a sequential device. Usually, the next state is determined by shifting right next state is determined by shifting right and inserting a primary input or output into and inserting a primary input or output into the next position (i.e. a finite memory the next position (i.e. a finite memory machine)machine)
– Very effective for sequence detectorsVery effective for sequence detectors
Serial Interconnection of SystemsSerial Interconnection of Systems– keep interconnection cost low with serial keep interconnection cost low with serial
interconnectinterconnect
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More Shift Register ApplicationsMore Shift Register Applications
Bit Serial OperationsBit Serial Operations– Bit serial operations can be performed Bit serial operations can be performed
quickly through device iterationquickly through device iteration– Iteration (a purely combinational approach) Iteration (a purely combinational approach)
is expensive (in terms of # of transistors, is expensive (in terms of # of transistors, chip area, power, etc).chip area, power, etc).
– A sequential approach allows the reuse of A sequential approach allows the reuse of combinational functional units throughout combinational functional units throughout the multi-cycle operationthe multi-cycle operation
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More Shift Register Applications More Shift Register Applications Example:Example:
Serial Interconnection of SystemsSerial Interconnection of Systems
Serial DATAParallel-to-serial converter
Parallel Data from
A-to-D converter
Serial-to-parallel converter
Parallel Data to D-to-A converter
Control
Circuits
CLOCK
/SYNC
TransmitterControl
Circuits
Receiver
n nOne bit
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More Shift Register Applications More Shift Register Applications Example:Example:
The shift register as a time-delay deviceThe shift register as a time-delay device
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Part IIIPart III
CountersCounters
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Standard Graphic Symbols for Standard Graphic Symbols for Latch and Flip-FlopsLatch and Flip-Flops
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Flip-Flop Characteristic Flip-Flop Characteristic TableTable
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Flip-Flop Excitation TablesFlip-Flop Excitation Tables
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Counters - Definition Counters - Definition
A counter is:A counter is:
A register that “counts” through a A register that “counts” through a specific sequence of states upon the specific sequence of states upon the application of a sequence of input application of a sequence of input pulses e.g. clock or other signals.pulses e.g. clock or other signals.
Counters can count up, count down, or Counters can count up, count down, or count through other fixed sequences. count through other fixed sequences.
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Binary CounterBinary Counter
An n-bit binary counter:An n-bit binary counter:
– Consists of n flip-flops.Consists of n flip-flops.
– Counts from 0 to (2Counts from 0 to (2n n -1).-1).
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Two Counter Categories Two Counter Categories
1.1. Synchronous counterSynchronous counter
2.2. Ripple counters (Asynchronous Ripple counters (Asynchronous counter)counter)
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… … CountersCounters
1.1. Ripple Counters (Asynchronous Ripple Counters (Asynchronous Counters)Counters)
– FF output transition serves as a source FF output transition serves as a source for triggering other FFs.for triggering other FFs.
– C input not triggered by the common C input not triggered by the common clock pulse.clock pulse.
2.2. Synchronous CountersSynchronous Counters– C inputs of all FFs receive the common C inputs of all FFs receive the common
clock pulse.clock pulse.– The change of state is determined The change of state is determined
from the present state of the counter.from the present state of the counter.
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Counter ExamplesCounter Examples
Binary CounterBinary Counter Decade Counter/BCD CounterDecade Counter/BCD Counter Gray-Code CounterGray-Code Counter Modulus CounterModulus Counter Up-Down Counter Up-Down Counter Arbitrary Sequence CounterArbitrary Sequence Counter
Johnson CounterJohnson Counter Ring CounterRing Counter
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Synchronous Synchronous CountersCounters
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Synchronous CountersSynchronous Counters
The clk inputs of all flip-flops receive The clk inputs of all flip-flops receive a a commoncommon clock pulse clock pulse (directly (directly connected)connected)..
The change of state is determined The change of state is determined from the present state.from the present state.– By using combinational logic.By using combinational logic.
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4-bit Synchronous Binary 4-bit Synchronous Binary CounterCounter
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Johnson CounterJohnson Counter
The complement of the output of the last flip-The complement of the output of the last flip-flop is connected back to the input of the first flop is connected back to the input of the first flip-flop.flip-flop.
The counter will “fill up” with 1’s from left to The counter will “fill up” with 1’s from left to right, and then will “fill up” with 0’s againright, and then will “fill up” with 0’s again
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Figure 9–24Figure 9–24 Timing sequence for a 4-bit Johnson counter. Timing sequence for a 4-bit Johnson counter.
Convert the waveform results into table form.Convert the waveform results into table form.
Thomas L. FloydThomas L. FloydDigital Fundamentals, 9eDigital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Copyright ©2006 by Pearson Education, Inc.Inc.
Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458All rights reserved.All rights reserved.
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Ring CounterRing Counter
A “1” is always retained in the counter and simply shifted A “1” is always retained in the counter and simply shifted “around the ring”, advancing one stage for each clock pulse.“around the ring”, advancing one stage for each clock pulse.
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Output of 10-bit Ring Output of 10-bit Ring CounterCounter
Initial state is 1010 0000 00
Convert the waveform results into table form.Convert the waveform results into table form.
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Asynchronous Asynchronous CountersCounters
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Ripple Counters – clk SourceRipple Counters – clk Source
The clk inputs of some flip-flops are The clk inputs of some flip-flops are supplied by the outputs on other flip-supplied by the outputs on other flip-flops.flops.
– The (Master) CLOCK is connected to the clk The (Master) CLOCK is connected to the clk input on the LSB bit flip-flop.input on the LSB bit flip-flop.
– For all other bits, a flip-flop output is For all other bits, a flip-flop output is connected to the clock input, connected to the clock input,
– Thus, the circuit is Thus, the circuit is not synchronous.not synchronous.
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Ripple Counters – Pros & Ripple Counters – Pros & ConsCons
AdvantageAdvantage– Simple Hardware (Decoder gates not Simple Hardware (Decoder gates not
required).required).– Low power Low power consumption.consumption.
DisadvantageDisadvantage– SlowSlow– Output change is Output change is delayeddelayed more for each more for each
bit towards the MSB.bit towards the MSB.
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4-Bit Ripple Counter4-Bit Ripple Counter
Both J and K inputsof the flip-flops aretied to logic 1flip-flop complements
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5-45-4 Ripple CountersRipple Counters
Figure 5-8Figure 5-8 J and K of all FFs – tied together to J and K of all FFs – tied together to
logic 1logic 1 Negative edge triggered clock inputs.Negative edge triggered clock inputs. QQ00 serves as clock input to 2 serves as clock input to 2ndnd FF, FF,
and so on.and so on. N(Clear) – clears registers to 0 N(Clear) – clears registers to 0
asynchronously. asynchronously.
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SEQUENTIAL CIRCUITSSEQUENTIAL CIRCUITS
Design ExamplesDesign ExamplesUsing Flip-flopsUsing Flip-flops
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Example 1Example 1
InputInput: : x(t) x(t) Output:Output: y(t) y(t) State:State: (A(t), B(t)) (A(t), B(t)) What is the What is the Output Output
Function Function??
What is the What is the Next State Next State FunctionFunction??
AC
D Q
Q
C
D Q
Q
y
x A
B
CP
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Example 1Example 1 Boolean equations Boolean equations
for the functions: for the functions:– A(t+1) = A(t)x(t) A(t+1) = A(t)x(t)
+ B(t)x(t) + B(t)x(t)
– B(t+1) = B(t+1) = AA(t)x(t)(t)x(t)– y(t) = x(t)(B(t) + A(t))y(t) = x(t)(B(t) + A(t))
C
D Q
Q
C
D Q
Q'
y
xA
A
B
CP
Next State
Output
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State Table CharacteristicsState Table Characteristics State tableState table – a multiple variable table with – a multiple variable table with
the following four sections:the following four sections:– Present StatePresent State – the values of the state variables – the values of the state variables
for each allowed state.for each allowed state.– InputInput – the input combinations allowed. – the input combinations allowed.– Next-stateNext-state – the value of the state at time (t+1) – the value of the state at time (t+1)
based on the based on the present statepresent state and the and the inputinput..– OutputOutput – the value of the output as a function – the value of the output as a function
of the of the present statepresent state and (sometimes) the and (sometimes) the inputinput.. From the viewpoint of a truth table:From the viewpoint of a truth table:
– the inputs are Input, Present Statethe inputs are Input, Present State– and the outputs are Output, Next Stateand the outputs are Output, Next State
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Example 1: State TableExample 1: State Table
The state table can be filled in using the next The state table can be filled in using the next state and output equations: state and output equations: A(t+1) = A(t)x(t) + A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =B(t)x(t) B(t+1) =A (t)x(t) A (t)x(t) y(t) = y(t) =x (t)(B(t) + A(t))x (t)(B(t) + A(t))
Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0
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Example 2: Alternative State Example 2: Alternative State TableTable
2-dimensional table that matches well to a K-2-dimensional table that matches well to a K-map. Present state rows and input columns in map. Present state rows and input columns in Gray code order. Gray code order. – A(t+1) = A(t)x(t) + B(t)x(t)A(t+1) = A(t)x(t) + B(t)x(t)– B(t+1) =B(t+1) =A (t)x(t)A (t)x(t)– y(t) =y(t) =x (t)(B(t) + A(t))x (t)(B(t) + A(t))
Present State
Next State x(t)=0 x(t)=1
Output x(t)=0 x(t)=1
A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
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Design of Design of Synchronous Binary Synchronous Binary
CountersCounters
1.1. Using D flip-fops Using D flip-fops
2.2. Using JK flip-flopsUsing JK flip-flops
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Q
D Latch D Latch Detailed Detailed Function Function
TableTable
DD QQ Q+Q+
00 00 00
00 11 00
11 00 11
11 11 11
00 11
00 00 1111 00 11
D
Excitation Excitation TableTable
QQ Q+Q+ DD
00 00 00
00 11 11
11 00 00
11 11 11
Characteristic EquationQ+ = D
State Transition Diagram
0
1
0
1
1
0
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Counting Sequence of a 4-bit Counting Sequence of a 4-bit Binary CounterBinary Counter
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4-bit Binary Counter4-bit Binary Counter
Using D flip-flopUsing D flip-flop
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State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for Binary CounterBinary Counter
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What’s next? .. What’s next? ..
K-maps (4) K-maps (4)
Minimized Equations for:Minimized Equations for: D0D0 D1D1 D2D2 D3D3
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4-Bit Binary Counter with D Flip-4-Bit Binary Counter with D Flip-FlopsFlops
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4-bit Binary Counter4-bit Binary Counter
Using JK flip-flopUsing JK flip-flop
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State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for Binary CounterBinary Counter
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K-MapsK-Maps
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Count-Enable InputCount-Enable Input
To control the operation of counter, EN.To control the operation of counter, EN.JJQ0Q0 = K = KQ0Q0 = EN = EN
JJQ1Q1 = K = KQ1Q1 = Q = Q0 0 . EN. EN
JJQ2Q2 = K = KQ2Q2 = Q = Q00 . Q . Q1 1 . EN. EN
JJQ3Q3 = K = KQ3Q3 = Q = Q00 . Q . Q1 1 . Q. Q22 . EN . EN
EN = 0; all J and K inputs equal to 0, FFs- EN = 0; all J and K inputs equal to 0, FFs- no change.no change.
EN = 1; JEN = 1; JQ0Q0 = K = KQ0Q0 = 1, and the other = 1, and the other equations follow Fig. 5-9.equations follow Fig. 5-9.
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4-Bit Synchronous Binary Counter4-Bit Synchronous Binary Counter
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Binary Counter with Parallel Binary Counter with Parallel LoadLoad
Counters in digital systems, e.g. Counters in digital systems, e.g. computers, often require a parallel-computers, often require a parallel-load capability.load capability.– To transfer an initial binary number into To transfer an initial binary number into
the counter before the count operation.the counter before the count operation.– Load = 1; count operation disabled, data Load = 1; count operation disabled, data
transferred from the 4 parallel inputs transferred from the 4 parallel inputs into the 4 FFs.into the 4 FFs.
– Load = 0 and Count = 1; normal Load = 0 and Count = 1; normal operation. operation.
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4-Bit Binary Counter with Parallel 4-Bit Binary Counter with Parallel LoadLoad
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Up-Down Binary Up-Down Binary CounterCounter
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Synchronous Count Down Synchronous Count Down CounterCounter
Sequence (reverse):Sequence (reverse):– From 1111 to 0000 and back to 1111 to From 1111 to 0000 and back to 1111 to
repeat the count.repeat the count.
The logic diagram is similar to the The logic diagram is similar to the count-up counter, except that the count-up counter, except that the inputs to the AND gates must come inputs to the AND gates must come from the complement outputs of the from the complement outputs of the flip-flops.flip-flops.
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Synchronous Up-Down Synchronous Up-Down CounterCounter
Needs a mode input to select Needs a mode input to select between the two operations.between the two operations.– S=1: count upS=1: count up– S=0: count downS=0: count down
Also need a count enable input, EN:Also need a count enable input, EN:– EN=1; normal operation (up/down)EN=1; normal operation (up/down)– EN=0; disable both countsEN=0; disable both counts
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4-bit BCD Counter4-bit BCD Counter
Using T flip-flopUsing T flip-flop
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State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for BCD CounterBCD Counter
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The scHeMatiCThe scHeMatiC
Draw the K-maps and get the Draw the K-maps and get the minimized equations. minimized equations.
.. Draw with four T flip-flops, four .. Draw with four T flip-flops, four AND gates and one Or gate.AND gates and one Or gate.
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ExerciseExercise
Design a 4-bit Gray Code Counter Design a 4-bit Gray Code Counter using D flip-flopsusing D flip-flops
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Arbitrary Sequence Arbitrary Sequence CounterCounter
Using JK flip-flopUsing JK flip-flop
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Counter with Arbitrary CountCounter with Arbitrary Count
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State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for CounterCounter
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Additional BOOK Additional BOOK slides slides
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Comparison of 4-bit modulus Comparison of 4-bit modulus 16 and modulus 10 16 and modulus 10
Modulus 16
Modulus 10
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Timing diagramTiming diagram
Modulus 16
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Q0
Q1
Q2
Q3
For For modulus 10modulus 10, pay , pay attention at clock 9 , and 10 attention at clock 9 , and 10 of modulus 16of modulus 16
At At clock 9clock 9, Q3..Q0 o/p = , Q3..Q0 o/p = 10011001 ( in decimal = 9) ( in decimal = 9)
For For modulus 16modulus 16– At At clock 10clock 10, Q3..Q0 o/p = 1010 , Q3..Q0 o/p = 1010
( in decimal = 10).( in decimal = 10).– Here Q3 = 1, Q1 = 1Here Q3 = 1, Q1 = 1
For For modulus 10modulus 10– Q3 AND Q1 Q3 AND Q1 connected byconnected by
NAND NAND gate.gate.– Means when Q1 =1 AND Q3 = Means when Q1 =1 AND Q3 =
1, o/p of NAND = 0 1, o/p of NAND = 0 – Happened at Happened at clock 10clock 10, Q1 = 1 , Q1 = 1
AND Q3 = 1AND Q3 = 1
Taken from modulus 16 o/p
Q1
Q3
CLR
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CLR
FF0 FF1 FF2 FF3
Here the o/p of NAND gate will Here the o/p of NAND gate will fed into ACTIVE LOW input of CLR.fed into ACTIVE LOW input of CLR.
Since NAND o/p =0, the Flip-flop Since NAND o/p =0, the Flip-flop will be will be CLEAREDCLEARED..
This introduce glitch in the This introduce glitch in the modulus 10 o/p.modulus 10 o/p.– Data transmission as described above Data transmission as described above
only happens in a very short timeonly happens in a very short time glitch. glitch.
– Data being cleared at Data being cleared at clock 10clock 10
CLR
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eXerCisE quEstioNseXerCisE quEstioNs
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Design these Sequential Design these Sequential Counters…Counters…
3-bit Up-Counter3-bit Up-Counter
Arbitrary Sequence Counter: 000, Arbitrary Sequence Counter: 000, 010,011,101,110, 000, ...010,011,101,110, 000, ...
3-bit Gray Code Counter3-bit Gray Code Counter
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Design these Sequential Design these Sequential Counters ..Counters ..
4-bit Up-Counter4-bit Up-Counter
Modulus-10 CounterModulus-10 Counter
Arbitrary Sequence Counter: 0, 2, 4, Arbitrary Sequence Counter: 0, 2, 4, 6, 8, 10, 12, 14, 0, … (in decimal)6, 8, 10, 12, 14, 0, … (in decimal)