1 Register Transfer Level & Design with ASM Logic and Digital System Design - CS 303 Erkay Savaş...
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1 Register Transfer Level & Design with ASM Logic and Digital System Design - CS 303 Erkay Savaş Sabancı University
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Transcript of 1 Register Transfer Level & Design with ASM Logic and Digital System Design - CS 303 Erkay Savaş...
1
Register Transfer Level&
Design with ASM
Logic and Digital System Design - CS 303Erkay Savaş
Sabancı University
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Overview• Register transfer level (RTL) to model complex
digital systems– a level of abstraction used in describing the
operation of a synchronous digital circuits
– a circuit's behavior is defined in terms of the transfer of data between hardware registers, and the operations performed on data.
• Goal: Algorithmic expression of a digital system
• Algorithmic State Machine (ASM) charts – to model complex digital systems
– to map a complex design into hardware
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Register Transfer Level
• Designing a complex digital system using state tables becomes difficult as the number of states increases
• Remedy– partition the system into modular subsystems– each module is designed separately– modules are connected to each other
• A digital module is best defined by1. set of registers2. operations on the binary information stored in
them
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Register Transfer Level
• Register operations– move, copy, shift, count, clear, load, add,
subtract
• A digital system is said to be represented at the register transfer level (RTL) when it is specified by the following three components
1. Set of registers2. Operations performed on the data stored in
the registers3. The control supervises the sequence of
operations in the system
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The Control • Control logic
– Initiates the sequence of operations – generates timing (control) signals that sequence
the operations in prescribed manner• The outputs of control logic are binary signals
that initiate the various operations in registers– Certain conditions that depend on the previous
operations may determine the sequence of future operations
• Transfer statement– R2 R1 (“replacement” operation)
• Conditional transfer statement– if (T1 = 1) then R2 R1 – T1 is a control signal
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Register Transfer Operations• In register transfer operations, clock is not
explicitly shown– but, transfer is assumed to happen at the clock edge.– previous example
•if (T1 = 1) then R2 R1
•T1 may become 1 before the clock edge, but actual transfer happens exactly at the clock edge.
• Examples:– if (T3 = 1) then (R2 R1, R1 R2)
– R1 R1 + R2
– R3 R3 + 1
– R4 shr R4
– R5 0
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Types of Register Operations
• Four categories1. transfer operations2. arithmetic operations3. logic operations4. shift operations
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Datapath and Control
• One obvious distinction1. design of datapath (data processing path)2. design of control circuit
Control Unit
Datapath
Control signals
Status signalsControlinputs
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Hardware Algorithm & ASM Chart
• (Digital) hardware algorithm– is a procedure for implementing a digital circuit with
given pieces of hardware equipments
– specifies the control sequence and datapath tasks
• Algorithmic state machine (ASM) chart is a special type of flowchart used to define digital hardware algorithms.– state machine is another term for a sequential
circuit
• ASM chart describes – the sequence of events,
– events that occur at state transitions.
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ASM Chart
• Three basic elements1. State box2. Decision box3. Conditional box
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State Box
• The output signals (e.g., START) in the box take the specified values in the current state– if not specified in other states they are 0.
• The notation R 0 means that the register is cleared to 0 when the system transits from A to the next state
name state assignment
STARTR 0
A 1011
State Box
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Control
START
RRESET_R
name state assignment
STARTR 0
A 1011
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Decision Box
• Decision box has two or more branches going out.• Decision is made based on the value of one or more
input signals (e.g., signal J)• Decision box must follow and be associated with a
state box.• Thus, the decision is made in the same clock cycle as
the other actions of the state.
J0
1
Decision Box
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J0
1
Control Unit
Datapath
Control signals
Status signalsControlinputs
Control
START
RRESET_RJ
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Conditional Box
• A conditional box must follow a decision box.• A conditional box is attached to a state box
through one or more decision boxes.• Therefore, the output signals in the conditional output
box are asserted in the same clock cycle as those inthe state box to which it is attached.
• The output signals can change during the current state as aresult of changes on the inputs.
• The conditional output signals are sometimes referredas Mealy outputs since they depend on the input signalsas well.
Register operationor output
Conditional Box
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ControlSTART
RRESET_R
Register operationor output
J
START
RESET_R
J0
1
STARTR 0
ENABLE
S0
ENABLE
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Example: Traffic Control
Major road
Minor roadsensor
major=Gminor=R
car/start_timer
timed
timed’car’
major=Rminor=G
18Datapath
Datapath & Control
ControlSensorcar
Counter
timed
MAJOR
MINOR
MAJOR
M INORstart_timer
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Example: ASM Chart
car
R
MINOR
MAJOR
G
0
0
start_timer
1
1timed
ASM Block
Datapath
ControlSensorcar
Counter
MAJOR
MINOR
MAJOR
MINOR
start_timertimed
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Traffic Controller with a Timer
• There is an abundance of states.
• states from s0 to s255 map to a simple counter
• we can just separate the traffic light controller from the timer.
MAJOR
G
car
1
MINOR
s0
MINOR
s255
0
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Linked ASM Charts
IDLE
start
1
timeup
0
s0
s255
MAJOR
G
MINOR
R
car
start_timer
timed
0
0
1
1
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Linked ASM Charts
CNT 0
IDLE
start
1
0
MAJOR
G
MINOR
R
car
start_timer
timed
0
0
1
1
timeup
1
COUNT
CNT CNT+1
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Linked ASM Charts
CNT 0
IDLE
start
1
0
MAJOR
G
MINOR
R
car
start_timer
timed
0
0
1
1
CNT==255
1
COUNT
CNT CNT+1
Traffic Control Example - Schematic
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Note that present_state, start_timer and timed outputs are normally not shown (they are internal). Here, they are used for debugging
Verilog Code – Counter 1/4`timescale 1ns / 1ps
module Counter(input clk, reset, start, output reg timeup);
reg pres_state;reg next_state;reg[2:0] CNT;
parameter ST_IDLE=1'b0, ST_COUNT=1'b1; parameter LIMIT = 3'd6;
//Sequential circuit state transitionsalways@(posedge clk or posedge reset)begin if(reset)
pres_state <= ST_IDLE; else
pres_state <= next_state;end...
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reset
start timeup
Verilog Code – Counter 2/4...//Combinational state transition circuitalways@(*)begin case (pres_state)
ST_IDLE: begin if(start) next_state = ST_COUNT; else next_state = ST_IDLE; end ST_COUNT: begin if(timeup) next_state = ST_IDLE; else next_state = pres_state; end default: next_state = ST_IDLE; endcase
end
...26
Verilog Code – Counter 3/4
...// sequential internal registry update.always@(posedge clk)begin case(pres_state) ST_IDLE: CNT <= 0; ST_COUNT: CNT <= CNT + 1;
endcaseend...
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Verilog Code – Counter 4/4
... //Combinational output circuitalways@(*)begin
case (pres_state) ST_COUNT: if(CNT == LIMIT)
timeup = 1'b1; else
timeup = 1'b0;default:
timeup = 1'b0;endcase
end
endmodule
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Verilog Code –Trafic Light 1/4`timescale 1ns / 1psmodule TraficLight (clk, reset, car, timed, MAJOR, MINOR, start_timer, pres_state);
input clk, reset, car, timed; output MAJOR, MINOR, start_timer, pres_state;
reg next_state;reg pres_state;
reg MAJOR;reg MINOR;reg start_timer;
parameterST_G = 1'b0,ST_R = 1'b1;
// FSM starts//Sequential circuit state transitionsalways@(posedge clk or posedge reset)begin if(reset) pres_state <= ST_G; else pres_state <= next_state;end... 29
reset
car
MAJOR
timed
start_timer
MINOR
pres_state
Verilog Code –Trafic Light 2/4...//Combinational circuit for state transitionalways@(*) case (pres_state) ST_G: begin if(car) next_state = ST_R; else next_state = pres_state; end ST_R: begin if(timed) next_state = ST_G; else next_state = pres_state; end default: next_state = ST_G;
endcase...
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Verilog Code –Trafic Light 3/4...//Combinational circuits outputsalways@(*) case(pres_state) ST_G: begin if(car) start_timer = 1; // Mealy output else start_timer = 0; // Mealy output end default: start_timer = 0; endcase // FSM ends...
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Verilog Code –Trafic Light 4/4...// DATAPATH STARTS: We have 2 register at datapath MAJOR and MINOR//DATAPATH starts
always@(*)begin case(pres_state)
ST_R: begin MAJOR = 0; // Moore output MINOR = 1; // Moore output end default: begin MAJOR = 1; // Moore output MINOR = 0; // Moore output end endcase end
//DATAPATH ends endmodule
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Traffic Control Example - Simulation
• Note 1: 0 is state Green and 1 is state Red for present_state.
• Note 2: Second time the “car” signal is asserted, the system is not affected, because the system is designed in this way (i.e., the car signal is effective only when the present state is Green). 33
Traffic Control Example - Verilog Code
• Please see the files “TrafficLight.v” and “Counter.v” for verilog codes of the traffic control example.
• Note that these modules are seperate and they are used– in a schematic file called “TrafficControl_sch.sch”, – and, in a verilog file called “TrafficControl.v”.
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ASM Block• A structure consisting of one state box and all the
decision and conditional boxes associated with it.
A A + 1
e
f R 0
T1
T2 T3 T4
1
1
0
0
001
010 011 100
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ASM Block• One input path, any number
of exit paths• Each ASM block describes
the state of a system during one clock-pulse interval– The register operations within
the state and conditional boxes in the example are executed with a common clock pulse when the system in this state (e.g., T1 in the example)
– The same clock pulse transfer the system controller to one of the next states (e.g., T2, T3, or T4)
A A + 1
e
f R 0
T1
T2 T3 T4
1
1
0
0
001
010 011 100
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Timing Considerations 1/4
• The pulses of the common clock are applied to– registers in the datapath– all flip-flops in the control
• We can assume that inputs are also synchronized with the clock– Since they are the outputs of another circuit
working with the same common clock.– Synchronous inputs
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Timing Considerations 2/4• Major difference between a conventional
flow chart and ASM chart is in the time relations among the various operations
• Example
A A + 1start
e
f R 0
T1
T2 T3 T4
1
1
0
0
001
010 011 100
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Timing Considerations 3/4
• If it were a conventional flowchart1. A A + 1
2. start = 1
3. if e = 1 then
R 0
next state is T4
4. else
if f = 1 then
next state is T3
elsenext state is T2
A A + 1start
e
f R 0
T1
T2 T3 T4
1
1
0
0
001
010 011 100
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Timing Considerations 4/4• But, in ASM chart,
interpretation is different– all operations in a block occur in
synchronism with the clock
– “start” is asserted in T1
– input signals “e” and “f” are checked in T1
– The following operations are executed simultaneously during the next positive edge of clock
• A A + 1• R 0 (if e = 1) • control transfer to the next
state
present state T1next state T2 or T3 or T4
clock
A A + 1start
e
f R 0
T1
T2 T3 T4
1
1
0
0
001
010 011 100
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Example: Binary Multiplier
• Sequential multiplier• Algorithm: successive additions and shifting
multiplier
multiplicand
x2 y0x2 y1x2 y2x2 y3
x3 y0x3 y1x3 y2x2 y3
x1 y0x1 y1x1 y2x1 y3
x0 y0x0 y1x0 y2x0 y3
x0x1x2x3×
y0y1y2y3
+
z7 z0z1z2z3z4z5z6
product
partial product
Hardware Algorithm for MultiplierInput: X, Y, n = log2X
Output: Z = X Y
Step 0. if (Start == 0) do nothing
else go to Step 1;
Step 1. Q X; B Y; A 0; C 0; CNT n; go to Step 2;
Step 2. CNT CNT-1;
if(Q0 == 1)
A A+B; C Carry(A+B);
go to Step 3;
Step 3. CAQ shr(CAQ); C 0;
if (CNT == 0) go to Step 0;
else go to Step 2; 42
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Schematic of Binary Multiplier• Register Configuration
Register B
multiplicand
multiplier
Register Q0
Parallel adder
sum
Register A
CNT
Check for zero
n
Controllogic
S(start)
if CNT= 0 then Z = 1
Z
Q0
Product
C
cout
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Example: ASM ChartT0
S0
Q0
A A + B, C Cout
10
CNT==00 1
QX; A 0 B Y; C 0
CNT n
1T1
CNT CNT - 1
T2
Shift Right CAQ, C 0
T3
A shr A, An-1 C
Q shr Q, Qn-1 A0
C 0
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Example: ASM ChartT0
S0
Q0
A A + B, C Cout
10
CNT=00 1
1
CNT CNT - 1
T1
Shift Right CAQ, C 0
T2
A shr A, An-1 C
Q shr Q, Qn-1 A0
C 0
QX; A 0 B Y; C 0
P n
Multiplier – Verilog Code 1/7module TopModule(x, y, n, clk, start, reset, out, state, cnt);
input [3:0] x, y, n;
input clk, start, reset;
output [8:0] out;
output [1:0] state;
output [3:0] cnt;
reg [8:0] out;
reg [1:0] state;
reg [3:0] b, a, q, cnt;
reg c;
parameter t0=0, t1=1, t2=2, t3=3;
parameter zero = 0;
...
46
Multiplier – Verilog Code 2/7...
module TopModule(x, y, n, clk, start, reset, out, state);
...
always @ *
begin
case (state)
t0:
out = {c, a, q};
t1:
out = {c, a, q};
t2:
out = {c, a, q};
t3:
out = {c, a, q};
default:
out = {c, a, q};
endcase
end
...47
Multiplier – Verilog Code 3/7...
always @(posedge clk or posedge reset)
begin
if (reset)
begin
state <= t0;
a <= zero;
b <= zero;
c <= zero;
q <= zero;
cnt <= zero;
end
else
...
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T0
S0
from T3
to T1
reset
Multiplier – Verilog Code 4/7...
always @(posedge clk or posedge reset)
begin
if (reset)
...
else
case (state)
t0:
if(start)
state <= t1;
else
state <= t0;
...
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T0
S0
from T3
to T1
reset
Multiplier – Verilog Code 5/7...
always @(posedge clk or posedge reset)
begin
if (reset)
...
else
case (state)
...
t1:
begin
b <= y;
q <= x;
cnt <= n;
state <= t2;
end
...
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S
QX; A 0 B Y; C 0
CNT n
1T1
to T2
0
to T0
from T0
...
always @(posedge clk or posedge reset)
begin
if (reset)
...
else
case (state)
...
t2:
begin
if(q[0] == 1'b0)
begin
cnt <= cnt - 1;
state <= t3;
end
else
begin
cnt <= cnt - 1;
{c, a} <= a + b;
state <= t3;
end
end
... 51
Q0
A A + B, C Cout
1
CNT CNT - 1T2
0
To T3
To T3
Multiplier – Verilog Code 6/7
...
always @(posedge clk or posedge reset)
begin
if (reset)
...
else
case (state)
...
t3:
begin
if(cnt == 0) begin
{c, a, q} <= {1'b0, c, a, q[3:1]};
state <= t0;
end
else begin
{c, a, q} <= {1'b0, c, a, q[3:1]};
state <= t2;
end
end
endcase
end
endmodule
Multiplier – Verilog Code 7/7
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CNT==00 1
Shift Right CAQ, C 0T3
from T2
to T2 to T0
Multiplier – Test Code 1/4`timescale 1ns / 1ps
module topmoduleTest;
// Inputs
reg [3:0] x;
reg [3:0] y;
reg [3:0] n;
reg clk;
reg start;
reg reset;
// Outputs
wire [8:0] out;
wire [1:0] state;
wire [3:0] cnt;
...
53
Multiplier – Test Code 2/4`timescale 1ns / 1ps
module topmoduleTest;
...
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.x(x),
.y(y),
.n(n),
.clk(clk),
.start(start),
.reset(reset),
.out(out),
.state(state),
.cnt(cnt)
);
...
54
Multiplier – Test Code 3/4`timescale 1ns / 1ps
module topmoduleTest;
...
initial begin
// Initialize Inputs
x = 0;
y = 0;
n = 0;
clk = 0;
start = 0;
reset = 0;
...
55
Multiplier – Test Code 4/4module topmoduleTest;
...
initial begin
...
// Wait 15 ns for global reset to finish
#15
reset = 1;
#10
reset = 0;
#5
start = 1;
n = 4;
x = 10;
y = 13;
#10
start = 0;
#200;
end
always #10 clk = ~clk;
endmodule56
Multiplier – Simulation 1/3
57
Multiplier – Simulation 2/3
58
Multiplier – Simulation 3/3
59
