1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

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Page 1: 1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

1 of 24

The new way for FPGA & ASIC development

© 2004-2007GE-Research

Page 2: 1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

Semulator V2.2 dsr 2 of 24

Development of complex FPGA and ASIC

Stable parts transferred to Hpe_midiDesign File

VHDL

Design FileVerilog

Testbench Files

HDL Simulatorand Hpe Desk

Design FileSystemC

Design Files

Macro3

Macro4

Macro1

Macro2

Simulation & Emulation

Stable parts transferred to Hpe_midi

Stable parts transferred to Hpe_midi

Stable parts transferred to Hpe_midi

SEmulation=

Simulator controlled Emulation

Hpe_midi

R a

p i

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P r

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H D

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Semulator V2.2 dsr 3 of 24

Development of complex FPGA and ASIC

Testbench Files

HDL Simulatorand Hpe Desk

Macro3

Macro4

Hpe_midi

Design FileVHDL

Macro1

Macro2

Switch off a FPGA block

• bug• challenge • specification change

Simulate with a new model

Macro3disabledMacro3A

Design finished!

H D

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Semulator V2.2 dsr 4 of 24

Wave Window

Development of complex FPGA and ASICdebugging

Testbench

HDL Simulatorand Hpe Desk Hpe_midi

H D

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R a

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LEON3SPARC V8

I-Cache D-Cache

FPU CoP

MMU

PCIExpress

SVGAController

AHB

PCIeX4 over Cable

• debugging on hardware with trusted test bench

+• hardware assertions (simple subset of PSL)

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Semulator V2.2 dsr 5 of 24

Hardware in the Loop

Hpe_midi

Macro1

Macro n

...

Ext. Componente.g. CPU

Hpe_child board

Standard components can be implemented directly into simulation and emulation

Testbench Files

HDL Simulatorand Hpe Desk

Design FileVHDLH

D L

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u l

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o r

R a

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Used for EmulationUsed for Simulation

Controlled by a click in Hpe_desk

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Semulator V2.2 dsr 6 of 24

Clock Acceleration*

Testbench Files

HDL Simulatorand Hpe Desk

Macro3

Macro4

Hpe_midi

Macro1

Macro2

Controlled by userClockFactory

up to 100 MHz

Simulator clock

20kHz – 200 kHz

*International patent applied

Individual clock for

every macro

Runs your Modelsim ® simulation in “real time”H

D L

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Semulator V2.2 dsr 7 of 24

What you need for SEmulation:

• A standard FPGA development system e.g. Hpe_midi

• A PCIe X4 over cable communication card e.g. Hpe_com1

• Software package Hpe_desk includes SEmulator, Clock Factory Programmer, JTAG Scanner/Debugger, ALTERA Quartus

• And last but not least a PC and MENTOR Modelsim

Page 8: 1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

Semulator V2.2 dsr 8 of 24

Faster Simulation

The SEmulator can speed up your Modelsim simulation:

Page 9: 1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

Semulator V2.2 dsr 9 of 24

Clock Factory

You can program every clock source -> clock input by a click

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Semulator V2.2 dsr 10 of 24

JTAG Debugger / Scanner

You can read and write every pin of every component in the JTAG chain,customer specific chain in DUT is supported.

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Semulator V2.2 dsr 11 of 24

Advantages of SEmulation

• Early and continued testing of final hardware Higher design quality / reliability

• Dramatically decrease RTL simulation time Decrease development time

• Standard FPGA board for development, different boards available No additional hardware cost

• Hardware in the Loop (Cosimulation) Every external hardware can be implemented easily in the SEmulator

• ‘No’ limitation on pin and gate count Broad family concept – Many extension boards

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Semulator V2.2 dsr 12 of 24

What are successful teams doing?% of designs achieving 1st silicon success by verification technique

0% 5% 10% 15% 20% 25% 30% 35% 40% 45%

Sim. Acceleration

Model Checking

Special Test Chips

Transistor-level Sim.

HW/ SW Co-Verification

Theorem Proving

Standard C/ C++

Custom built system

Random

Functional

Equivalency Checking

Code Coverage

Directed

Full-Timing

Commercial emulation system

FPGA prototyping

Constrained-Random

Assertion

System Level (TLM)

Ver

ific

atio

n T

ech

niq

ues

1st Silicon Success Rate %

Collett International Research Inc.,2004 IC/ASIC Functional Verification Study

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Semulator V2.2 dsr 13 of 24

H u m a n I n t e r f a c eInternal and external

LCDConnector

Keyboard

DIP LED

FPGAPrototyping Area

Clock Factory

Reset

PowerSupply3,3V2,5V

12V

Hpe_childConnector

Hpe_childConnector

Santa CruzConnector

USB2.0FS-Host

USB2.0FS-Host

USB2.0FS-OTG

Ethernet10/100

RS232

RS232

LIN

CAN

VGA3 * 8bit

PS2

AC97

SD-Card

FLASH8M*32

SRAM256k*32

EEPROM2k bit

720 pin Hpe Module Connector473 I/O plus Power Supply 6-12 bit

D/A6-12 bit

A/D

USB2.0HS-Target

Motherboard for FPGA development

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Semulator V2.2 dsr 14 of 24

The Enclosure - Protect your hardware

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Semulator V2.2 dsr 15 of 24

1 FPGA module for FPGA development with or without SEmulation

180.000 (340.000) Logic Elements = 1.8 (3,4) Mio ASIC gates*)

Hardware in the LoopEvery Child Board can be used for simulation

and for emulation

*) Figures in brackets are STRATIX3 values

I/O manager can be added on request

Clock Factory

IP & SWProtection

Controller

Hpe_module1X

Child Board

High speed access L4

Hpe_module connector473 I/O plus power supply

Child Board

EP2S180DUT

CommonConfig.Device

ALTERAUSB

BlasterTo PC

CommunicationController

PCIe X4over cable

Hpe_PCIe Child Board

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Semulator V2.2 dsr 16 of 24

Child Board

2 FPGA module for FPGA development with or without SEmulation

360.000 (680.000) Logic Elements = 3.6 (6.8) Mio ASIC gates

High speed access 2 * L4

Hpe_module connector473 I/O plus power supply

EP2S180DUT

Child Board

EP2S180DUT

512 single ended bus

128 LVDS pairs between every FPGA

CommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

Hpe_module2X

CommunicationController

PCIe X4over cable

Hpe_PCIe Child Board

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Semulator V2.2 dsr 17 of 24

4 FPGA module for FPGA development with or without SEmulation

720k (1,3 Mio) Logic Elements = 7,2 (13) Mio ASIC gates

CommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

PCIe X4over cable

CommunicationController

Hpe_PCIe Child Board 256 bit single ended bus

64 LVDS pairs between every FPGA

high speed access (L4)

EP2S180DUT

EP2S180DUT

EP2S180DUT

EP2S60 Board

Controller

Child Board

o 48 LVDS-I/O

u 128 se

EP2S180DUT

Child Boardo L17

u L17

u L16

Child Board

o 48 LVDS-I/O

u 128 se

Child Board

o 48 LVDS-I

u 128 se

Child Board

o 48 LVDS-O

u 128 se

Child Boardo L17

Child Board

o 128 se

Child Board

o 128 se

Child Board

o 128 se

Child Board

o 128 seDDR2 socketDDR2 socket

Hpe_module4X

Page 18: 1 of 24 The new way for FPGA & ASIC development © 2004-2007 GE-Research.

Semulator V2.2 dsr 18 of 24

CommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

PCIe X4over cable

CommunicationController

Hpe_PCIe Child Board

ModuleX4

ModuleX4

Mainboard

Hpe_childboard

1,6M (3 Mio) Logic Elements = 16 (30) Mio ASIC gates

high speed access

EP2S180DUT

EP2S180DUT

EP2S180DUT

EP2S60 Board

Controller

Child Board

o 48 LVDS

u 64 LVDS

EP2S180DUT

Child Boardo 2 * L16

u 2 * L16

u L16

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Boardo L16

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDSDDR2 socketDDR2 socket

high speed access

EP2S180DUT

EP2S180DUT

EP2S180DUT

EP2S60 Board

Controller

Child Board

o 48 LVDS

u 64 LVDS

EP2S180DUT

Child Boardo 2 * L16

u 2 * L16

u L16

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Boardo L16

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDSDDR2 socketDDR2 socket

Hpe_module8X

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Semulator V2.2 dsr 19 of 24

Hpe_child Board

• Hpe_child board with 99 I/O signals• Easy stackable, easy connectable to Logic Analyzer• Connects the SEmulator with the ‚real world‘• Development plan for 2006/2007

– Universal connector and test board – DDR1 and DDR2 RAM – 1G Ethernet (twice)– A/D and D/A for high speed– A/D and D/A for high resolution– Video in and Video out– 8 UART / RS232– MOST and FlexRay– Wireless (Nanonet and/or Bluetooth)– High speed optical– PCI Express external X4 and X8(16)

• We develop customer specific child boards on demand(Ask for details of our development participation program)

Hpe_child board connector:130 pin, 99 usable I/O

Example of a Hpe_child board

Adapter board to connecta logic analyzer

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20 of 24

C o

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The next Generation

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Semulator V2.2 dsr 21 of 24

4 FPGA module for FPGA development with or without SEmulation

720k (1,3 Mio) Logic Elements = 7,2 (13) Mio ASIC gates

CommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

PCIe X4over cable

CommunicationController

Hpe_PCIe Child Board

high speed access

EP2S180DUT

EP2S180DUT

EP2S180DUT

EP2S60 Board

Controller

Child Board

o 48 LVDS

u 64 LVDS

EP2S180DUT

Child Boardo 2 * L16

u 2 * L16

u L16

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 48 LVDS

u 64 LVDS

Child Boardo L16

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDSDDR2 socketDDR2 socket

Hpe_module4XL

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Semulator V2.2 dsr 22 of 24

2 FPGA module for FPGA development with or without SEmulation

PCIe X4over cable

CommunicationController

Hpe_PCIe Child BoardCommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

high speed access

EP2S180DUT

Child Board

o 48 LVDS

u 64 LVDS

EP2S180DUT

Child BoardL4 o L4

u L16

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDS o 64 LVDSDDR2 socket

Hpe_module2XL

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Semulator V2.2 dsr 23 of 24

1 FPGA module for FPGA development with or without SEmulation

PCIe X4over cable

CommunicationController

Hpe_PCIe Child BoardCommonConfig.Device

ALTERAUSB

Blaster

Clock Factory

To PC

IP & SWProtection

Controller

high speed access

EP2S180DUT

Child Board

o 48 LVDS

u 64 LVDS

Child Boardo L 4

u L16

Child Board

o 48 LVDS

u 64 LVDS

Child Board

o 64 LVDS

Child Board

o 64 LVDSDDR2 socket

Hpe_module1XL

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Semulator V2.2 dsr 24 of 24

H u m a n I n t e r f a c eon front panel

4 * 20 charLCD

Keyboard

DIP LED

Clock Factory

Reset

PowerSupply3,3V2,5V

12V

USB2.0FS-Host

USB2.0FS-Host

USB2.0FS-OTG

Ethernet10/100

RS232

RS232

LIN

CAN

VGA3 * 8bit

PS2

AC97

SD-Card

Motherboard for FPGA development

6-12 bitD/A

6-12 bitA/D

USB2.0HS-Target

Modul Connector128 I/O pin

FLASH8M*32

SRAM256k*32

Modul Connector128 I/O pin

Modul Connector128 I/O pin

SDRAMsocket

Modul Connector128 I/O pin

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