1

Microprocessor-based Systems

Course 8 Design of input/output interfaces

2

Input/output interfaces Role: adapt the

particularities of a peripheral device to the requirements of a computer system (system bus)

What to adapt: Signals Data transmission and

reception sequence The transfer speed/frequency

– the interface is a temporary buffer

Structure: 2 parts: Bus adapter Peripheral device adaptor

Peripheral device

Bus interface

Device interface

System bus

(address, data and command)

3

Schematic diagram of an input/output interface

Adress bus Data bus Commands bus Cmd. device Dec Cmd R Status R Output reg. Input reg.

IOR\ IOW\

Signal adapter Peripheral device

4

Components:

Bus interface: Data registers (input and output) command registers status registers register selection block (decoder) command device

Device interface: Signal adapters/converters Buffer memory (RAM) Program memory (driver) Device controllers (floppy, HDD, video, etc.) DMA controller, interrupt controller Etc.

5

Transfer modes

Main role of an interface: transfer of data Transfer types:

Transfer through program Transfer through interrupts Transfer through direct memory access (DMA) Transfer through input/output processor

Different degrees of main processor involvement Optimal selection of a transfer mode is based on :

transfer speed transfer complexity time and cost restrictions

6

Phases of a transfer

Transfer initialization tasks: setting the parameters of a transfer

direction of the transfer, number of data transferred, the address of the memory zone where or from

where the transfer is made Transfer phase

tasks: Transfer of data Synchronization with the peripheral device

Final phase tasks:

verify the correctness of the transfer

7

Transfer through a program

The simplest transfer mode requires simple hardware the transfer program is simple/short

The main processor handles all the phases and tasks of the transfer, through a routine (driver): Initialization Transfer: Final verification

8

A program example – without control signal (feedback)

buf: DB 100 DUP(?)lbuf EQU $-buf ; buffer lengthadrport EQU 300h ; input port address…….; transfer initialization

mov si, offset buf ; initialize memory pointermov dx, adrport ; initialize port addressmov cx, lbuf ; initialize counter

…….; transfer de dateet1: in al, dx ; read input port

mov [si], al ; memorize datainc si ; increment pointercall delay ; call delay routineloop et1 ; test the end of the transfer

……..

9

A program example – with control signal (feedback)

buf: DB 100 DUP(?)lbuf EQU $-buf ; buffer lengthadrport EQU 300h ; input port addressadrstare EQU 301h ; status port addressmasca EQU 01h ; mask for d0 bittimeout EQU 100h ; time limit…….; transfer initialization

mov si, offset buf ; memory pointer initializationmov dx, adrport ; port address initializationmov cx, lbuf ; counter initialization

…….; data transeret1: mov bx, timeout ; set the timeout limit

;inc dx ; status port address

et2: in al, dx ; read the portand al, masca ; test the status bitjnz et3 ; see if the bit is 1dec bx ; decrement timeout countercmp bx,0 ; test the timeout limitjnz et2jmp sfîrşit ; jump to the end

et3: dec dx ; input port addressin al, dx ; read portmov [si], al ; store the datainc si ; move on the pointerloop et1 ; test the end of the transfer and loop back in not

; verify the correctness of the transfersfîrşit: cmp cx,0 ; test if the transfer ended correctly

jnz eroare ; (counter=0)…….

10

Transfer through program – advantages and drawbacks

Advantages : Simple Easy to implement Cheep

Drawbacks: Slow The processor is blocked for the whole

duration of the transfer Inefficient

11

Transfer through interrupts

Feature: Solves the synchronization problem in the

transfer phase The processor can perform other tasks in

parallel The processor is responsible for the

initialization data transfer and verifications The interrupt: temporary pausing of a

program execution as result of an external or internal event or signal. Handling an interrupt: through the execution of

an interrupt routine The interrupt table: contains the address of

all interrupt routine

12

Handling multiple interrupt requests

Main program Interrupt Interrupt ….. într. j routine i routine j inter. i instr. n-1 ….. instr. n instr. k instr. n+1 instr. k+1 ….. …

13

The interrupt system for the Intel x86 processors

256 interrupt levels Interrupts:

Internal: Division by 0, software interrupts (INT n),

trace interrupt, overflow, breakpoint External:

Non-maskable: NMI Maskable INTR

Enable/Disable interrupts: STI: set interrupt – IF=1 - enable CLI: clear interrupt – IF=0 – Disable (masking)

14

Handling an interrupt request by the microprocessor

1. Save the next instruction's address and the status word (PSW) on the stack

2. generate 2 INTA cycles (INTerrupt Acknowlidge) to accept the interrupt and to identify the source of the interrupt; in the second cycle read the interrupt’s vector placed on the bus by the interrupt controller;

3. jump to the interrupt rountine; the address of the interrupt routine is found in the interrupt table in the position indicated by the interrupt vector;

4. when the routine is finished it will restore the status register (from the stack) and it will jump back in the interrupted program, using the address stored on the stack

5. continue the execution of the interrupted program

15

Interrupt types

Hardware: generated by external signals Interrupt signals: INTR, NMI Interrupt acknowledge signal: INTA/ Interrupt sources:

Input/output interfaces: mouse, keyboard, HDD, network Detect detectors: parity error, power-down

Software: generated by instructions Simulates hardware interrupts Used for calling functions of the operating system:

system calls (INT 21H) Interrupt instruction types:

INT n INTO INT 3 (breakpoint)

16

The interrupt controller - I8259A

Responsible for handling 8 hardware interrupts

Bus system μP INTR IRQ0 I/O I/O INTA\ IRQ1 interface interface I8259A IRQ7

Figure 10-3. Connecting the I8259A controller in the system

17

The internal structure of an interrupt controller (I8259)

D0-7 Data Command device INTR ampl. INTA\ IOR\ Control ISR CMP IRR IRQ0 IOW\ logic … A0 IRQ7

CS\ CAS0-2 Cascading Mask reg (IMR) block

18

Programming the interrupt controller

initialization words (used once when the system is started) - ICW0-4 (Initialization Command Word)

operation words (used during normal operations ) - OCW0-3 (Operation Command Word)

The following parameters are set through the program: working mode 8080 or 8086 interrupt detection mode: on edge (transition from 0

to 1) or on level interrupt nesting mode: normal or special (nesting=

handling a new interrupt during the execution of a previous one)

priority type: fixed or through rotation the position of the handled interrupts in the

interrupt space of the processor (the base address)

19

The interrupt handling sequence

1. The Interface generates an interrupt by activating an IRQ signal to the controller

2. The Controller test if the interrupt is allowed and if there are no higher priority interrupts in service

3. If the interrupt is allowed and there are no higher priority interrupts than the controller generates an interrupt to the processor through the INTR signal

4. Afer the end of the current instruction the Processor generates 2 INTA cycles in order to accept and identify the interrupt source

5. On the second INTA cycle the controller puts on the data lines the interrupt vector (its number)

6. The Processor uses the vector as an index in the interrupt table to find the address of the interrupt routine

7. The Processor saves on the stack the returning address and the program status word (PSW), than makes a jump to the interrupt routine

8. At the end of the interrupt routine the processor sends a command to the controller in order to end the interrupt (EOI)

9. As a result of the IRET instruction (return from interrupt routine) the processor restores the PSW and gets the returning address from the stack; than it makes a jump to this address, continuing the interrupted program

20

The interrupt system of the IBM PC compatible computers

2 interrupt controllers Hardware interrupts:

Real-time counter Keyboard Serial channels printer interface FDD/HDD interface Network interface

Software interrupts: BIOS interrupts: keyboard, video interface, serial

transmission, printing, external memory (HDD. floppy) operations

System calls (INT 21h): read the standard input channel, write the standard output channel, read/write on disck, etc.

21

Example of redirecting an interruptVECT DW 2 DUP(?) ; place for saving the old interrupt routine’s address

;initialization……..MOV AH, 35h ; 35h-system function for reading the interrupt vector MOV AL, n ; n – the level of the redirected interruptINT 21h ;call the system routine ;the routine will return in ES:BX the address of the old routineMOV VECT, BX ; save the addressMOV BX, ESMOV VECT+2, BXMOV AX, SEG RUT_INTMOV DS, AX ;DS <- the segment address of the new routineMOV DX, OFFSET RUT_INT ; DX <- the offset address of the new routine MOV AH, 25h ;25h – the function that writes the address in the interrupt

table MOV AL,n ;n – the interrupt levelINT 21h ;call the function……….; main program

………INT n……; end of the programMOV AX, VECT+2 ; restore the old addressMOV DS, AXMOV DX, VECT MOV AH, 25hMOV AL,nINT 21h…….

22

Continue

;interrupt handling routineRUT_INT PROC FAR ; the new interrupt handling routine

PUSH r ; save all the registers used in the routine; (r = AX, BX, ….)

STI ; enable interrupts………..

; the body of the routine………..

; end of the routinePOP r ; restore registersIRET

RUT_INT ENDP

23

Example 2 – programming a hardware interrupt

INTA00 EQU 20H ; address of port 0 in the interrupt controllerINTA01 EQU 21H ; address of port 1 in the interrupt controller EOI EQU 20h ; end of interrupt commandMASCA EQU 11011111B ; mask for enabling interrupt no. 5MASCA1 EQU 00100000B ; mask for disenabling interrupt no. 5

………..; initialize the interrupt

CLI ; disable maskable interrupts MOV AX, SEG RUT_INTMOV DS, AXMOV DX, OFFSET RUT_INT MOV AH, 25h ; 25h – routine for writing an interrupt vector MOV AL, 5+8 ; 5+8= the level of the programmed interrupt;the address of the first controller is 8 INT 21h ; system callMOV DX, INTA01IN AL,DX ; read the mask registerAND AL, MASCA ; clear the mask bit for interrupt 5OUT DX,AL ; enable the interruptSTI ; enable all maskable interrupts……….; program

………

24

Continue

; end of programCLI

MOV DX, INTA01IN AL,DX ; read mask registerOR AL, MASCA1 ; set the mask register for interrupt 5OUT DX,AL ; disable the interrupt entrySTI…….;interrupt handling routineRUT_INT PROC FAR ; new interrupt handling routine

PUSH r ; save the registers used in the routineSTI ; enable interrupts………..

; body of the routine………..

; end of the routineMOV DX, INTA00MOV AL,EOIOUT DX, AL ; end of interrupt commandPOP r ; restore register’s contentIRETRUT_INT ENDP