1 Memory Systems Computer Architectures M. 2 EPROM memories Access time: 50-80 ns VPP A16 A15 A12 A7...
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Transcript of 1 Memory Systems Computer Architectures M. 2 EPROM memories Access time: 50-80 ns VPP A16 A15 A12 A7...
1
Memory Systems
Computer Architectures M
2
EPROM memories
• Access time: 50-80 ns
VPPA16A15A12A7A6A5A4A3A2A1A0D0D1D2GND
VCCPGM*
NCA14A13A8A9
A11OE*A10CE*D7D6D5D4D3
EPROM12345678910111213141516
32313029282726252423222120191817
128K 8
Ai
CE*
OE*
Di
Tce
Tacc
Toe
CE*OE*
DiCell M/bit i
Tri-state driver
• Non volatile read-only memories
• Capacities: two’s multiples: 32K, 64K, 128K, 256K……
3
RAM memories(SRAM)
• DRAM: 1 transistor per bit, higher capacity, less speed
Ai
CE*
OE*
I/Oi
Tce
Tacc
Toe
(Out)
ReadCycle
Ai
CE*
WE*
I/Oi
Taw
Twp
(In)
Tds
WriteCycle
NCA16A14A12A7A6A5A4A3A2A1A0I/O0I/O1I/O2GND
VCCA15NC
WE*A13A8A9
A11OE*A10CE*I/O7I/O6I/O5I/O4I/O3
12345678910111213141516
32313029282726252423222120191817
128K 8
RAM
• Volatiles memories, readable and writable
• Capacity four’s multiples: 8K, 32K, 128K, 512K……
• Access time: 5-40 ns
C Qi
D
Cell Address: “j”
RAM cell
DECODER
j
2n N => 2n cells each of N bits
WR RD Data bit
Tri-state driver
5
Decoder and Decoder matrix
C D “column decode”
(AND => associative property)
A
B
“row decode”
6
7
8
9
10
Register File (1 read-port, 1 write-port)
DECODER
01
M-1
EN*
n
Read_Address
DEC
01
M-1
EN*
n
Write_Address
RD* WR*
N
Write_DataRead_Data
N
CK
D[0..N-1] WE*OE*
O[0..N-1]
R0
D[0..N-1] WE*OE*
O[0..N-1]R1
D[0..N-1] WE*OE*
O[0..N-1]RM-1
N.B. :M=2n
A memory device is a register file
12
Memories with 2K bytes• Any memory (and in particular memories with 8-bit parallelism – the only we will address), with 2k cells,
has internally a k-variables decoder with E enable (negative true) input (this means that when E = 1 none of the outputs of the decoder is active) which selects one of the memory bytes. The memory interface has therefore the following signals
• Address bits ( An….A0) which select the addressed byte (if E enabled)
• Data bits (D7….D0)
• At least one chip select (CS*) (called also “chip enable” (CE* - asterisk means «negative true») which is the enable of the decoder. If CS* is inactive (=1) it means that no byte of this memory (of this «chip») is addressed. CS* is used to selected a memory device when multiple devices are present
• A memory bank (device) is «aligned» if its lowest address within the entire memory system is located at an address multiple of 2k (a 4 cells device is aligned if its two LSBs address are 0 – multiple of 4 -, a 64K cells device if its 16 LSBs are 0 etc.)
• A Read Command (RD*) which enables the data onto the bus. Normally there is also an Output Enable (OE*) signal. The addressed byte of the memory is output only if CS*=RD*=OE*=0
• If the memory is a RAM (read/write memory) another signal is present: write command WR* or WE* which allows to store bus data into the selected memory byte. Obiously this can occur only if CS*=RD*=OE*=0
• Needless to say RD* and WR* are mutually exclusive
• In a system there are normally multiple memory devices in order to implement memory systems bigger that a single device. Multiple devices are therefore needed, each one implementing a portion of the entire memory
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0K
32K
8K
8K
8K
8K
Memory space
0121314
Device selection
Devices internal address
Memory device implementing a memory
system portion
0000
1FFF
8K CS* = (A14 A13*)*
In this case
An example: a 32 Kbytes memory system made with 8K devices32 Kbytes correspond to a 15 bit address
Memory systems with parallelism > 8An example: a 16 bit bus
Logicmemory Physical
memoryHigh BUS Low BUS
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
1
0a
b
c
d
e
f
g
h
i
a
c
e
g
i
b
d
f
h
l
078bit 15
memories internal address
The physical memories must be always coupled!
For instance 2 x 8K = 16 K !
2
Chip pin A0 -> AD1 bus A1 -> AD2 bus
………………………..
Word(4) -> Byteh(2) & Bytel(2) => 2 read
Logic Physical Physical
(f,e) (f ) (e )
What about a word at address 7 (not aligned)????
Memories physical address = Logic address / 2
Word(7) -> Byteh(i) & Bytel(h) => 4/3 read
Logic Physical Physical
(i,h) (i ) (h )
ll
Two memory accesses!!!!
14
For each bus there must be a ByteEnable*
BE0* for bus7-0 e BE1* for bus15-8
Memory systems with parallelism > 8An example: a 16 bit bus
15
mov al, even_byte_address ; transfer one byte at even address => one bus cycle 8 bit =>BE0*
mov al, odd_byte_address ; transfer one byte at odd address => one bus cycle 8 bit => BE1*
mov ax, even_word_address ; transfer one word at even address => one bus cycle 16 bit => BE0* and BE!*
mov ax, odd_word_address ; transfer one word at odd address => two 8 bit cycles => BE1* and then BE0*
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MEMORIES in a 16 BIT SYSTEM (I.E. 8086)
BE1* BE0*
0 0 Word
0 1 High Byte (odd addr.)
1 0 Low Byte(even addr.)
1 1 No transfer
The routing of byte high external to byte low internal is implemented
within the microprocessor chip
A0 of the processor not generated (instead BE0* and BE1*) A1 of the processor connected to chip pin A0 A2 of the processor connected to chip pin A1
etc. etc.
7 015 8Physical memories
MicroprocessorRi
MUX
Odd addresses Even addresses
17
Memory systems with parallelism > 8A 16 bit bus in a 1MB memory (19 to 0 addresses)
128K
128K
128K
128K
FFFFFh
00000h
40000h
5FFFFhPhysicalmemoryHigh BUS Low BUS
64K 64K
070bit 70000h
FFFFh
EPROM internal addresses
2 x 64K = 128K
EPROM1BE1*
EPROM0BE0*
CSEPROM1= A19* A18 A17* BE1
CSEPROM0= A19* A18 A17* BE0In the square the bank selection
CS here in positive true form
The decoding is performed as if a 8-bit memory were used.Devices (a couple!) (each one half size of the bank) are used
and selected by BE0 e BE1
Logicmemory
(5H=0101B ; 4H=0100B)
18
Memory systems with parallelism > 8A 16 bit bus in a 1MB memory (19 to 0 addresses)
400054000440003400024000140000
5FFFH5FFFE5FFFD5FFFC5FFFB
Logic Memory
128K
HIGH BUS(logic odd addresses)
Eprom pin 7 0 Bus Pin 15 8
EPROM1BE1* - 64K
FFFFFFFEFFFDFFFC
0003000200010000
EPROM internal addresses
Logic memory addresses
LOW BUS(logic even addresses)
0 Eprom Pin 0 Bus Pin
77
EPROM0BE0* - 64K
FFFFFFFEFFFDFFFC
0003000200010000
EPROM internal addresses
Odd mP addresses Even mP addresses
19
Memory systems with parallelism > 8A 32 bit bus
LogicMemory
PhysicalMemory
BUS 3BE3*
8
7
6
5
4
3
2
1
0 a
b
c
d
e
f
g
h
i
a
e
i
b
f
l
07815
c
g
d
h
162324bit 31
8
7
6
5
4
2
1
0
BUS 2BE2*
BUS 1BE1*
BUS 0BE0*
Always 4 coupled devices------------------
Internal memoriesphysical address is the
processor address/4
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32 BIT bus memories
BE3* BE2* BE1* BE0*
0 0 0 0 Word 32 bit
1 1 0 0 Half word low
0 0 1 1 Half word high
1 1 1 0 byte 0-7
N.B. Processor A0 and A1 are not generated (instead BE0*, BE1*, BE2*, BE3* are generated)
Processor A2connected to memories A0Processor A3connected to memories A1
etc. etc.
etc.
1 1 0 1 byte 15-8
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32 BIT bus memories(NB the symbol ! before a logic variable is equivalent to asterisk and means negation)
Logic Memory
2MB
2MB
2MB
FFFFFFFFh
00000000h
40000000h
401FFFFFh
4 Memories x 512K= 2MB
Memory bank selection
CSEPROM3= !A31 A30 !A29 !A28 !A27 !A26 !A25 !A24 !A23 !A22 !A21 BE3
CSEPROM2= !A31 A30 !A29 !A28 !A27 !A26 !A25 !A24 !A23 !A22 !A21 BE2
CSEPROM1= !A31 A30 !A29 !A28 !A27 !A26 !A25 !A24 !A23 !A22 !A21 BE1
CSEPROM0= !A31 A30 !A29 !A28 !A27 !A26 !A25 !A24 !A23 !A22 !A21 BE0
CS as Positive true form
Physical Memory
BUS 3
512K
2431 00000h
7FFFFh
EPROM internal addresses
EPROM3BE3*
512K
1623
EPROM2BE2*
512K
815
EPROM1BE1*
512K
07
EPROM0BE0*
BUS 2 BUS 1 BUS0
BUSselection
Aligned memory
In the selected bank eleven high address bit
are identical
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32 BIT bus memories
Logic Memory
Physical Memory
BUS 3 - D24-312MB
2MB
2MB
FFFFFFFFh
00000000h
512K
40000000h
401FFFFFh 00000h
7FFFFh
EPROM3
mP
512K
512K
EPROM2
EPROM1
00000h
7FFFFh
00000h
7FFFFh
512K EPROM0 00000h
7FFFFh
BUS 2 - D23-16
BUS1 - D15-8
BUS 0 - D7-0
BE0*
BE1*
BE2*
BE3*
Generated by the processorinstead of A1 and A0
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32 BIT bus memories
Logic Memory (as seen by the programmer)
512K
40000000h
401FFFFFh
00000h
7FFFFhEPROM3
Physical Memory (as really
implemented)
dh 00001h
2MB
512K
00000h
7FFFFhEPROM2
cg 00001h
512K
00000h
7FFFFhEPROM1
bf 00001h
512K
00000h
7FFFFhEPROM0
ae 00001h
abcde
40000001h
40000002h
40000003h
40000004h
physical addreses of the devices
------
x
Consecutive addresses data are on different devices
Byte x at logical address abcdefgh is located at physical address /4 abcdefgh of EPROM i where i is the rest of the division
abcdefgh
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Exercise
A 256K memory RAM (32 bit parallelism) bank starting at address 84000000H in a 4GB memory space using the minimum number of devices. No 128K and greater size RAM available
1) What is the address range?2) What RAM devices can be used ?3) What are the logic functions of the CE*4) Does the address parallelism influence the CE*?5) What if the data parallelism were 64 bit?
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Exercise
A 256K memory RAM (32 bit parallelism) starting at address 84000000 (aligned) in a 4GB memory space . Address range 84000000-8403FFFF. Devices: 8X32 K RAM devices (64K RAM do not exist!!!!)
First bankCSRAM00=(BA31BA30!BA29!BA28!BA27!BA26 .…BA18!BA17!)BE0CSRAM01=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE1CSRAM02=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE2CSRAM03=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE3
Second bankCSRAM10=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE0CSRAM11=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE1 CSRAM12=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE2CSRAM13=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE3
Therefore two banks of 128K : the first implements the range 000000 to 8401FFFF and the other the range 84020000 to 8403FFFF. The 32K memory chips use internally the addresses A14-A0 which are connected to bus addresses BA16-BA2 . Notice that bus address BA17 separates the two banks
Obviously the address parallelism influences the address range and therefore the high portion only of the CS
If the parallelism of the memory were 64 bit the 8 CS would NOT be affected by BA17. BE7-BE0 instead would play its role and memory chips addresses A14-A0 would be connected to bus addresses BA17-BA3 !! It is the parallelism which changes not the address range!!!