1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.
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Transcript of 1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.
![Page 1: 1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.](https://reader035.fdocuments.us/reader035/viewer/2022070402/56649f275503460f94c3ed6d/html5/thumbnails/1.jpg)
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Lecture 6
BOOLEAN ALGEBRA and GATES
Building a 32 bit processor
PH 3: B.1-B.5
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Lets Build a Processor
• Almost ready to move into chapter 5 and start building a processor
• First, let’s review Boolean Logic and build the ALU we’ll need(Material from Appendix B)
32
32
32
operation
result
a
b
ALU
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Boolean Algebra
• In Boolean Algebra, all variables are 0 and 1 and there are 3 operators
• OR is written as + as in A + B, called logical sum. (Sometimes denoted with A U B)
• AND is written as ∙ , as in A ∙ B, (also denoted AB) called the logical product. (Sometimes denoted by A ∩ B)
• NOT is written as A’. The result of NOT A is 0 if A is 1 and 1 if A is 0.
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Laws of Boolean Algebra
• Identity law: A + 0 = A and A ∙ 1 = A• Zero and One laws: A + 1 = 1 and A ∙ 0 = 0• Inverse laws: A + A’ = 1 and A ∙ A’ = 0• Commutative laws: A + B = B + A and A ∙ B = B ∙ A• Associative laws: A + (B + C) = (A + B) + C
A ∙ (B ∙ C) = (A ∙ B) ∙ C• Distributive laws: A ∙ (B + C) = A ∙ B + A ∙ C
A + (B ∙ C) = (A + B) ∙ (A + C)• DeMorgan’s laws: (A + B)’ = A’ ∙ B’ and
(A ∙ B)’ = A’ + B’
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Boolean Algebra & Gates
• Problem: Consider a logic function with three inputs: A, B, and C.
Output D is true if at least one input is trueOutput E is true if exactly two inputs are trueOutput F is true only if all three inputs are true
• Show the truth table for these three functions.
• Show the Boolean equations for these three functions.
• Show an implementation consisting of inverters, AND, and OR gates.
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Truth Tables
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Sum of Products
• The sum of products form is constructed from a truth table by choosing only those inputs that result in an output of 1 and forming the product of the inputs that are 1 and the complements of the inputs that are false. The sum of all such products gives an implementation of the function.
• For D this would mean D = A’B’C + A’BC’ + A’BC + … (7 terms in all). It works but we can do it easier by noting that D’ = A’B’C’.
• By one of DeMorgan’s Laws we have D = A + B + C
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Boolean Equations
• D = A + B + C
• F = ABC
• E = ABC’ + AB’C + A’BC or
E = (AB + BC + AC) (ABC)’
• It is easy to show the two equations for E are equivalent by using truth tables or by using DeMorgan’s law to change (ABC)’ into A’ + B’ + C’, then using the distributive law a few times.
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Another example of Sum of Products
The sum of products gives D = A’B’C + A’BC’ + AB’C’ + ABC
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Simplification of Boolean Expressions
• The Karnaugh map is a graphic method that can handle Boolean expressions up to 6 variables
• It is a simplification method that uses the following relations:
x + x’ = 1 and y ∙ 1 = 1 ∙ y = y• Basic idea is the sum of two expressions can be combined and
simplified if they have a distance of 1 where distance is defined as follows:
• The distance between two product terms is equal to the number of literals that occur differently, i.e., one is complemented while the other is not. For example A’B’C and A’B’C’ have a distance of 1 whereas A’BC and A’B’C’ have a distance of 2.
• Now the sum of the distance 1 pair can be simplified as follows:
A’B’C + A’B’C’ = A’B’(C + C’) = A’B’
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A one-variable Boolean function. (a) Truth table. (b) Karnaugh map.
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A two-variable Boolean function. (a) Truth table. (b) Karnaugh map
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An illustrative three-variable Boolean function. (a) Truth table. (b) Karnaugh map.
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A four-variable Boolean function. (a) Truth table. (b) Karnaugh map.
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Karnaugh map for a four-variable map functions.
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Typical map subcubes for the elimination of one variable in a product term.
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Typical map subcubes for the elimination of two variables in a product term.
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Typical map subcubes for the elimination of three variables in a product term.
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Addition
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Adder
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You can see that the carry out is correct with a Karnaugh map if it is not obvious already
bc
00 01 11 10
0 0 0 1 0
a
1 0 1 1 1
You have a column of two 1’s that gives bc, a left most row of two 1’s that gives ac and a right most row of two 1’s that gives ab
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Exclusive-Or
• Truth table
x y x xor y (x xor y)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
• Equation
x xor y = x’y + xy’
Where xy means x and y and x + y means x or y
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Exclusive-or continued
The following equation can be represented as (a xor b) xor carryin
Proof: (a xor b) xor ci = (ab’ + a’b) ci’ + (ab’ + a’b)’ ci = (ab’ + a’b) ci’ + (a’b’ + ab) ci .
Note it is easily shown that (a xor b)’ = a’b’ + ab
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Realization of a full binary adder
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Parallel (Ripple) binary adder
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A 32-bit Ripple Carry Adder/Subtractor
Remember 2’s complement is just
complement all the bits
add a 1 in the least significant bit
A 0111 0111 B - 0110 +
1-bit FA S0
c0=carry_in
c1
1-bit FA S1
c2
1-bit FA S2
c3
c32=carry_out
1-bit FA S31
c31
. .
.
A0
A1
A2
A31
B0
B1
B2
B31
add/sub
B0
control(0=add,1=sub) B0 if control =
0, !B0 if control = 1
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• Let's build an ALU to support the and and or instructions
– we'll just build a 1 bit ALU, and use 32 of them
• For AND just use an AND gate and
• for OR just use an OR gate
b
a
operation
result
op a b res
An ALU (arithmetic logic unit)
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• Selects one of the inputs to be the output, based on a control input
• S causes A or B to be selected.
• Lets build our ALU using a MUX:
S
CA
B0
1
Review: The Multiplexor
note: we call this a 2-input mux even though it has 3 inputs!
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• Not easy to decide the “best” way to build something
– Don't want too many inputs to a single gate
– Don’t want to have to go through too many gates
– for our purposes, ease of comprehension is important
• Let's look at a 1-bit ALU for addition:
• How could we build a 1-bit ALU for add, and, and or?
• How could we build a 32-bit ALU?
Different Implementations
cout = a b + a cin + b cin
sum = a xor b xor cin
Sum
CarryIn
CarryOut
a
b
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Building a 32 bit ALU
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
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• Two's complement approach: just negate b and add.
• How do we negate?
• A very clever solution:
What about subtraction (a – b) ?
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
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Subtractor circuit from modified adder
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Binary adder/subtractor
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Adding a NOR function
• Can also choose to invert a. How do we get “a NOR b” ?
• Invert both a and b and input to an and gate since (a + b)’ = a’b’
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2+
Result
1
0
Ainvert
1
0
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• Need to support the set-on-less-than instruction (slt)
– remember: slt is an arithmetic instruction
– produces a 1 if rs < rt and 0 otherwise
– use subtraction: (a - b) < 0 implies a < b
• Need to support test for equality (beq $t5, $t6, $t7)
– use subtraction: (a - b) = 0 implies a = b
Tailoring the ALU to the MIPS
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Supporting slt Can we figure out the idea?
Binvert
a
b
CarryIn
Operation
1
0
2+
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
Handling the most significantbit
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All other bits for slt
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2+
Result
1
0
Ainvert
1
0
3Less
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a0
Operation
CarryInALU0Less
CarryOut
b0
CarryIn
a1 CarryInALU1Less
CarryOut
b1
Result0
Result1
a2 CarryInALU2Less
CarryOut
b2
a31 CarryInALU31Less
b31
Result2
Result31
......
...
BinvertAinvert
0
0
0 Overflow
Set
CarryIn
Supporting slt
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Equality Test
• If a – b = 0 in the slt test the two numbers are equal. One can add a test for this by setting an output flag, zero = 1 if the two values are equal and to 0 otherwise.
• Therefore zero can be defined by
Zero = (Result31 + Result30 + … + Result0)’
• It can then be added as output as in the following diagram.
![Page 40: 1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.](https://reader035.fdocuments.us/reader035/viewer/2022070402/56649f275503460f94c3ed6d/html5/thumbnails/40.jpg)
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Equality
• Notice control lines:
0000 = and0001 = or0010 = add0110 = subtract0111 = slt1100 = NOR
• The right two bits
are the operation
•Note: zero is a 1
when the result
is zero!
a0
Operation
CarryInALU0Less
CarryOut
b0
a1 CarryInALU1Less
CarryOut
b1
Result0
Result1
a2 CarryInALU2Less
CarryOut
b2
a31 CarryInALU31Less
b31
Result2
Result31
......
...
Bnegate
Ainvert
0
0
0 Overflow
Set
CarryIn...
...Zero
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Conclusion
• We can build an ALU to support the MIPS instruction set
– key idea: use multiplexor to select the output we want
– we can efficiently perform subtraction using two’s complement
– we can replicate a 1-bit ALU to produce a 32-bit ALU
• Important points about hardware
– all of the gates are always working
– the speed of a gate is affected by the number of inputs to the gate
– the speed of a circuit is affected by the number of gates in series(on the “critical path” or the “deepest level of logic”)
• Our primary focus: comprehension, however,– Clever changes to organization can improve performance
(similar to using better algorithms in software)– We saw this in multiplication, let’s look at addition now
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Reading material for next time
• PH 3: B.6-B.11