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Introduction to Time Dependent Dielectric Breakdown in Digital Circuits

• Traps generated under the influence of electric field

• Gate dielectric no longer a reliable insulator

• Statistical process requires large # of tests for characterization

n+ n+

0V0VVCC

TrapConduction

Path

Stressed NMOS Cross Section Breakdown in Digital Circuits

Time-to-Breakdown CDFs

Breakdown IGATE paths

2

An Array-Based Test Circuit for Fully Automated TDDB Characterization

• Measure 32x32 array of stressed transistors in parallel without a probe station

• 16b results scanned out and stored for post-processing• Efficient collection of failure statistics by running a

simple control program

Wafer Probe StationProposed System

Save:(1) Time(2) $$$$

32x32 Array of Stress

Cells+

Selection Logic

SC

AN

OU

T

A/D Current Monitor

Stress Cell Abstraction

Stressed Device

VSTRESS

IG

Bitlin

e

Select

3

Measured TBD Results

• Array-based design define a CDF with a single test and check spatial correlation

• Parallel stressing large experiment speedup

• Cheap & accessible test setup

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-2

-1

0

1

2

-1 1 3 5 7 9 11 13

TBD or TFAIL (ln(s))

ln(-

ln(1

-F))

3.8V through 4.3V stress

30oCln

(-ln

(1-C

DF

))

TBD or TFAIL (ln(a.u.))-2 0 2 4 6 8 10 12

2

1

0

-1

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(1) (2)

(3) (4)

Fast Statistical Characterization Analysis of Spatial Correlation

Measurement Lab Setup