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Freeha Azmat

Saba Zia

Dec 02, 2008

Learning SystemC

AgendaInstallationIntroductionFrom Verilog to SystemCCounter as an ExampleComplete SystemC Modeling

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Installation on Linux Download System2.2 from www.systemc.org Run following commands in terminal

cd systemC-2.2 mkdir objdir cd objdir setenv CXX g++ ./configure Gmake debug Gmake instaal Gmake check

Download dinotrace from www.veripool.com/dinotrace tar xvf dinotrace*.tg*z cd dinotrace* ./configure make # Test ./dinotrace traces/ascii.tra make install

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Introduction :System C :

Is a C++ Library for system Level ModelingSupports various abstraction Layers

System C is used for :Fast and efficient designsSystem verification

SystemC VS C++

•Sequential Language

•Not suitable for complex and detailed systems

•Data Types are not suitable for Hardware Implementation

•Parallel Processing is possible

•Incorporate delays, Clocks or Time

•Data Types dedicated to Hardware modeling e.g bit, vector types as well as fixed point types.

System CC ++

SystemC implementation• Modules• Processes• Ports and Interfaces• Channels

Modules :Is a C++ ClassEncapsulates hardware /software

descriptionAny Modules has to be derived from the

existing class sc_module.SystemC modules are analogous to verilog

modules or VHDL entity / architecture pair.

Modules communicate to other modules via ports.

Ports and Interfaces :

Ports are defined as objects inside a modulePublically available to the outside world

through the use of public Keyword.Predefined Ports:

sc_in<>,sc_out<>,sc_inout<>,sc_fifo_in<>,sc_fifo_out<>

Example :sc_in<bool>clk;User Defined Ports are defined with the help of

sc_port class Example:Sc_port <sc_signal_in_if<bool>, 1>

clk;

Processes :Two kinds of Processes :SC_METHOD: cannot be suspended during its execution

Once the execution of SC_METHOD as been performed it halts and waits for new activities on its sensitivity listSimilar to Verilog always block

SC_THREAD :Can be suspended during execution and resumed at a

later stageSC_THREAD only executes once during simulation and

then suspendsSimilar to Verilog initial Block

Channels :

SystemC ‘s communication Medium.Modules communicate via ports and channelsThey are similar to Verilog wire and VHDL

signal System C provides a exhaustive range of pre-

defined channels for generic uses such as sc_signal.

This Feature of language differentiate it from VHDL and Verilog

From Verilog to SystemC

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module name();// module functionalityendmodule

input A,B;output F;reg [3:0] G;

always @(posedge clk)begin//process sensitive //to rising edge of clock //inputend

SC_MODULE(name){//module functionality}

sc_in<bool> A,B;sc_out<bool> F;sc_uint<4> G;

SC_CTOR(name){//process to executeSC_METHOD(myfunc);//sensitive to clocksensitive<<clk.pos();}

From Verilog to SystemC

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add inst(.F(F),.A(A),.B(B));

always @ ()beginend

add inst;SC_CTOR(name):inst(“INST”){inst.A(A);inst.B(B);inst.F(F);}

SC_METHOD(myfunc);

Initialbeginend

SC_THREAD (myfunc);

Counter

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#include <systemc.h>

SC_MODULE(counter){

sc_in_clk clk; sc_in<bool>reset;sc_out<sc_uint<4> > counter_out; sc_uint<4> count;

SC_CTOR(counter){SC_METHOD(myfunc);sensitive<<clk.pos();sensitive<<reset;}

void myfunc(){count=0;if(reset.read()==1)counter_out.write(count);elsecount =count + 1;counter_out.write(count);cout<<counter_out.read()<<endl;}};

int sc_main(int argc,char *argv[]){counter c("hello");c.myfunc();sc_start();return(0);}

module counter(clk,reset,counter_out);

input clk;input reset;output [3:0]counter_out;reg [3:0]counter_out;

always @(posedge clk or negedge reset)begin

if(!reset)counter_out<=0;elsecounter_out<=counter_out + 1;

end

endmodule

Complete SystemC Model

14REF:Introduction to SystemC by Deian Tabakov Rice University Houston, TX

Stimulus Generator

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/************************stimulus.h *********************/#include "systemc.h"SC_MODULE(stim) {sc_out<bool> A, B;sc_in<bool> Clk;

void StimGen() {A.write(false);B.write(false);wait(); // wait for the next clock tickA.write(false);B.write(true);wait(); // wait for the next clock tick...sc_stop(); // notify kernel to stop simulation}

SC_CTOR(stim) {SC_THREAD(StimGen);sensitive << Clk.pos();}}; REF:Introduction to SystemC by Deian Tabakov Rice University Houston, TX

Monitor

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/************************monitor.h *********************/

#include "systemc.h"SC_MODULE(mon) {sc_in<bool> A, B, F;sc_in_clk Clk;void Monitor() {while(1) {wait();cout << sc_time_stamp() << "\t " << A.read()<< " " << B.read() << " " << F.read() << endl;}}SC_CTOR(mon) {SC_THREAD(Monitor);sensitive << Clk.pos();cout << "Time\t A B F" << endl;}};

REF:Introduction to SystemC by Deian Tabakov Rice University Houston, TX

Complete XOR Model

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#include "stim.h"#include "exor.h"#include "mon.h“

int sc_main(int argc, char* argv[]) {sc_signal<bool> ASig, BSig, FSig;sc_clock TestClk("TestClock", 10, SC_NS, 0.5);

stim Stim1("Stimulus"); mon Monitor1("Monitor");Stim1.A(ASig); Monitor1.A(ASig);Stim1.B(BSig); Monitor1.B(BSig);Stim1.Clk(TestClk); Monitor1.F(FSig);Monitor1.Clk(TestClk);

exor DUV("exor");DUV.A(ASig);DUV.B(BSig);DUV.F(FSig);sc_start(); // run foreverreturn 0;}

REF:Introduction to SystemC by Deian Tabakov Rice University Houston, TX

Simulation in Terminal

18REF:Introduction to SystemC by Deian Tabakov Rice University Houston, TX