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EGRE 254 Digital Logic DesignLecture 1

Dr. Jerry H. Tucker

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Web page• Class handouts, announcements, and other

information will be posted on the class web page at http://www.people.vcu.edu/~jhtucker/s09-egre254/index.html.

• Bookmark and monitor this page! There is a link to it on my home page which you can find by doing a Google search for Jerry Tucker.

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Labs• Everyone needs to be registered for Lab.

– Either the 2:00 or 4:00 sessions on Thursday.– Due to the class size the lab will actually be divided into three

sections, however, you must be registered for the original official time.

– Normally lab will be in room 237, but occasionally may be in room 337.

– Monitor the class web page for changes in lab location if there is no announcement go to room 237.

– Lab report guidelines are posted on the class web page.– Not all labs will require a lab report.– Most labs will be conducted with a partner.– You should select a lab partner by next week.

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Textbook• We will use Digital Design Principles and Practices either 3rd or 4th

editions by John Wakerly. • The book may contain a CD with Xilinx software. This software is

obsolete. Don’t bother to install it. You may want to go to http://www.xilinx.com/support/download/index.htm register and download and install the free ISEWebPack and the ModelSim MXE simulator on your home computer.

• You may also want to download and install the evaluation version of Orcad form http://www.cadence.com/downloads/orcad/requestform.aspx?dl=orcadDemo

• We will use this software in some labs.

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Final course grades will be determined as follows:Homework 10%Laboratory 10%Quizzes (2) 50%Final exam 30%Some curving may be used to determine the final letter grade for this class. You

may expect the grade dividing points to be as follows: Between A and B: 90-93. Between B and C: 80-85.Between C and D: 70-75.Between D and F: 60-65.The grade dividing points on the curve will be determined primarily by gaps in

the distribution of the final average. It is not predetermined that a certain number of students will receive a given grade.

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Digital logic design (DLD)• In this class take time to understand the fundamental

concepts and don’t get behind.• If you do this, DLD will be an easy and interesting course.• Digital systems are simpler and better behaved that analog

systems. (Provided you follow the rules.)• This is because in digital systems we deal with only two

levels referred to as “0” and “1”.– Sometimes the “0” level is referred to as “false” and the “1” lever

as true.– In logic circuits voltages levels correspond to the “0” and “1”.

Typical “0” is a voltage near 0 volts, and “1” is a higher voltage such as 5 volts.

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Digital Circuits• Digital Circuits are divided into two major

classifications. • Combinational

– Consist of logic gates with no feedback.– Output depends only on present input.

• Sequential– Contain flip-flops or gates with feedback.– Output depends on both present input and previous

inputs.– Sequential circuits have memory.

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23

U1A

74LS00

9

108

U1C

74LS00

4

56

U1B

74LS001 2

U2A

74LS06

1

23

U1A

74LS00

9

108

U1C

74LS00

4

56

U1B

74LS001 2

U2A

74LS06Q

1D

2

CLK3

DFF

J1

CLK12

K4 Q

3

Q2

CLR13

74LS107

8

1

23

U2A

74LS00

12

45

6

U3A

74LS20

We will typically use NAND gates and the 74LS logic family. All other gates can be implemented using NAND gates. 74LS gate outputs can drive about twenty 74LS inputs. In practice you probably should not drive much more that ten inputs.

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12

0.0 V

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Interfacing to non 74LS devices. Consider driving an LED.

VCC

R2R

74LS04

1 2

D2

LED

74LS04

1 2

D1

LEDR3R

Or

Dose it make any difference?

IOH = -0.4 ma max

IOL = 4.0 ma max for 74

IOL = 8.0 ma max for 54

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Operating region

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Pin count as seen from the top. Notice notch!

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Field Programmable Gate Arrays (FPGA’s) may contain the equivalent of millions of gates in one IC.

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