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1 Design Process

VHDL Compiler, a member of the Synopsys HDL Compiler family,translates and optimizes a VHDL description to an internalgate-level equivalent. This representation is then compiled withthe Synopsys Design Compiler Family to produce an optimizedgate-level design in a given ASIC technology.

Conversely, an existing technology-dependent gate-leveldescription (such as a netlist) can be read by Design Compil-er, then written out as a technology-independent VHDLdescription by VHDL Compiler. This translation capability iscalled reverse synthesis; it provides a powerful means ofleveraging existing designs.

VHDL Compiler Reference V3.4


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To work with VHDL, familiarize yourself with the followingconcepts:

Hardware Description Languages About VHDL About VHDL Compiler Using VHDL Compiler with Design Compiler A Model of the Design Process VHDL Examples Design Problem VHDL Design Description Synthesizing the Example VHDL Design

The United States Department of Defense, as part of its Very-High-Speed Integrated Circuit (VHSIC) program, developedVHSIC HDL (VHDL) in 1982. VHDL describes the behavior,function, and inputs and outputs of a digital circuit design.VHDL is similar in style and syntax to modern programminglanguages, but includes many hardware-specific constructs.Appendix A contains sample VHDL designs, with schematicsof their synthesized circuits.

VHDL Compiler reads and parses the supported VHDL syntax.Appendix C lists all VHDL constructs with the level of Synopsyssupport for each.



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Hardware Description LanguagesHardware description languages (HDLs) are used to describethe architecture and behavior of discrete electronic systems.

HDLs were developed to deal with increasingly complexdesigns. An analogy is often made to the history of what canbe called software description languages, from machinecode (transistors and solder), to assembly language (netlists),to high-level languages (HDLs).

Top-down, HDL-based system design is most useful in largeprojects, where several designers or teams of designers areworking concurrently. HDLs provide structured development.After major architectural decisions have been made, andmajor components and their connections have been identi-fied, work can proceed independently on subprojects.

Typical Uses for HDLsHDLs typically support a mixed-level description where struc-tural or netlist constructs can be mixed with behavioral oralgorithmic descriptions. With this mixed-level capability, youcan describe system architectures at a high level of abstrac-tion; then incrementally refine a design into a particularcomponent-level or gate-level implementation. Alternatively,you can read an HDL design description into the SynopsysDesign Compiler, then direct the compiler to synthesize agate-level implementation automatically.



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Advantages of HDLsA design methodology that uses HDLs has several fundamen-tal advantages over a traditional gate-level design method-ology. Among the advantages are the following:

� You can verify design functionality early in the designprocess, and immediately simulate a design written asan HDL description. Design simulation at this higher level,before implementation at the gate-level, allows you totest architectural and design decisions.

� By using VHDL Compiler with Synopsys’ logic synthesis,you can automatically convert a VHDL description to agate-level implementation in a given technology. Thismethodology eliminates the former gate-level designbottleneck and reduces circuit design time and errorsintroduced when hand-translating a VHDL specificationto gates. With Synopsys’ logic optimization, you canautomatically transform a synthesized design to a small-er or faster circuit. You can apply information gainedfrom the synthesized and optimized circuits back to theVHDL description, perhaps to fine-tune architecturaldecisions. Synopsys Design Compiler, which is describedin the , provides logic synthesis and optimization.

� HDL descriptions provide technology-independentdocumentation of a design and its functionality. An HDLdescription is more easily read and understood than anetlist or schematic description. Since the initial HDLdesign description is technology-independent, you canlater reuse it to generate the design in a differenttechnology, without having to translate from the originaltechnology.



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� VHDL, like most high-level software languages, providesstrong type checking. A component that expects afour-bit-wide signal type cannot be connected to athree- or five-bit-wide signal; this mismatch causes anerror when the HDL description is compiled. If a vari-able’s range is defined as 1 to 15, an error results fromassigning it a value of 0. Incorrect use of types has beenshown to be a major source of errors in descriptions. Typechecking catches this kind of error in the HDL descriptioneven before a design is generated.

About VHDLVHDL is one of just a few HDLs in widespread use today. VHDLis recognized as a standard HDL by the IEEE (IEEE Standard1076, ratified in 1987) and by the United States Department ofDefense (MIL–STD–454L).

VHDL divides entities (components, circuits, or systems) be-tween an external or visible part (entity name and connec-tions) and an internal or hidden part (entity algorithm andimplementation). After you define the external interface toan entity, other entities can use that entity when they all arebeing developed. This concept of internal and external viewsis central to a VHDL view of system design. An entity is de-fined, with respect to other entities, by its connections andbehavior. You can explore alternate implementations (archi-tectures) of an entity without changing the rest of the design.

After you define an entity for one design, you can reuse it inother designs as needed. You can develop libraries of entitiesfor use by many designs, or for a family of designs.

The VHDL model of hardware is shown in Figure 1–1.



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Figure 1–1 VHDL Hardware Model

Entity

Process Process

(Signals)

Sequential

(Architecture)

Component

red, blue

0 to 15

ProcessCombinational

Processwait ... ;

X and (Y xor Z);

Subprogram

if A

end if; else Y then X

Ports

A VHDL entity (design) has one or more input, output, orinput-output ports that are connected (wired) to neighboringsystems. An entity is itself composed of interconnected enti-ties, processes, and components, all which operate concur-rently. Each entity is defined by a particular architecture,which is composed of VHDL constructs such as arithmetic,signal assignment, or component instantiation statements.

In VHDL, independent processes model sequential (clocked)circuits, such as flip-flops, and combinational (unclocked)circuits, such as AND or XOR gates. Processes can define andcall (instantiate) subprograms (subdesigns). Processes com-municate with each other by signals (wires).



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A signal has a source (driver), one or more destinations (read-ers), and a user-defined type, such as “color” or “numberbetween 0 and 15.”

VHDL provides a broad set of constructs. With VHDL you candescribe discrete electronic systems of varying complexity(systems, boards, chips, modules) with varying levels of ab-straction.

VHDL language constructs are divided into three categoriesby their level of abstraction: behavioral, dataflow, and struc-tural. These categories are described as follows:

behavioralThe functional or algorithmic aspects of a design, ex-pressed in a sequential VHDL process.

dataflowThe view of data as flowing through a design, from inputto output. An operation is defined in terms of a collec-tion of data transformations, expressed as concurrentstatements.

structuralThe view closest to hardware; a model where the com-ponents of a design are interconnected. This view isexpressed by component instantiations.



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About VHDL CompilerVHDL Compiler converts VHDL source code to an internalformat used by the Synopsys Design Compiler. VHDL Compileris accessed in dc_shell or Design Analyzer by executingelaborate and analyze . VHDL Compiler performs two func-tions: translating VHDL to an internal format, and optimizingthe block level representation through various optimizationmethods.

Design Compiler reads the design in internal format fromVHDL Compiler, then optimizes and maps the design’s logicalstructure for a specific ASIC technology library, as shown inFigure 1–2.

Figure 1–2 VHDL Compiler Used with VHDL System Simulator (VSS)and Design Compiler

ASIC TechnologyLibrary

VHDL Compiler

Design Compiler

VHDL Description

(translation, block level

(logical optimizations,technology–specificnetlist /schematic)

optimization)

VHDL System Simulator

(functionality verification)



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A VHDL description is first simulated to verify design function-ality, by using a VHDL simulator such as the Synopsys VSSFamily (VSS Expert or VSS Professional).

When analyzing VHDL design files for simulation you can usevhdlan –spc to verify Synopsys synthesis policy. For moreinformation, refer to the chapter on the VHDL Analyzer in the or the .

VHDL Compiler is called by Design Compiler when you readin or write out a VHDL design. VHDL Compiler synthesizesVHDL descriptions according to the VHDL synthesis policydefined in Chapter 2, “Description Styles.”

The Synopsys VHDL synthesis policy has three parts: designmethodology, design style, and language constructs. You usethe VHDL synthesis policy to produce high quality VHDL-based designs.

Using VHDL Compiler with Design CompilerWhen VHDL Compiler reads a VHDL design, the design isconverted to Design Compiler’s internal database format.When Design Compiler performs logic optimization on adesign, Design Compiler can restructure part or all of thedesign. You control the degree of restructuring. You can keepa design hierarchy intact, move modules up or down thedesign hierarchy, combine modules, or compress the entiredesign into one module.



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After you are in Design Compiler, you can write out anydesign in a variety of formats, including VHDL. Existing gate-level netlists, sets of logic equations, or technology-specificcircuits can be automatically converted to a VHDL descrip-tion. The new VHDL description can serve as documentationof the original design, and you can use it as a starting pointfor reimplementation into a new technology. In addition, youcan give the VHDL description to a VHDL simulator to providecircuit timing information.

A Model of the Design ProcessAn example of a VHDL design session is described below.Starting with a VHDL description (source file), the exampleshows how to execute Design Compiler, read in and optimizea design, view its schematic, and write out the optimizedcircuit description.

Figure 1–3 illustrates a typical design flow that uses VHDLCompiler, Design Compiler, and your VHDL simulator.



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Figure 1–3 Design Flow that Uses VHDL Compiler

VHDL Description

VHDLSimulator

Synopsys VHDLCompiler

Synopsys Design Compiler

VHDLDriver

VHDL Gate-Level Description

VHDL Simulator

SimulationOutput

SimulationOutput

CompareOutput

1

2

4

73

5

6

8

The steps in Figure 1–3 are explained below.

1. Write a design description in the VHDL language. Thisdescription can be a combination of structural andfunctional elements (as shown in Chapter 2, “DescriptionStyles”). This description is used with both the SynopsysVHDL Compiler and your VHDL simulator.



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2. Provide VHDL-language test drivers for your VHDL simula-tor. These drivers supply test vectors for the simulationand gather output data.

3. Simulate the design by using your VHDL simulator toverify the accuracy of the description.

4. Synthesize the VHDL description with VHDL Compiler.VHDL Compiler performs architectural optimizations,then creates an internal representation of the design.

5. Use the Synopsys Design Compiler to produce an opti-mized gate-level description in the target ASIC library.You can optimize the generated circuits to meet thetiming and area constraints you want. This optimizationstep must follow the translation step (step 4) to producean efficient design.

6. Use the Synopsys Design Compiler to output a gate-levelVHDL description. This netlist-style description uses ASICcomponents as the leaf-level cells of the design. Thegate-level description has the same port and moduledefinitions as the original high-level VHDL description.

7. Pass the gate-level VHDL description from step 6 throughyour VHDL simulator. You can use the VHDL simulationdrivers from Step 2 because module and port definitionsare preserved through the translation and optimizationprocesses.

8. Compare the output of the gate-level simulation (step 7)against the output of the original VHDL descriptionsimulation (step 3) to verify that the implementation iscorrect.



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VHDL ExampleThe example that follows is called “Count Zeros—SequentialVersion,” and is taken from Appendix A. The next three sec-tions contain

� A description of the design problem (count the numberof zeros in a sequentially input eight-bit value).

� A listing of a VHDL design description.

� A step-by-step description of how to read in the VHDLdesign description, how to compile (synthesize) the circuit,how to view the resulting schematic, and how to write outthe synthesized circuit description as a VHDL file.

Design ProblemThe Count Zeros example illustrates a design problem wherean eight-bit value is given and the circuit determines

� Exactly one sequence of 0s is in the value.

� The number of 0s in that sequence (if any).

A valid value can have no more than one series of consecu-tive zeros. A value consisting entirely of 1s is defined as a validvalue. If a value is invalid, the zero counter is reset to zero. Forexample, value 00000000 is valid and has eight zeros; value11000111 is valid and has three zeros; value 00111100 is notvalid.



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The circuit accepts the eight-bit data value serially, one bitper clock cycle, by using the DATA and CLK inputs. The othertwo inputs are

� RESET, which resets the circuit (synchronous reset).

� READ, which causes the circuit to begin accepting databits and continue to accept data bits.

The circuit’s three outputs are

� IS_LEGAL, which is TRUE if the data was a valid value.

� COUNT_READY, which is TRUE at the first invalid bit or whenall eight bits have been processed.

� COUNT, the number of zeros (if IS_LEGAL is TRUE). The outputport COUNT is declared with mode BUFFER, so that it canbe read inside the process. OUT ports can only be writtento, not read.

Note:The pathname of the VHDL source file for this example is /synopsys/doc/syn/examples/vhdl/cnt–seq/cnt–seq.vhd ,where /synopsys is the name of your Synopsys rootdirectory.

VHDL Design DescriptionExample 1–1 shows the VHDL source description for the CountZeroes circuit.

Example 1–1 VHDL Design Source File

entity COUNT_SEQ_VHDL is port(DATA, CLK: in BIT; RESET, READ: in BOOLEAN; COUNT: buffer INTEGER range 0 to 8; IS_LEGAL: out BOOLEAN; COUNT_READY: out BOOLEAN);end;



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architecture BEHAVIOR of COUNT_SEQ_VHDL isbegin process variable SEEN_ZERO, SEEN_TRAILING: BOOLEAN; variable BITS_SEEN: INTEGER range 0 to 7; begin wait until CLK’event and CLK = ’1’; if (RESET) then COUNT_READY <= FALSE; IS_LEGAL <= TRUE; –– Signal assignment SEEN_ZERO := FALSE; –– Variable assignment SEEN_TRAILING := FALSE; COUNT <= 0; BITS_SEEN := 0; else if (READ) then if (SEEN_TRAILING and DATA = ’0’) then IS_LEGAL <= FALSE; COUNT <= 0; COUNT_READY <= TRUE; elsif (SEEN_ZERO and DATA = ’1’) then SEEN_TRAILING := TRUE; elsif (DATA = ’0’) then SEEN_ZERO := TRUE; COUNT <= COUNT + 1; end if; if (BITS_SEEN = 7) then COUNT_READY <= TRUE; else BITS_SEEN := BITS_SEEN + 1; end if;

end if; –– if (READ) end if; –– if (RESET) end process;end BEHAVIOR;



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Synthesizing the VHDL DesignTo synthesize a circuit from the VHDL design example, useDesign Analyzer and follow these steps:

1. Start Design Analyzer by entering the following com-mand at your UNIX prompt (%):

% design_analyzer &

The main Design Analyzer window appears as shown inFigure 1–4.

Figure 1–4 Initial Design Analyzer Window



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2. Set your target library and the associated link and sym-bol libraries. For this example, use the generic Synopsysclass library. Move the cursor to Setup , then click the leftmouse button to bring up the Setup menu. Click onDefaults... to bring up the Setup/Defaults dialog.

Add the Synopsys-supplied library directory name /synopsys/libraries/syn to the end of the Search Path

field. Set the Link Library , Target Library , and Symbol

Library fields as shown in Figure 1–5. Click on OK to setthese default values.

Figure 1–5 Setup/Defaults Window



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Click on Cancel to remove the Variables dialog.

3. Analyze the VHDL source file; use the File/Analyze

dialog.



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Enter the directory name /synopsys/doc/syn/examples/

vhdl/cnt–seq/ in the File Name field and click on OK. AnAnalyze window appears with a design_analyzer

prompt.

Click on CANCEL.



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4. Elaborate the VHDL source file by using the File/Elabo-

rate dialog. The Elaborate Design window appears.

Enter the library name WORK in the Library field.

Enter the design name COUNT_SEQ_VHDL (BEHAVIOR) in theDesign field. Click OK.



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An Elaborate window opens to show the status mes-sages and inferred devices (see “Register and Three-State Inference” in Chapter 8) produced by VHDL Com-piler.

After you have reviewed the VHDL report, click on Cancel

to remove the report window.



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5. The design has now been read into memory and trans-lated to an internal (equation-based) format, indicatedby the symbol Y=A+B. The Design Analyzer window nowshows the design’s icon and name (COUNT_SEQ_VHDL).



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6. Click on the design icon to select it, then click on thedown-arrow button (left side of window) to generateand display the symbol view of the design.



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7. Set a constraint for the design. Ask for the minimum areaby using the Attributes/Optimization Constraints/De-

sign Constraints selection.



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The Design Constraints dialog box appears.

Click Apply then Cancel .



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8. Look at the initial (HDL-level) schematic. Click on theschematic view icon.

9. You can see the ports and gates produced by VHDLCompiler from the VHDL description by using HDL Advi-sor. For more information, see the HDL Advisor UserGuide.



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10.Compile the design by using the Tools/Design Optimiza-

tion dialog. Use the default settings and click on OK tostart the compilation.

Delay



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A Compile Log report window shows the compilationstatus. After you review the report, click on Cancel toremove the window.



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11.Display the schematic for the design by clicking on theSchematic View button (small AND gate).

At this point, you can explore the design by using DesignAnalyzer. You can see the critical path, get timing in-formation, highlight all cells or references of a giventype, change circuit constraints, group and ungroupsubsets of the circuit, and get a variety of reports. Seethe for complete information.



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12.Write out the design by using the File/Save As dialog.Enter the new filename in the File Name field, for exam-ple, example.vhdl . Choose the output format you wantfrom the File Format list; in this case, VHDL netlist outputformat.



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13.Quit Design Analyzer by using the File/Quit dialog.

Click on OK to exit Design Analyzer, or Cancel to removethis dialog. The screen is locked when this dialog isdisplayed.

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