1-bit Half Adder 1 - Undergraduate...

17
Logic Design 1 1-bit Half Adder Let's make a 1-bit adder (half adder)… we can think of it as a Boolean function with two inputs and the following defining table: A B Sum 0 0 0 0 1 1 1 0 1 1 1 0 Intro Computer Organization Computer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens Here's the resulting circuit. It's equivalent to the XOR circuit seen earlier. But… in the final row of the truth table above, we've ignored the fact that there's a carry-out bit.

Transcript of 1-bit Half Adder 1 - Undergraduate...

Page 1: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 11-bit Half Adder

Let's make a 1-bit adder (half adder)… we can think of it as a Boolean function with two

inputs and the following defining table:A B Sum

0 0 0

0 1 1

1 0 1

1 1 0

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Here's the resulting circuit.

It's equivalent to the XOR circuit

seen earlier.

But… in the final row of the truth

table above, we've ignored the fact

that there's a carry-out bit.

Page 2: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 2Dealing with the Carry

The carry-out value from the 1-bit sum can also be expressed via a truth table.

However, the result won't be terribly useful unless we also take into account a carry-in.

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

The resulting sum-of-products expressions are:

inininin CBACBACBACBASum ⋅⋅+⋅⋅+⋅⋅+⋅⋅=

CBACBACBACBACarry inininin ⋅⋅+⋅⋅+⋅⋅+⋅⋅=

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

( )

BACACB

BACBACBA

CCBACBACBA

inin

inininin

⋅+⋅+⋅=

⋅+⋅⋅+⋅⋅=

+⋅⋅+⋅⋅+⋅⋅=

Page 3: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 31-bit Full Adder

The expressions for the sum and carry lead to the following unified implementation:

inin

inin

CBACBA

CBACBASum

⋅⋅+⋅⋅+

⋅⋅+⋅⋅=

BACACBCarry ⋅+⋅+⋅=

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

This implementation requires

only two levels of logic

(ignoring the inverters as

customary).

Is there an alternative design

that requires fewer AND/OR

gates? If so, how many levels

does it require?

Page 4: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 4LogiSim Implementation

The previous circuit is easily implemented in LogiSim.

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Page 5: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 5LogiSim Analysis Tool

The Project menu contains an option to analyze the circuit.

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

You may find these useful in verifying the correctness of a circuit.

Page 6: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 61-bit Full Adder as a Module

When building more complex circuits, it is useful to consider sub-circuits as individual,

"black-box" modules. For example:

inin

inin

CBACBA

CBACBASum

⋅⋅+⋅⋅+

⋅⋅+⋅⋅=

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

BACACBCarry ⋅+⋅+⋅=

Page 7: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 7Chaining an 8-bit Adder

An 8-bit adder build by

chaining 1-bit adders:

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

This has one serious shortcoming. The carry bits must ripple

from top to bottom, creating a lag before the result will be

obtained for the final sum bit and carry.

Page 8: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 8Programmable Logic Arrays

We know that every Boolean function can be expressed in sum-of-products form, and it is

obvious that a sum-of-products form can be implemented with two levels of logic, the

first consisting of AND gates and the second of OR gates.

A programmable logic array (PLA) is a structured logic element consisting of a set of N

inputs (and corresponding input complements), and two stages of logic the first generating

P product terms of the inputs and the second generating S sums of the product terms.

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

A PLA can be used to implement a set of

Boolean functions in a compact form.

Any set of k functions on n variables can

be implemented via an m x n array of

AND gates connected to a k x m array of

OR gates, where m is the number of

different product terms that are needed.

AND array

OR array

. . .

. . .

. . .

Page 9: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 9PLA Example

Consider the collection of Boolean functions defined by the following truth table:

Inputs Functions

A B C F G H

0 0 0 0 0 0

0 0 1 1 0 0

0 1 0 1 0 0

0 1 1 1 1 0

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 1 0

1 1 1 1 0 1

Since there are 7 rows in which at least one function is 1, we will need 7 AND gates.

We will need an OR gate to form the output for each function.

Page 10: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 10PLA Example

Here's the PLA:

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

This is advantageous because the functions in question have a significant number of

product terms in common.

Page 11: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 11Read Only Memories

A read-only-memory (ROM) is a decoder-like circuit that takes n bits as input and selects

one of 2n k-bit sequences as its output.

The shape of the ROM is its height, which is 2n, and its width, which is k.

A ROM exactly encodes a truth table.

A ROM is generally larger than the equivalent PLA.

At right is an modular representation of a ROM

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

4 32

At right is an modular representation of a ROM

with height 16, and width 32.

Page 12: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 12Creating a Basic 1-bit ALU

Here's a basic 1-bit ALU:

- user-selectable output

via the MUX

- 01: A AND B

- 10: A OR B

- 11: A + B

- carry-in and carry-out

bits

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

The multiplexor is used to select the desired function the ALU will perform.

Additional features can be incorporated fairly easily.

1-bit full

adder

bits

Page 13: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 13Extending the 1-bit ALU

Let's add some features:

- negation of A and/or B

- A + B, A + -B

(hence, subtraction)

- A NOR B

- user-selectable output via

the MUX

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

- 00: A AND B

- 01: A OR B

- 10: A + B

- 11: SLT

- carry-in and carry-out bits

- output bit for SLT*

- overflow detection*

* implemented ONLY for high-order bit

Page 14: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 14Creating a Multi-bit ALU

As we saw earlier with the adder, we can chain 1-bit ALUs together to produce an ALU

for any width input we desire.

There are a few considerations:

- only the ALU for the high-order bit would include the Set output and the Overflow

detection logic and output.

- the Set output from the high-order ALU will be connected to the Less input of the

low-order ALU in order to implement the SLT instruction

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

low-order ALU in order to implement the SLT instruction

- the addition module still uses a ripple-carry; that should be remedied eventually

Page 15: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 15A 4-bit ALU

Here's a 4-bit ALU created from the extended

1-bit ALU shown earlier:

Here, the ALU is being used to evaluate the slt

instruction on its operands,

setting the result in Result.

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

Note that the InvertB input is

also connected to the CarryIn

port of the low-order 1-bit

ALU module. Why?

Page 16: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 16Supporting Conditional Branch

To support conditional branch we need the slt instruction, and a way to test whether the

inputs are equal (or non-equal). This can be added fairly trivially:

Effectively, this ALU has a

4-bits control mechanism

for selecting the desired

function.

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

InvA InvB FnSel ALU Fn

0 0 00 AND

0 0 01 OR

0 0 10 add

0 1 10 sub

0 1 11 slt

1 1 00 NOR

Page 17: 1-bit Half Adder 1 - Undergraduate Coursescourses.cs.vt.edu/~cs2504/fall2008/Notes/PDF/L17.LogicDesign.pdf · 1-bit Half Adder Logic Design 1 Let's make a 1-bit adder ( half adder)

Logic Design 17Conceptual View of the ALU

From the user perspective, the ALU may be considered as a black box with a relatively

simple interface:

InvA InvB FnSel ALU Fn

0 0 00 AND

0 0 01 OR

0 0 10 add

0 1 10 sub

Intro Computer OrganizationComputer Science Dept Va Tech March 2006 ©2006 McQuain & Ribbens

0 1 11 slt

1 1 00 NOR