1

A Case for Using Signal Transition Graphs for Analysing and Refining

Genetic Networks

Richard Banks, Victor Khomenko and Jason StegglesSchool of Computing Science,

Newcastle University, UK

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Overview• Modelling genetic regulatory networks using

Boolean networks (BNs).• Problems with BN approach.• Asynchronous circuit design techniques.• A refinement approach based on Signal

Transition Graphs (STGs).• Case study on lysis-lysogeny switch in Lambda

phage.• Conclusions and future work.

Modelling Genetic Networks• Genetic regulatory networks

(GRNs) are complex control structures mediating cell function.

• Require practical modelling and analysis techniques.

• Kinetic parameters lacking for construction of meaningful quantitative models.

• Qualitative approaches often used for gaining initial insights.

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Kobiler et. al. 2005

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Boolean Networks• Qualitative model: Boolean networks (BNs).• Regulatory entities abstracted to binary switches.• Behaviour of each switch given by Boolean function over

inputs.

• Synchronous or asynchronous interpretation.• BNs circuits.

a b c [a] [b] [c]

0 0 0 0 0 10 0 1 0 0 10 1 0 1 0 10 1 1 1 0 11 0 0 0 0 01 0 1 0 1 01 1 0 1 0 01 1 1 1 1 0

a

b c

Circuit equations[a] = b[b] = ac[c] = a

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Aim• Synchronous BN interpretation arguably unrealistic.• Asynchronous BNs more realistic, but capture too rich,

non-deterministic behaviour unrealisable in practice.• Require realistic qualitative modelling approach with

appropriate analysis techniques and tools.

Solution:• Use asynchronous approach.• Remove unrealisable behaviour using techniques from asynchronous circuit design.• Based on speed-independent (SI) circuits

functions correctly regardless of gate delays.

Solution:• Use asynchronous approach.• Remove unrealisable behaviour using techniques from asynchronous circuit design.• Based on speed-independent (SI) circuits

functions correctly regardless of gate delays.

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STG

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1b = 1

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1b = 1c = 1

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1b = 1c = 1a = 0

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1b = 1c = 1a = 0b = 0

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STGa = 1b = 1c = 1a = 0b = 0c = 0

Asynchronous Circuit Design• Signal transition graphs (STGs) are specification language

based on Petri nets well founded techniques/tools.• Regulatory entities Boolean variables signals.• Input, output and internal signals (output + internal = local).• Transitions model signal change, e.g. a+ from a=0 to a=1.

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Ca

b

c

Environment

a+ b+

c+

a- b-

c-

STG

Capture contract between circuit and environment

a = 1b = 1c = 1a = 0b = 0c = 0

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Relationship between BNs and STGs

Circuit equation (BN)[c] = ab + c(a + b)

• BN STG straightforward.• Equation loses environmental information STGs more useful for analysis

a+ b+

c+

a- b-

c- a+a-

b-b+

c-c+

Models most generalenvironment!

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Speed-Independent (SI) Circuits• Function correctly independent of

gate delay.• SI requires output persistency (OP):

– no choices involving local transitions.

• OP violation non-determinism.• Choices between input transitions

models non-deterministic decision in the environment – OK.

a+ b+

c+

a- b-

c-

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Speed-Independent (SI) Circuits• Function correctly independent of

gate delay.• SI requires output persistency (OP):

– no choices involving local transitions.

• OP violation non-determinism.• Choices between input transitions

models non-deterministic decision in the environment – OK.

Speed-independent (SI)in specified environment

a+ b+

c+

a- b-

c-

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Speed-Independent (SI) Circuits• Function correctly independent of

gate delay.• SI requires output persistency (OP):

– no choices involving local transitions.

• OP violation non-determinism.• Choices between input transitions

models non-deterministic decision in the environment – OK.

a+ b+

c+

a- b-

c-

a-

Add extra transition a-

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Speed-Independent (SI) Circuits• Function correctly independent of

gate delay.• SI requires output persistency (OP):

– no choices involving local transitions.

• OP violation non-determinism.• Choices between input transitions

models non-deterministic decision in the environment – OK.

Not SI: c+ disabled by a-

a+ b+

c+

a- b-

c-

a-

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Speed-Independent (SI) Circuits• Function correctly independent of

gate delay.• SI requires output persistency (OP):

– no choices involving local transitions.

• OP violation non-determinism.• Choices between input transitions

models non-deterministic decision in the environment – OK.

• Exception: choices involving only local transitions can be left in model:– should be documented;– if represent stochastic phenomenon, can

be handled in SI manner with arbiters.

a+ b+

c+

a- b-

c-

a-

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Approach Overview

BN STG SI Circuit

Identify OP violations (auto)

User assumptions (priorities)

(auto)

PN analysis tools

STG analysis tools

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Refinement Approach

a+a-

b-b+

c-c+[c] = ab + c(a + b)

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Refinement Approach

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

a+a-

b-b+

c-c+

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Refinement Approach

User adds priorities:• slow environment• relative reaction rates

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

a+a-

b-b+

c-c+

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Refinement Approach

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

User adds priorities:• slow environment• relative reaction rates

a+a-

b-b+

c-c+

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Refinement Approach

E.g.assume c+ faster than a-

a+a-

b-b+

c-c+

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

User adds priorities:• slow environment• relative reaction rates

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Refinement Approach

Prioritise c+ over a- when both enabled by capturing when a- can fire but c+ cannot.

a+a-

b-b+

c-c+

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

User adds priorities:• slow environment• relative reaction rates

E.g.assume c+ faster than a-

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Refinement Approach

Prioritise c+ over a- when both enabled by capturing when a- can fire but c+ cannot.

Identify all OP violations: c+ disabled by a- c+ disabled by b- c- disabled by a+ c- disabled by b+

User adds priorities:• slow environment• relative reaction rates

E.g.assume c+ faster than a-

a+a-

b-b+

c-c+

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All OP Violations Resolved

Refine OP violations (automated)

Priorities assumed:

c+ faster than a-, c+ faster than b-

c- faster than a+, c- faster than b+

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Resynthesized STG

• Optimised using circuit synthesis tool Petrify.• STG is SI and, surprisingly, contains more behaviour

than original, i.e. can cope with more demanding environment than one intended.

a-

a+ b+

b-

b+/1 a+/1

c-

c+

a+/2

a-/1 b-/1

b+/2

a-/2b-/2

30Case Study: Lysis-Lysogeny Switch in Lambda Phage

Inputs: CI (repressor)Internal: CII (trans. activator),

Int (integrase), Xis (excisionase)

Outputs: Intg (integrated)

[CII] = CI

[Int] = CII + CI

[Xis] = CI

[Intg] = Intg Int + Intg(Int + Xis)

Circuit

Ptashne, 2004

Thomas et. al.,1990

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OP Violations in Lambda Phage

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OP Violations in Lambda Phage

OP violations:Xis+ disabled by CI+ Xis− disabled by CI− Int+ disabled by CI +Int− disabled by CI −CII+ disabled by CI+CII − disabled by CI−Intg− disabled by Int−Intg− disabled by Xis−Intg+ disabled by Int−Int+/1 disabled by CII−

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OP Violations in Lambda Phage

Environm

ent

OP violations:Xis+ disabled by CI+ Xis− disabled by CI− Int+ disabled by CI +Int− disabled by CI −CII+ disabled by CI+CII − disabled by CI−Intg− disabled by Int−Intg− disabled by Xis−Intg+ disabled by Int−Int+/1 disabled by CII−

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OP Violations in Lambda Phage

Environm

ent

OP violations:Xis+ disabled by CI+ Xis− disabled by CI− Int+ disabled by CI +Int− disabled by CI −CII+ disabled by CI+CII − disabled by CI−Intg− disabled by Int−Intg− disabled by Xis−Intg+ disabled by Int−Int+/1 disabled by CII−

Resolve by assuming slow environment

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OP Violations in Lambda Phage

Environm

ent

OP violations:Xis+ disabled by CI+ Xis− disabled by CI− Int+ disabled by CI +Int− disabled by CI −CII+ disabled by CI+CII − disabled by CI−Intg− disabled by Int−Intg− disabled by Xis−Intg+ disabled by Int−Int+/1 disabled by CII−

Resolve by assuming slow environment

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Final SI STG• Much less cluttered.• Remaining OP violations:

Intg− disabled by Int− Intg− disabled by Xis− Intg+ disabled by Int−

Heart of lysis-lysogeny switch (stochastic) • Can now be analysed

further with PN and STG tools.

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Conclusions• BN STG SI STG.• Framework for obtaining realistic models of GRNs using

notion of SI circuits:– refine unrealisable behaviour based on user knowledge;– identifying and documenting missing information.

• STG construction and refinement automated.• Re-use existing PN and STG tools/techniques for analysis.• Not all OP violations may always be resolved

document.• Future work:

– further case studies;– generalise approach to multi-valued networks;– investigate application to synthetic biology.

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Thanks

A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Network

Richard Banks, Victor Khomenko and Jason Steggles

http://bioinf.ncl.ac.uk/gnapn/