1 8-Bit Binary-to-Gray Code Converter Mike Wong Scott Echols Advisor: Dave Parent May 11, 2005.
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Transcript of 1 8-Bit Binary-to-Gray Code Converter Mike Wong Scott Echols Advisor: Dave Parent May 11, 2005.
![Page 1: 1 8-Bit Binary-to-Gray Code Converter Mike Wong Scott Echols Advisor: Dave Parent May 11, 2005.](https://reader035.fdocuments.us/reader035/viewer/2022081506/56649d545503460f94a30aed/html5/thumbnails/1.jpg)
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8-Bit Binary-to-Gray Code Converter
Mike WongScott Echols
Advisor: Dave ParentMay 11, 2005
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Agenda
• Abstract• Introduction
– Why– Simple Theory– Back Ground information
• Summary of Results• Project (Experimental) Details• Results• Cost Analysis• Conclusions
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Abstract
• 8-Bit Gray Code Converter – Operates at 200 MHz– Uses 5.65 mW of Power – Occupies an area of 346x154 m2
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Introduction
• To convert a series of 8 binary numbers into Gray Code.
• Used in digital communication.
• When counting, only one bit is changed.– Effect of error minimized.
• Uses the basic principles learned in EE166.
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Introduction• Truth Table:
#
Binary Gray Code
3rd bit 2nd bit 1st bit Bit X Bit Y Bit Z
0 0 0 0 0 0 0
1 0 0 1 0 0 1
2 0 1 0 0 1 1
3 0 1 1 0 1 0
4 1 0 0 1 1 0
5 1 0 1 1 1 1
6 1 1 0 1 0 1
7 1 1 1 1 0 0
YBitbitndbitrd 23
)()(3 MSBorXBitMSBorbitrd
Bit A
Bit B
XOR
0 0 0
0 1 1
1 0 1
1 1 0
ZBitbitstbitnd 12
XOR Logic
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Longest Path Calculations
nsns
PHL 625.08
5 Note: All widths are in microns
and capacitances in fF
Logic Level
Gate Cg to Drive
#CDNs #CDPs #LNs #LPs WN (H.C)
WP (H.C)
WN (S)
WP (S)
WN (L)
WP (L)
Cg of gate
1 NAND3 30 5 3 3 1 1.80 1.80 1.8 1.8 1.8 1.8 6.01 2 NAND3 6.01 5 3 3 1 0.82 0.82 1.5 1.5 1.5 1.5 5.03 3 INV 5.03 1 1 1 1 0.12 0.20 1.5 1.5 1.5 1.5 5.03 4 NOR 5.03 4 6 1 2 0.25 0.51 1.5 1.5 1.5 1.5 5.03 5 NOR 5.03 4 6 1 2 0.25 0.51 1.5 1.5 1.5 1.5 5.03 6 INV 5.03 1 1 1 1 0.12 0.20 1.5 1.5 1.5 1.5 5.03 7 NAND3 5.03 5 3 3 1 0.78 0.78 1.5 1.5 1.5 1.5 5.03 8 NAND3 5.03 5 3 3 1 0.78 0.78 1.5 1.5 1.5 1.5 5.03
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Schematic
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Layout
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Verification
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Simulations
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Cost Analysis
• Time spent on each phase of the project– verifying logic – 1 week– verifying timing – 1 week– layout – 2 weeks– post extracted timing – 1 day
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Lessons Learned
• Use DRC often for the layout.
• Consult with Dr. Parent when needed.
• Start early and don’t procrastinate.
• Smaller groups are easier to manage.
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Summary
• Incorporated many of the principles taught in EE166.
• Designed a circuit that converts binary coded numbers to the Gray Code.
• Implemented logic design into layout form of CMOS technology.
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Acknowledgements
• Thanks to:– Cadence Design Systems for the VLSI lab– Synopsys for Software donation.– Professor Parent.