1 4-bit ALU Advisor: Prof. David W. Parent Presentation Date: 12/05/05 Roberto Reyes Sunil Adhikari...
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Transcript of 1 4-bit ALU Advisor: Prof. David W. Parent Presentation Date: 12/05/05 Roberto Reyes Sunil Adhikari...
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4-bit ALU
Advisor: Prof. David W. Parent
Presentation Date: 12/05/05
Roberto ReyesSunil AdhikariSamir PatelYesha Patel
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Agenda Abstract Introduction
WhySimple theory
Project detailsSchematicsLayout Verification: DRC, Extract, LVSSimulation Results
Cost Analysis Conclusion Lessons Learned
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Abstract 4-bit ALU
• Gates Used: NAND, XOR, AOI, NOR, INV• Number of Operations: 16-Logic, 16-Arithmetic• Driven load: 30fF• Clock Frequency: 222 MHz• Power Density: 13.54 mW/cm2
• Area: 430.00 x 833.10 µm2
Specifications:• Frequency: 200 MHz• Max Power: 20W/Cm2
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Goal
Design 4-bit ALU using Cadence Tools
Implementation of concepts learned in EE 166 – Design of CMOS Digital Integrated Circuit
To improve the Motorola designing criteria from previous projects
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Introduction ALU is a fundamental unit of many
combinational circuits which performs logical and arithmetic operations.
Cadence Tools were used to verify the Design and Simulation.
CMOS Design high speed less power
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Project Summary
Using particular widths for transistors
Consuming less power than previous designs
Achieving higher operating frequency than previous project
Tried minimizing area compared to the previous projects
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Project Flowchart
Longest Path
Gate Level Schematic
Transistor Level Schematic
LayoutDRC
Extracted LVS
Post Extractio
n
NC Verilog
Verify ALU DesignPower Check
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Gate Level SchematicS0S1
S3S2
B3
A3
B2
B1
A2
A1
B0
A0M
Cn
G
Cn+4
P
F3
F2
F1
F0
A=B
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Longest Path CalculationsCELL BIT# Cg+Cint phl (s) plh (s) NSN NSP N M R WN (cm) WP (cm)
INV3 1 3.0000E-14 2.31E-10 2.31E-10 1 1 1 1 1.772 1.50E-04 2.66E-04
NAND_4 2 6.9788E-15 3.85E-10 3.85E-10 4 1 7 4 0.433 7.84E-04 3.40E-04
XOR_2 3 1.8863E-14 3.85E-10 3.85E-10 2 2 4 6 1.734 3.27E-04 5.66E-04
INV_XOR 4 2.9962E-14 1.54E-10 1.54E-10 1 1 1 1 1.792 1.85E-04 3.32E-04
NOR_2 5 2.9962E-14 3.08E-10 3.08E-10 1 2 2 3 3.506 1.50E-04 5.26E-04
NOR_3 5 1.1343E-14 3.85E-10 3.85E-10 1 3 3 5 5.202 1.50E-04 7.80E-04
NOR_4 5 3.1223E-14 6.92E-10 6.92E-10 1 4 4 7 6.628 1.50E-04 9.94E-04
INV2 6 1.9201E-14 1.54E-10 1.54E-10 1 1 1 1 1.792 1.50E-04 2.69E-04
NAND_2 7 1.6054E-14 2.31E-10 2.31E-10 2 1 3 2 0.886 2.22E-04 1.97E-04
NAND_3 7 9.0204E-15 3.08E-10 3.08E-10 3 1 5 3 0.584 3.18E-04 1.86E-04
NAND_4 7 1.8928E-14 4.62E-10 4.62E-10 4 1 7 4 0.429 5.15E-04 2.21E-04
NAND_5 7 1.4359E-14 6.15E-10 6.15E-10 5 1 9 5 0.335 4.95E-04 1.66E-04
AOI_1 8 2.4204E-14 6.15E-10 6.15E-10 3 2 10 9 1.117 6.51E-04 7.27E-04
AOI_2 8 2.5131E-14 6.15E-10 6.15E-10 2 3 7 8 2.514 2.87E-04 7.21E-04
INV1 9 3.3834E-14 1.54E-10 1.54E-10 1 1 1 1 1.792 2.08E-04 3.72E-04
NAND_4 1 3.0000E-14 5.71E-10 5.71E-10 4 1 7 4 4.22 4.04E-4 1.71E-4
Shortest Path
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Transistor Level Schematic
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Layout
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DRC
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LVS Check
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Extracted View of Schematic
Function VerificationFunction Table
L = LOW VoltageH = HIGH Voltage* Each bit is shifted to the next most significant position**Arithmetic Operations expressed in 2s complement notation.
Table used from http://www.mil.ufl.edu/courses/eel4712/docs/74LS181.pdf
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Logic VerificationLogic Operation : A B Keeping S3 = H, S2 = L, S1 = L, S0 = H, M= H
A11
1
0
0
0
0
0
01
1
0
0
+
RSET
A0
CK
A2
A3
B0
B1
B2
B3
F1
F0
F2
F3
τphl = 2.62nsτplh = 2.64ns
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Logic VerificationArithmetic Operation : A + B
Keeping S3 = H, S2 = L, S1 = H, S0 = H, M= L, and Cn = L
A1
RSET
A0
CK
A2
A3
B0
B1
B2
B3
F1
F0
F2
F3
1
1
0
0
0
0
0
01
0
1
1
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Cost Analysis Estimated time spent on each phase of the project
Drawing Schematics: 1 week
Verifying Logic : 1 week
Verifying Timing : 1 week
DFF Schematic and DFF Layout: 3 days
4-bit ALU Layout: 2 weeks
Post Extraction of Timing: 4 days
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Conclusion
Power Density: 13.54 mW/cm2
Clock Frequency: 222 MHzArea: 430.00 x 833.10 µm2
Metal 1, 2, and 3are usedHold time: 0.26nsSetup time: 0.73ns902 NMOS & 902 PMOS transistors513 Nets26 Terminals
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Lessons Learned
Do the “Hay” when the sun shines! Do NOT use prime (‘) to name pins in NC Verilog.
Do NOT cross same type of metals. Consult your manager instead of being lost.
Good CoordinationLearn to make trade offs
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Acknowledgement
Thanks to Professor D. Parent for his guidance and unlimited office hours
Thanks to Synopsys for software donation
Thanks to Cadence Design Systems for the VLSI lab