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16 BIT KOGGE-STONE TREE ADDER

Shayan Kazemkhani

Nghia Do

Jia Kang Yu

Toan Luong

Advisor: David ParentMay 8th 2006

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Agenda• Abstract• Introduction

– Why Tree Adder?– Theory

• Project Details• Summary of Results• Lessons Learned• Cost Analysis• Conclusion

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Abstract

• We designed 16 bit Kogge-Stone Tree Adder - the most commonly used parallel prefix carry-lookahead adder topology.

• 200MHz clock frequency• Area 1000*600 um^2• Power density • AMI06 Technology

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Introduction• Why? - minimum logic depth, wide wiring channels,

regular structure and large fanout points. • Prefix Adder Structure

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC0C1C2C3

Cout

C4

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PROJECT DETAILS

•17 pin outs

•33 input D-flip flops and 17 output D-flip flops

•Create schematic and layout for 16 bit tree adder

•Test schematic using test bench

•Run DRC and LVS to verify the design

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BLOCK DIAGRAM

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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Longest path calculation

Tphl = 5ns/(14+3) = .29ns

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Table of actual Wn & Wp

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Schematic

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Layout

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DRC Report

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Extraction report

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LVS Report

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Cost Analysis

• Estimate amount of time spent on project:

- Verifying NC Verilog 5 hrs

- Verifying Timing 10 hrs

- Layout 40 hrs

- Post Extracted Timing 10 hrs

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Lessons Learned

• Start early

• Work in group

• Study previous projects

• Seek advice from Dr. Parent and previous students

• Save time for debugging error

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Conclusions

• We designed and implemented a 16 bit Kogge-Stone Tree Adder that operates at 200MHz in an area of 1000*600 um^2

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Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab

• Thanks to Dr. David Parent

• Thanks to all 166, 167, and 224 students