1 1 VLSI Introduction Overview

7/29/2019 1 1 VLSI Introduction Overview

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TTM Institute of Technology 1

IC LAYOUT ENGINEERING

Introduction

to

Microelectronics

DAY ~ 2


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Evolution Of Microelectronics

1947: Three scientists at Bell Telephone Laboratories, WilliamShockley, Walter Brattain, and John Bardeen demonstrate the firsttransistor :

1955: Frosch and Derick at Bell Labs patent the diffusion furnace anddevelop SiO2 passivation layers for silicon transistors

1955: Andrus and Bond at Bell Labs pattern oxide layers withphotolithography

1957: Lantrop and Nall (US Army) Pattern 200um leads to connectdiscrete transistors

1958: Last and Noyce develop the first step and repeat cameras for lithographic processing at Fairchild


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1957/1958: Jean Hoerni at Fairchild conceptualizes the first planer fabrication process for pn junctions using oxide barriers to protect pn

junctions underneath. Allowed all of the circuitry required for transistor fabrication to be patterned on 1 side of the wafer.

1959: Fairchilds Robert Noyce patents the monolithic IC that tiestransistors, capacitors, resistors together using micro lithographicallypatterned aluminum leads deposited on top of Heornis protectivecoating.

1960:Fairchild sells planer npn transistor device utilizing SiO2 barrier oxide for passivation that was patterned using a lithographic fabricationprocess

1960: Fairchild demonstrates the first IC with 4 transistors and 5resistors

1961 GCA Corporation commercializes the step and repeat reduction

device for optical lithography


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Evolution Of Microelectronics (cont.)

1960: First MOS transistor

1960: Ian Ross of Bell Labs uses CVD to between the substrate andthe collector to raise breakdown voltage and significantly increase thespeed of the circuit

1961: Hoerni demonstrates Silicon transistor that exceeds Geswitching speeds: Computers take off!!

1963: San and Wanlass of Fairchild showed that p and n channelMOS transistors arranged into a complementary circuit (CMOS) drewclose to zero power in standby mode

1964: Standard logic IC families introduced

1964: General Microelectronics releases the first commercial MOS IC


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MOS FET Structure


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1965: Fairchilds Director Gordon Moore introduces Moores law whichaccurately predicts the exponential increase of transistor density in anIC and provides a guide for technological progression that is still in usetoday

NSF is now preparing for the demise of Moores law reached thelimits of optical lithography Single bit logic is fading to quantumcomputing and the q bit


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Moores Law 1965: Fairchilds Director Gordon Moore introduces Moores law which

accurately predicts the exponential increase of transistor density in anIC and provides a guide for technological progression that is still in usetoday

NSF is now preparing for the demise of Moores law

reached the limits of optical lithography Single bit logic is fading toquantum computing and the q bit


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1964: Multi chip SLT packaging technology introduced by IBM1965: Fairchild Engineers develop Dual In Line (DIP) chip packaging1966: Semiconductor bipolar RAM 1966/1967: Computer aided design leads to Application Specific IC(ASIC)

1967: Turnkey equipment supplies such as Applied Materials introducecommercial tooling1969: Intel enters the scene with commercial tooling, silicon gatetechnology, and embedded metallic leads


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1966 : First 256K Bipolar Ram 1971 : Intels 1stMicroprocessor: i4004


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Design Of Performance Parameters

Physical : Area , Size , Weight

Power : Dissipation/Consumption

Speed : Timing

Noise : Cross talk
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THE GOAL OF ASIC DESIGNER

Meet the market requirement Satisfying the customer need Beating the competition Increasing the functionality Reducing the cost

Achieved by Using the next generation Silicon

Technologies New Design concept and Tools High Level Integration


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Power

Cost

Delay

Smaller is Better

THE PERFORMANCE CUBE


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VLSI TECHNOLOGY

Backbone for all IT advancements. A Technology solution and not a product.Packages lot of circuitry ( Millions of Gates] MiniaturisationConfidentiality Low power operation

Hand held battery operated gadgets


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APPLICATIONS

High Performance computing

Datacom/ Networking

Telecom/MOBILE/CELL/ WIL

Multimedia

Smart Cards

Remote Controls


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ADVANTAGES OF VLSI

REDUCTION IN

Design cycle time

Product Size

Power Consumption

Cost

INCREASE IN

Speed

Design Security

Productivity

Design Flexibility


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MOORES LAW

In 1969, Gorden Moore stated that SiliconTechnology will double the number of transistors per chip every 18 months!!!

Gordon MooreIntel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com


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MOORES LAW

In 1969, Gorden Moore stated that SiliconTechnology will double the number of transistors

per chip every 18 months!!!

And it is happening ! ! ! ! ! ! !!!!!!!!

Now Moores law has become self sustani ng

Gordon MooreIntel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com
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INTEGRATION LEVEL

Year Types gates per chip

60s - SSI : small-scale integration ~10

70s MSI: medium-scale integration ~100 1K

80s - LSI: large-scale integration ~1K 10K

90s - VLSI: very large-scale integration ~10K 100K

ULSI: ultra large scale integration ~1M 10M upwards


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Shrinking of Technology


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Gate & Interconnect Delays with shrinking

0.651989

0.51992

0.351995

0.251998

0.182001

0.132004

0.12007

0

5

10

1520

25

30

35

40Gate delayInterconnect delay

Source: SIA Roadmap 1997


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Technology Directions

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35Mtrans/cm 2 7 14-26 47 115 284 701

Chip size (mm 2) 170 170-214 235 269 308 354

Signal pins/chip 768 1024 1024 1280 1408 1472

Clock rate (MHz) 600 800 1100 1400 1800 2200Wiring levels 6-7 7-8 8-9 9 9-10 10

Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6

High-perf power (W) 90 130 160 170 174 183

Battery power(W) 1.4 2.0 2.4 2.0 2.2 2.4


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Over View

Of

VLSI DESIGN METHODOLOGY


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VLSI - OVERVIEW

Customer Specification

Semi -CustomASIC

Gate ArrayASIC

FPGA

ASIC

VLSITECHNOLOGY

FullCustom

ASIC


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Silicon Manufacturing Alternatives

Standard Components Application Specific ICs

Fixed Application

Applicationby Programming

SemiCustom

SiliconCompilation

FullCustom

LogicFamilies

HardwareProgramming

(MASK)

SoftwareProgramming

TTLCMOS

PLAROM

Microprocessor EPROM,EEPROM

PLD


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Design Styles

Complexity of VLSI circuits

Full custom

Performance Size Cost Market time

Standard Cell Gate Array FPGA

Different design styles

Cost ,Flexibility,Performance

( )


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VLSI - OVERVIEW (cont )Customer Specification

Semi -CustomASIC

Gate ArrayASIC

FPGAASIC

Full Custom ASIC

Logic Design/Front End

Gate Level

Net List


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behavioral 13

Blocking assignment

always @ (A1 or B1 or C1 or M1)// blocking assignments

begin: BLOCK_COMBM1 = #3 (A1 & B1);Y1 = #1 (M1 | C1);

end

A1

B1

C1

M1

Y1

3 1

LOGIC DESIGN


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VLSI - OVERVIEW

Customer Specification

Semi -CustomASIC

Gate ArrayASIC

FPGAASIC

FullCustom

ASIC

Logic Design/Front End

Physical Design/Back End

Gate Level

Net List

Physicallayout


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PHYSICAL

DESIGN


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FOUNDRY Masks

Si wafer

Chemicals

ProcessedWafer

Chips

FinishedASIC

ASICprocessing


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ASIC


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Design Summary


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Design Functional Parameters

ApplicationsSystem On Chip

Mobile Communications

Networking

Space/Automobile applications

Signal Processing

Remote Sensing


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Examples :

SSI : All 74 XX ,54 XX series gates

MSI: Decoders, mux, shift registers, counters etc.

LSI: Memories, 8bit UPs/ UCs ,Peripheral devises etc

VLSI : X86 to pentium,memories,and fpgas & ASICs

ASIC Products


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Applications Growth.

1971 : Intel 4004 - 2300 transistors, 1 MHzclock

Ultra Sparc III - 16 Million transistors

2001 : Intel P4 - 42 Million, 2 GHz clock

HP PA-8500 - 140 Million transistor

Amazingly visionary million transistor/chip barrier was crossed in the 1980s


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Design Characteristics

0.13M12MHz1.5 um

CAESystems,Silicon

compilation

7.5M333MHz0.25 um

Cycle-basedsimulation,

FormalVerification

3.3M200MHz

0.6 um

Top-DownDesign,

Emulation

1.2M50MHz0.8 um

HDLs,Synthesis

0.06M2MHz

6um

SPICESimulation

Key CAD Capabilities

The Challenges to sustain such an exponential growth to achievegigascale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology .

VLSI Technology Trend


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Intel Pentium (IV) Microprocessor


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Technology 0.1 umTransistors 200 MLogic gates 40 MSize 520 mm 2

Clock 2 - 3.5 GHzChip I/Os 4,000Wiring levels 7 - 8Voltage 0.9 - 1.2Power 160 WattsSupply current ~160 Amps

PerformancePower consumption

Noise immunityAreaCostTime-to-market

Tradeoffs!!!

The VLSI Chip in 2006


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Design Abstraction Levels

DEVICE

n+S D

n+

G

CIRCUIT

Vout Vin

CIRCUIT

Vout Vin

GATE

MODULE

+

SYSTEM


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VLSI TECHNOLOGY

Encompasses different Design Domains:

Logic Design - As Code

Physical design - As Layout

Product Fabrication - As product

DESIGN METHODOLOGIES- Y CHART


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TTM Institute of Technology 52Circuit abstraction level

Micro architectureabstraction level

ogic abstraction levelSystem abstracti

level

Ph ysical domain

STRUCTURAL DOMAIBEHAVIORAL DOMAIN Synthesis

Chips.MCM,boards

CellsChips / modules

Layout transistor

Transistors

Logic gates ALUs , registers

processors

instructionsSubroutines ,B.equations

programs

Application algorithms

Overview Of VLSI Design Methodology


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Overview Of VLSI Design MethodologySummary :

* VLSI Design Methodology using Major Activity Blocks

* Explain the Activity in each of the above Block . A) Logic Design. B) Physical design c) Foundry

* Types of libraries appended to Design Flow & its significance

* Using HA Truth table derive the followinga) Boolean Expression b) Behavioral Model C) Structural Modeld) Physical Model e) Gate level Netlist

* With the help of Y-Chart explain Design domains and Levels of Abstraction DAY ~ 2


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Thank You


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Technology Definition

SSI : 2 - 20 GATES

MSI : 20 - 200 GATES

LSI : 200 - 2000,000 GATES

VLSI : OVER 1 MILLION GATES


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Semiconductor Product Evolution (cont.)

1925 - MOSFET transistor Heil (England)1935 - MOSFET transistor Lilienfeld (Canada)1947 - Transistor Bardeen (Bell Labs)1949 - Bipolar transistor Shockley1956 - First bipolar digital logic gate by Harris1959- First monolithic IC by Jack Kilby1960 - First commercial IC logic gate by Fairchild


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Semiconductor Product Evolution

1960s - CMOS plagued with manufacturing problems1960s - PMOS in (calculators)1962 - 90 - TTL Logic gates

1974 - 80 - ECL Logic gates1970s - NMOS in (4004, 8080) for speed1980s - CMOS in preferred MOSFET technologybecause of power benefitsBiCMOS, Gallium-Arsenide, Silicon-GermaniumSOI, Copper- Low K,


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Technology EvolutionTECHNOLOGICAL

YEAR ERA BREAKTHROUGH

1920 -- Vacuum Tube - Vacuum Technology -- Glass to metal seal

1948 -- Transistor fabrication -- Crystal growth

1958 -- SSI - Planar technology - Digital Gates -- Photolithography

1962 -- MSI - PMOS Technology - Registers, -- Gate Oxidedecoders, muxes

1968 -- LSI - NMOS Technology- Memory -- ION Implantation &CVD

1978 -- VLSI - CMOS Technology -- multi layerinterconnect Micro processors Technology


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1960: Fairchilds first IC Dec. 1947: First Transistor


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