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Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device

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2013 Nanotechnology 24 384009

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IOP PUBLISHING NANOTECHNOLOGY

Nanotechnology24 (2013) 384009 (6pp) doi:10.1088/0957-4484/24/38/384009

Nanoscale RRAM-based synaptic

electronics: toward a neuromorphiccomputing device

Sangsu Park1, Jinwoo Noh1, Myung-lae Choo1, Ahmad Muqeem Sheri1,

Man Chang2, Young-Bae Kim2, Chang Jung Kim2, Moongu Jeon1,

Byung-Geun Lee1, Byoung Hun Lee1 and Hyunsang Hwang3

1 Gwangju Institute of Science and Technology, Gwangju 500-712, Korea3 Samsung Advanced Institute of Technology, Yongin-si Gyeonggi-do, 446-712, Korea2 Pohang University of Science and Technology, Pohang, 790-784, Korea

E-mail:[email protected]

Received 3 January 2013, in final form 26 March 2013

Published 2 September 2013

Online atstacks.iop.org/Nano/24/384009

Abstract

Efforts to develop scalable learning algorithms for implementation of networks of spiking

neurons in silicon have been hindered by the considerable footprints of learning circuits,

which grow as the number of synapses increases. Recent developments in nanotechnologies

provide an extremely compact device with low-power consumption.

In particular, nanoscale resistive switching devices (resistive random-access memory

(RRAM)) are regarded as a promising solution for implementation of biological synapses dueto their nanoscale dimensions, capacity to store multiple bits and the low energy required to

operate distinct states. In this paper, we report the fabrication, modeling and implementation

of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In

addition, we first experimentally demonstrate the learning capabilities and predictable

performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point

array of synapses and complementary metaloxidesemiconductor neuron circuits. These

developments open up possibilities for the development of ubiquitous ultra-dense,

ultra-low-power cognitive computers.

(Some figures may appear in colour only in the online journal)

1. Introduction

Two critical issues associated with the current semiconductortechnology are the physical scaling limits of devicedimensions and the low energy efficiency of von Neumannsystems as compared to those of biological systems [15]. Thedevelopment of biologically inspired neuromorphic systemshas attracted considerable interest over the last few yearsas a means of overcoming both issues [610]. However,progress in implementing neuromorphic hardware systemshas been hindered by the difficulty associated with fabricatingsynapses in electronic circuits, as such structures simply

require a very large area. An artificial brain requires aconsiderable number and density of synapses (e.g., the density

is estimated to be 1010 cm2 in the human cortex), andbiological synaptic structures are not only dense but alsoconsume miniscule amounts of power and maintain memorystorage for long periods of time [11].

Recently, neuronal functions have been successfullymimicked using emerging nanoscale resistive memory(resistive random-access memory (RRAM)) arrays havinganalog memory capabilities suitable for synapse building;such architectures have been able to achieve high-density(using a 4F2 cell), high-efficiency and low-power signalprocessing. However, a fundamental problem faced by suchpassive arrays is that sneak paths (parasitic current paths that

cause interference between neighboring cells within the array)can be formed, causing the array to lose functionality [12, 13].

10957-4484/13/384009+06$33.00 c 2013 IOP Publishing Ltd Printed in the UK & the USA
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Nanotechnology24 (2013) 384009 S Park et al

Figure 1. Hybrid CMOS neuron/RRAM synapse circuit to emulate the biological neuron system.

Various solutions have been proposed to alleviate

the misreading problem and to ensure the reliability

of high-density memory arrays. One solution involves

introduction of a selection device in each cell, and

several types of these have been proposed for use

in bipolar-type RRAM arrays, including metalinsulator

transition devices[14], ovonic threshold switches[15], mixed

ionicelectronic conductors [16], and metal-oxide-based

metalinsulatormetal devices[17]. However, integration of

a selection device increases the complexity and cost of the

fabrication process. Instead of relying on external diodes

as selectors, a better approach to breaking sneak current

paths is to take advantage of the nonlinear currentvoltage(IV) characteristics inherent to some types of resistive

switches[1821].

Other research has focused on developing spike-timing-

dependent plasticity (STDP) using only individual memory

devices [2224]. Ultimately, the implementation of fully

functional large-scale neuromorphic systems that can mimic

brain functions is limited by the considerable gap that

currently exists between the ability to build semiconductor

devices and the ability to design systems.

To overcome this deficiency, we fabricated a real

neuromorphic system, which was comprised of comple-

mentory metaloxidesemiconductor (CMOS) neurons and aselector-less RRAM 1 kbit array, by taking advantage of the

nonlinear characteristics of the RRAM element (figure1).

2. Experimental setup

We fabricated a 1 kbit RRAM array of synapses; the

process scheme for this array is detailed in figure 2. The

system consists of a cross-point RRAM array of active

W/Al/Pr0.7Ca0.3MnO3 (PCMO)/Pt (from top to bottom)

devices having diameters ranging from 150 nm to 1 m

using a via-hole structure. To fabricate this structure, a bottom

electrode (BE) consisting of a 50 nm-thick Pt layer (by usingelectron beam evaporation) and a 30 nm-thick polycrystalline

PCMO film (by using RF magnetron sputter) was deposited by

means of conventional lithography and reactive ion etching.

During PCMO deposition, the substrate temperature was

maintained at 600 C. Next, a SiNx 80 nm-thick layer wasdeposited (by plasma-enhanced chemical vapor deposition),

followed by the formation of via holes by means of

conventional lithography and reactive ion etching. The PCMO

film was then annealed for 30 min at 500 C in an oxygenatmosphere in order to treat any defects on its surface. A top

electrode (TE) consisting of 7 nm of Al and 90 nm of W was

subsequently deposited (by using RF magnetron sputter) and

patterned by means of conventional lithography. The electrical

characteristics of all of these devices were measured usingan Agilent 4155A semiconductor parameter analyzer and an

Agilent 81104A pulse generator.

Microscopic images of the cross-point 1 kbit synaptic

RRAM array are shown in figures 3(a) and (b). The

cross-section of the memory device was investigated by

transmission electron microscopy (TEM), as shown in

figure3(c).

3. Results and discussion

Figure 4 shows the currentvoltage (IV) hysteresischaracteristics during incremental reset and set bias sweeps.

This graph shows the analog memory characteristics of the

selector-less, cross-point 1 kbit RRAM array. In light of

the previously studied operational mechanisms for this type

of device, the results show multi-level conductance caused

by the oxidation and reduction of AlOx at the Al/PCMO

interface [26]. When Al is deposited, the reaction between Al

and PCMO makes a very thin AlOxlayer. A dc bias is applied

to the W top electrode while the bottom electrode is grounded.

As a negative bias is applied at the top electrode, oxygen ions

(O2) move from the AlOx to the PCMO bulk layer, whichforms the LRS. In contrast, a positive bias attracts O2 andforms a thick insulating oxide layer, which results in an HRSby preventing conducting electrons. For an electronic synapse

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Figure 2. The process scheme for the cross-point 1 kbit synaptic RRAM array.

Figure 3. (a), (b) Microscopic images. (c) FIB-TEM image of the cross-point 1 kbit synaptic RRAM array. An RRAM is formed at eachcross-point.

to emulate the behavior of a biological synapse, it would be

necessary that the conductance of the electronic synapse could

be continuously modified by input impulses.

An important further step is design of a model of the

RRAM synapse, as shown in figure 5.Figure5(a) shows the

multi-level IVcharacteristic curves of the proposed device

under the double sweep mode. The switching behavior of

PCMO devices is mainly controlled by the migration of

oxygen ions under an electric field applied between the active

top electrode and the PCMO film. The bias voltage wasswept from 0 V Vmax 0 V +Vmax 0 V. Both

the current level and ROFF/RON ratio are increased graduallywhen the electric field (Vmax) increases.

On the basis of the experimental measurements, we

developed a Verilog-A model of an RRAM synapse in aCadence simulatorthe main platform tool for integratedcircuit development. Figure 5(b) shows the modeling resultfor the proposed device under the double sweep mode. Themodeling results showed that the resistance of RRAM-basedsynapses is closely related to the metal oxide layer thickness.As can be seen from equations (1)(2), the level of current

in the PooleFrenkel (PF) emission and space charge-limitedcurrent (SCLC) models is influenced by the oxide thickness

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Figure 4. Repeated incremental negative and positivecurrentvoltage (IV) sweeps. This graph shows the analog memorycharacteristics of the cross-point 1 kbit synaptic RRAM array.

(di) and the barrier height (B). Here, it is assumed that the

barrier height varies linearly with the thickness of the oxide.

JPFv

diexp

q

qV/dii B

kT

(1)

JSCLC AVB (2)RTotal= RPF +RSCLC. (3)

As testing of the capability of the Verilog-A modelshowed that it could be used to accurately simulate the

experimental data, we utilized it as the interface for simulating

RRAM-based synaptic networks with CMOS-based neurons

and for testing neuromorphic circuits.To evaluate the feasibility of the proposed neuromorphic

device, we designed a CMOS neuron and RRAM array

synapse circuit configuration based on a leaky integrate-

and-fire neuron model [25]. This electrical circuit consistedof a capacitor C in parallel with a resistor R and 30

RRAM synapses driven by a current I(t). The integration

and discharging times were determined from the parameters

of R and C; different clock cycles were used (not shown inthe figure). Larger RRAM conductance, which represents alarger number of open channels in real synapses, correspondsto larger synaptic weights. This architecture operates in twomodes: the learning and testing modes. Cycle CLK1 isactivated in the testing mode, whereas CLK2 is activated

during the learning mode; all of the clocks in this circuit sharea common clock. Figure6(b) shows the circuit configurationin the learning mode, in which the cycle number of CLK2 isused to determine the degree of learning, whereas figure 6(c)shows the circuit configuration in the testing mode. Sequentialinput signals from 0 to 9 were applied continuously in order tocontrol the state of the RRAM (i.e., LRS/HRS), and electricalpulses were applied to all of the inputs in order to updatethe resistance of the RRAM synapse (or the weight of thesynapses). The total current flow was determined from theresistance of the RRAM and the amplitude of the input pulse.

Figure 7(a) shows a photographic image of a CMOSneuron circuit with a 1 kbit RRAM array as the synapse.

The CMOS neuron circuit consists of pulse generation,neuron networks and connection parts. Figure 7(b) showsthe experimental results for the hybrid CMOS neuron/RRAMsynapse circuit in the testing mode. There are five states (fromVout1 to Vout5). The data were obtained by measuring theresponse of a 30 RRAM synapse branch to the input spikes.This bi-stable mode of using the RRAM would encode only anON or OFF synaptic state. Of course, we could modulatethe resistance of the RRAM to obtain multi-level distinctanalog states, as already shown in figure 4. In the testingmode, once a selected neuron fires, if its voltage exceeds theneurons firing threshold, it lets every other neuron know it hasdone so, which resets all of their internal states to minimum.

It is worth noting here that the slope of each curve showslinear behavior; this indicates that there is a constant valueof resistance in an RRAM synapse, which in turn shows thefavorable retention and learning properties of such synapses.

4. Conclusion

Previous research has shown that high-density, hybridRRAM/CMOS systems can function well by taking advantage

Figure 5. Comparison conducted with a variable voltage under the double voltage sweep mode between (a) the experimental and (b) themodeled nonlinear characteristics of the device.

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Figure 6. (a) Simple circuit diagram of a hybrid CMOS neuron/RRAM synapse circuit to emulate the biological neuron system. (b) Circuitconfiguration in the learning mode, in which the cycle number of the pulse is used to determine the degree of learning. (c) Circuitconfiguration in the testing mode.

Figure 7. (a) Photographic image of the hybrid CMOS neuron/RRAM synapse circuit. (b) Experimental results for the hybrid CMOSneuron/RRAM synapse circuit in the testing mode. There are five states (from Vout 1to Vout5). Each slope is linear. This means that theresistance of the RRAM synapse has good retention and learning properties.

of the nonlinear IVcharacteristics of the synaptic RRAM

array. In this study, we experimentally demonstrated for

the first time the learning capabilities and predictableperformance in a neuromorphic circuit consisting of a

nanoscale 1 kbit RRAM cross-point array synapse network

and CMOS neuron circuits. The results of our work strongly

suggest that RRAM-based synaptic electronics are well suitedfor use in future data storage and neuromorphic applications.

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Acknowledgments

This research was supported by the Pioneer Research Center

Program through the National Research Foundation of Korea

funded by the Ministry of Education, Science and Technology

(2012-0009460).

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