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A 4-Bit, 5Gsps ADC Board for the Radio Astronomy Community

Homin Jiang1, Howard Liu1, Kim Guzzino1, Derek Kubo1, Chao-Te Li1, Ray Chang1.

THE AUTHORS ARE WITH THE ACADEMIA SINICA INSTITUTE OF ASTRONOMY ANDASTROPHYSICS, P.O. BOX 23-141, TAIPEI, 106, TAIWAN. (PHONE: 886-2-23665347;

FAX: 886-2-23677849; E-MAIL: HOMIN@ASIAA.SINICA.EDU.TW)

Abstract We have designed, manufactured andcharacterized a 5 Giga samples per second (5 Gsps) , 4-bit,ADC printed circuit board (PCB). The board is compatiblewith the Field Programmable Gate Array(FPGA) platformsdeveloped by the Collaboration for Astronomy SignalProcessing and Electronics Research (CASPER) community.

The board can digitalize input radio frequencies from DC upto 2.5GHz with a flatness of 5dB. The ENOB ranges from 3.8to 2.5 bits across the 2.5GHz band, the SFDR from 35dB to 25dB, and the SINAD from 20dB to 12 dB respectively.

The board enables direct detection for observations in theradio frequency range, and will save tremendous resources inthe Intermediate Frequency (IF) distribution for observationsin the microwave frequency region. We have delivered theboards to several world class radio observatories for thedetection of celestial objects.

Index Terms Analog to Digital converter (ADC).Effective Number of bits (ENOB), Field Programmable GateArray (FPGA), Signal to Noise and Distortion (SINAD),Spurious Free Dynamic Range (SFDR).

I. INTRODUCTIONThe tremendous progress in microelectronics

significantly benefits not only our day-to-day lives, but

also the scientific research. The rapid increase in the

sampling rate of commercially available analog-to-digital

converters and the ever increasing processing power of

FPGA chips has led to the possibility of digitizing the

radio astronomical data in a broader IF bandwidth, thus

enhancing the capability of the radio astronomical

telescope.

To take advantage of the benefits mentioned above, we

selected a suitable and economic ADC chip, designed a

board to digitize the astronomical signal for furtherprocessing. As the data processing usually happens in

FPGA platforms, the ADC board has to be compatible

with the targeted FPGA platform.

Micram had announced its 30Gpsp ADC chips in 2010

which was in its developing phase, yet ready for the

market. [1] There was a similiar ADC board developed by

Klein [2], while this ADC board was being designed in

2010. Unfortunately, it is only used in their own research

projects, and is only compatible with their own FPGA

platform. Commercial boards by Acqiris[3] had been

surveyed. There was no academic discount so it was not

affordable. For radio telescope applications, it always

needs a large amount of ADC and FPGA boards.

Acquiring the hardware from a non-profit organization

such as CASPER will save the resources of scientific

institutes.Nowadays, there are several commercial ADC boards

with associated FPGA platforms available, such as

Tektronix's TADC-1000 which is 8-bit and 12 Gsps ADC

[4]. Flaska employed the CAEN V1751 , 10 bits / 1 Gsps

ADC board for his nuclear research[5]. These all used

several identical ADC chips, which were interleaved them

to make the sampling rate faster and so broaden the

bandwidth.

Interleaving two ADC boards of this work with the

CASPER's FPGA platform so called Reconfigurable Open

Architecture Computing Hardware (ROACH), which is a

standalone FPGA processing board [6], the users can

double the sampling rate to 10Gsps and 5GHz bandwidth.The capability is competitive with the commercial

products mentioned above, but the cost is more reasonable.

We have developed a 5 Giga sample per second (5Gsps)

Analog to Digital (ADC) Printed Circuit Board (PCB) for

the CASPERcommunity by employing e2Vs EV8AQ160

ADC chip [7][8]. Analog data is digitalized by the chip,

followed by the output of the digital data by the ADC

board to CASPERs FPGA platforms [9] [10] [11] via the

high speed board to board Z-DOK connector, the standard

process used in the CASPER toolflow.

Fig. 1. The 5Gsps ADC board is on duty.

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The maximum allowed global clock frequency of the

ROACH platform is 450MHz. Under this limitation, the

ADC clock can be driven to 1.8GHz, which is beneath thebandwidth of the board. To overcome this limitation, we

adopted the other option of de-multiplexing the chip by 8,

with the clock frequency one-half that of the default

approach of de-multiplexing by 4. On the other hand, the

number of data ports is doubled; with the number of pins

on the Z-DOK fixed, not all can be fitted in. We therefore

discarded 4 out of 8 bits to make the board compatible

with the Z-DOK connector. For radio astronomy telescope

applications, 4 bits resolution is good enough for celestial

imaging works [12]. The system clock of the FPGA

platform is usually aligned with the clock signal of the

ADC board. With the de-multiplexing factor of 8, when

the ADC board is driven up to 2.5GHz, the system clock isonly 312.5MHz, which is well within the operating range

of the ROACH board.

We performed both passive and active tests to canvas

more information about the board. The passive tests shed

light on the impedance of the PCB traces, insertion and

reflection loss of the input path and connected passive

components, etc. whereas the active measurements

provided information on typical ADC characterization

parameters such as the Effective Number Of Bits (ENOB),

Signal to Noise and Distortion (SINAD) and Spurious Free

Dynamic Range (SFDR) [13].

II. HARDWAREAs illustrated in Fig. 1, the heart of the board is a 5Gsps

8-bit ADC chip. It takes 2 SMA inputs for the 2-channel

input, and the third SMA connector for the sampling clock

signal. The fourth SMA on the board is the one pulse per

second signal for system synchronization. After the SMA

connectors, a filtering circuit composing of baluns limits

the input signals in the allowed bandwidth, i.e. 2.5GHz.

After digitization, a high speed board to board ZDOK

connector transfers the digital data from the board to the

FPGA platform. The board is a 4-layer PCB, of which

outer substrates are Rogers 4003. The material will yield

better performance in the radio frequency range. There arethe regular FR-4 substrates in between.

III. PASSIVEMEASUREMENTOFINPUTBALUNSDuring the S21 transmission test, two pigtail UT-047

wires with two SMA connectors were soldered to pin A7

and pin A8 individually, as showed in Fig. 2. The SMA

connector to A7 was connected to a network analyzer

while the SMA connector to A8 was terminated with a 50

ohm load. The coarse blue curve in Fig. 3 represents the

transmission loss of the 2 baluns configuration and the

coarse red line represents the transmission loss of the 3

baluns configuration. The balun was used in an input port

which contributed 0.4dB of transmission loss each.

Therefore, for the 2 balun configuration, there was a totalof 0.8 dB in transmission loss. The 2 baluns configuration

exhibited better transmission performance.

A 100 ohms termination resistor was placed between pin

A7 and A8 in lieu of the pigtail SMA connectors while the

test of return loss was performed. The results are depicted

by the thin curves in Fig. 3. The 2 baluns configuration

possessed lower return loss than the 3 baluns configuration.

From the measurements of the insertion loss, S11, and

the return loss, S21, for the 2 baluns and 3 baluns

configuration, we concluded that the 2 baluns

configuration is better suited for our application. The key

projects of our institute are focused on the broadband and

high frequency. Since the 3 baluns configuration performsbetter in the low frequency zone, essentially our guard

band area, the data will be useless for our application. Thus,

only the 2 baluns configuration of the ADC board

underwent characterization testing.

IV. SFDRMEASUREMENT

The input frequency of the Continuous Wave (CW)

signal was properly chosen to encompass the pure

monotonic signal right in the center of the spectral bin. To

avoid artifacts from the quantization noise correlation [14]

[16] [16], or the effect of Differential Nonlinearity (DNL),

a low power noise was added to the carrier. A 2 GHz

bandwidth noise source was attenuated at 30dB to the

carrier, and then combined with the CW carrier by a

combiner. At the end, a dithered carrier was injected into

the 5Gsps ADC board, the device under test.

The clock frequency was fixed at 2500MHz by

employing a frequency synthesizer at 0 dBm. The CW

Fig. 2. Input schematic of the ADC board. There are 3 baluns onthe schematic, L1, L2, and L3 for limiting the input signals in therange of 2.5GHz. The input signals go through these baluns,cross the zero ohm resistor, R1 and R3, and then pass through the10n capacitors, C1 and C2, before entering the input pins of the

ADC chip, A7 and A8. The two termination resistors R6 and R7

are not populated.

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signal was provided by another synthesizer at -5 dBm, with

the value chosen to avoid saturation of the ADC level.

To enable analysis of the spectrum, we performed FastFourier Transform (FFT) with Matlab. The number of

sample points is 16384, yielding a process gain of 39.13

dB as given by Equation (1):

)2

(10PrM

LogocessGain (1)

where M is the number of samples.

The setup of active measurements such as SFDR,

SINAD, and ENOB ,as depicted in Fig. 4, involved a

board plugged into the ZDOK connector of a FPGA

platform, in which a simple model file was running. The

model was equipped with a snap block that captured thedigitalized data from the ADC board and then saved it in

the Block RAM (BRAM). A Python program running in

the Personal Computer (PC) then pipelined the data in the

BRAM to the PC, and saved the data on the hard drive.

The test conductor subsequently retrieved the data files and

analyzed the data with Matlab.

As illustrated in Fig. 5, the SFDR is the power of

carrier to the power of the strongest harmonic. Fig. 5

depicts the SFDR of the board in the input range from

100MHz to 2400MHz. The SFDR values were around

35dB in the low frequency region, and down to 25 dB for

the input in the high frequency region.

V. SINADMEASUREMENT

The SINAD, as evident from its name, is comprised of

two components, signal to noise (SNR) and signal to

distortion (THD). The traditional approach to calculate

these two values is to gather information from the

spectrum. The SNR is calculated by subtracting the noise

floor and the process gain from the power of carrier as

demonstrated in Fig. 5.

The top 5 harmonic tones were picked and summed as

the power of the Distortion (D). By subtracting the power

of the top five harmonics from the carrier (S) power, the

Total Harmonic Distortion (THD) can be derived. After

combining the SNR and THD, the SINAD parameter can

be derived as given by Equation (2):

DN

SLogSINAD

DSLogTHD

N

SLogSNR

10

10

10

(2)

where N is the power of noises.

To avoid saturation, the input power was picked at

around 1 bit under the full scale. Since the ENOB needed

to be compensated due to the loss of the input power as

given by Equation (4), we input the amplitude at around

one-half of the full scale. The ratio was 15:8, with 15 being

the full scale for 4 bits.Another more straightforward method to derive the

SINAD is the use of software tools such as Matlab. The

process is as follows: search the entire spectrum, locate the

bin of the carrier, and sum the power of the carrier with

nearby spectral bins as the power of signal. Next, sum all

the power of every spectral bin as the total power of the

spectrum, and subtract the total power of the spectrum

from the power of carrier, leaving the power of the noise

and distortion. Finally, divide the power of the signal by

the power of the noise and distortion as given by Equation

(2).

-35

-30

-25

-20

-15

-10

-5

0

0 1 2 3 4 5

GHz

dB

Fig 3. Transmission of signal inputs in the 2 baluns and 3 balunsconfigurations. The blue curves depict the 2 baluns configuration, andthe red curves the 3 baluns configuration. The coarse curves represent

the S21 data and the thin curves the S11 data.

30dB

Attenuator

2GHz Noise

Source

CW Signals

By

Synthesizer

FPGA

Platform

ROACH

Mixer

The board under test

Computer

30dB

Attenuator

2GHz Noise

Source

CW Signals

By

Synthesizer

FPGA

Platform

ROACH

Mixer

The board under test

Computer

Fig. 4. Block diagram of dynamic characterization tests setup. Thedigitized data transmitted to PC by the Ethernet cable. Matlab wasrunning in PC to perform FFT .

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Since all the harmonics were taken into account, the

SINAD obtained by the software approach was not as

refined as that obtained from the plot.

VI. ENOB BY 3METHODS

The ENOB was obtained via 3 approaches: from the plot

of the spectrum, direct calculation by software, and curve

fitting with sine waves. The first approach is the most

popular for ADC characterization and thus most valuable

for comparison. The noise floor is picked visually, thus

human error is involved with this method. The second

approach, which utilized a software program, yielded theworst ENOB because all the harmonics were taken into

account. On the other hand, since no human error was

involved, it exhibited superior flatness across the band.

The third approach involving curve fitting yielded the best

ENOB, but employed pure sine waves and shed no light on

the spectral characteristics.

Once a SINAD value has been obtained, the ENOB can

be derived from Equation (3):

02.6

_

_2076.1 10

AmplitudeInput

AmplitudeFullscaleLogdBSINAD

ENOB (3)

With the two values of the SINAD from the previous

section, one can derive the two ENOB correspondingly.

Another approach to characterize the ENOB of the ADC

board is to perform 4 parameters sine wave curve fitting

[16]. We employed the curve fitting tool called cftool by

Matlab to perform this characterization.

cftool fitted the data set according to the 4 parameters

sine wave as given by Equation (4). In an ideal case, the

CW input signals are pure sine waves without offset. Thus,

the 4 parameters for fitting the curve as given by Equation

(4) were used to fit the amplitude, phase, frequency and

offset:

1)11sin(1)( dcxbaxF (4)

After fitting, measures of the goodness of fit were

generated. The key parameter was the Sum of Squares Due

to Error. This statistic factor measures the total deviation

of the response values from the fit to the response values.

It is also known as the summed square of residuals and is

usually labeled as SSE. A value close to 0 indicates that

the model has a small random error component, and that

the fit will be more predictive. The SSE measure includes

errors due to Integral Non-Linearity (INL), DNL, missing

codes, jitter, and noises. Note that the curve fitting methodwas performed in the time domain; consequently, no

spectral information such as THD and SINAD could be

generated.

Ideally, one would obtain a square error for every

sample. Under the assumption of one least significant bit(LSB), that would yield 1/12. By comparing the SSE

obtained by curve fitting with the ideal square error of the

entire spectrum, one can obtain the ENOB as given by

Equation (5):

SSEQ

Q

Q

QLogNENOB

A

T

T

A

12

16384

2

(5)where 16384 is the number of samples in the work, N is

SINAD and SFDR

10

14

18

22

26

30

34

91.6

183

275

366

458

549

641

733

824

916

1007

1099

1190

1282

1373

1465

1557

1648

1740

1831

1923

2014

2106

2197

2289

2380

MHz

dBc

Fig. 5. The black curve represents the SINAD obtainedthrough the traditional approach, while the red curve representsthe SINAD as calculated with Matlab. The blue curve depictsthe SFDR of input frequencies from 100MHz to 2400MHz. All

three curves are shown with respect to the carrier.

ENOB

1

1.5

2

2.5

3

3.5

4

91.6

183

275

366

458

549

641

733

824

916

1007

1099

1190

1282

1373

1465

1557

1648

1740

1831

1923

2014

2106

2197

2289

2380

MHz

Fig. 6. Effective Number of Bits by the 3 methods. The darkblue line represents the ENOB obtained from curve fitting, whilethe light blue line represents the ENOB obtained from thetraditional approach with compensation. The pink line representsthe ENOB calculated from the Matlab program with

compensation. The brown line represents the ENOB obtained

from the traditional approach without compensation, and theyellow line represents the ENOB calculated from the Matlab

program without compensation.

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the number of ADC bits, QT is the theoretical N-bit RMS

quantization error, and QA is the actual RMS error from the

best fit sine wave.The ENOB obtained by curve fitting in this work was

around 3.6 to 3.9 bits, as illustrated by the dark blue curve

in Fig. 6. It encompassed only pure sine waves, without

taking the input power level into consideration, and the

ENOB obtained by the curve fitting approach yielded

better numbers than those via the previous two approaches.

VII. SUMMARYThe passive measurements in Section III showed that

the layout of the ADC board is promising. The 2 baluns

configuration has been adopted by ASIAA to yield better

performance in the high frequency region. The major ADC

characterization parameter of interest, the ENOB, was

obtained via 3 approaches. The traditional approach

utilizing the spectrum plot yielded an ENOB in-between.

Reading the noise floor visually from the spectrum plot

can lead to worse flatness across the entire band. The

ENOB obtained by the software approach was the worst,

since all the harmonics were taken into account. On the

other hand, since no human error was involved, it

exhibited superior flatness across the band. The ENOB

obtained by curve fitting was the best, but only pure sine

waves were used without taking the spectral characteristics

into consideration.

The traditional approach is also the most popular forADC characterization, and the ENOB obtained via the

traditional method is thus the most valuable for

comparison. The worst ENOB was around 2.5 bits at the

high frequency end, and the best ENOB was around 3.9

bits in the lower region of the band.

The other two key parameters of ADC characterization,

SFDR and SINAD, were also obtained via the traditional

approach.

The board can digitalize input signals with frequencies

ranging from DC up to 2.5GHz, and the SFDR, SINAD,

and ENOB were satisfactory for a 4 bit test. With the ADC

board, the ROACH can process digitalized radio signals

from the sky by implementing the filter bank, FFT andcorrelation in the FPGA platform.

VIII. ACKNOWLEDGEMENTThe authors wish to acknowledge the assistance and

support of the CASPER community, especially the

University of California at Berkeley, Smithsonian

Astrophysical Observatory, National Radio Astronomy

Observatory and the MeerKAT in South Africa. This work

is partly funded by National Science Council, Taiwan,

under Grant NSC 98-2119-M-001-024-MY4, partly funded

by Academia Sinica .

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