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978-1-4673-4900-0/13/$31.00 2013 IEEE

A Current-Starved Inverter-Based Differential Amplifier Design for Ultra-Low

Power ApplicationsWilliam Wilson, T om Chen, Ryan Selby

Department of Electrical & Comput er Engineering

Colorado State University, Fort Collins, CO 80523 USA

Abstract As silicon feature sizes decrease, more complex circuitryarrays can now be contrived on a single die. This increase in the number

of on-chip devices per unit area results in increased power dissipation perunit area. In order to meet certain power and operating temperaturespecifications, circuit design necessitates a focus on power efficiency,which is especially important in systems employing hundreds or

thousands of instances of the same device. In large arrays, a slightincrease in the power efficiency of a single component is heightened bythe number of instances of the device in the system. This paper proposesa fully differential, low-power current-starving inverter-based amplifier

topology designed in a commercial 0.18m process. This design achieves46dB DC gain and a 464 kHz unity gain frequency with a powerconsumption of only 145.32nW at 700mV power supply voltage for ultra-low power, low bandwidth applications. Higher bandwidth designs are

also proposed, including a 48dB DC gain, 2.4 MHz unity-gain frequencyamplifier operating at 900mV with only 3.74W power consumption.

INTRODUCTION

Operational amplifiers are essential components in many signalprocessing circuit designs. Almost any typ e of analog circuits,

including most continuous or discrete time amplifiers, analog todigital converters, sense amplifiers, and many other circuits use somevariety of operational amplifiers as their basic building blocks. These

and various other circuit designs are used in many tasks, includingthe amplification of small signals, as well as various typ es of mixed-

domain processing for complex audio and video signals.[1]

Many large-scale system-on-chip designs such as imaging and

sensing arrays use complex signal processing chains. These systemsoften use mixed-signal chains in sub-m processes. These reduced

channel length processes have desirable effects on performance andoverall size in digital circuitry; however, reduced channel lengths

have undesirable effects in analog circuit designs. Low p ower supplyvoltages and decreased output impedance, as well as limited gain ofsingle transistor stages make analog circuit design in sub-m a

challenging t ask [2].

Traditional operational amplifier designs most commonly use

transistors in the saturation region, which generally requires at leastone DC bias current. As technology size has decreased, low power,

high gain amplifier design has become more challenging fordesigners. Since transistor threshold voltage generally doesntdecrease as fast as feature size and power supply voltage, manycascaded or folded designs are not possible with reduced voltagesupply. Given that the reduction in headroom reduces the ability to

cascode devices, low voltage high-gain amplifiers are commonlybuilt by expanding outward, using two or even three cascaded

amplification stages. These multi-stage cascaded designs require thedesigner to take extra measures to ensure amplifier stability, and,

depending on the topology, can be very challenging or complex tostabilize. Most stabilization schemes require additional compensationcapacitors and/or nulling resistors, which use additional silicon area,

and can decrease circuit bandwidth; however, these compensation

schemes have been improving with the usage of active compensationnetworks. [3-13]

Reduced power supply voltage and the increasing demand for lowpower consumption make sub-threshold operation and desi gn a more

viable alternative when a reduction in bandwidth is acceptable.Operation in the sub-threshold region causes the drain current toincrease exponentially with VGS as opposed to quadratically in the

saturation region [14]. The disadvantage with sub-thresholdoperation is the reduction in amplifier driving current, and the loss of

ability to quickly drive large capacitive loads.

In this paper, an inverter-based operational amplifier topology

and operation and design principles are discussed and evaluated. Weuse two previously used figures of merit to objectively comparevarious aspects of the different circuit topologies. We conclude that

the inverter-based differential amplifier topology with currentstarving provides one of best circuit topologies for energy efficiency.

PROPOSED DESIGN

A prior attempt at achieving high gain with minimal DC current

usage and minimal area is the use of CMOS inverters in a differentialconfiguration [15-18].

FIGURE 1:INVERTER-BASED OP-AMP

The inverter-based amplifier topology shown in Figure 1 uses

CMOS inverters as the amplifier input. This input stage design has

the advantage of combining the transconductance of the n and ptransistors.

m mn mpG G G= +

This combination of the two transconductances should provide6dB increase in gain over a traditional common source amplification

stage, with approximately the same DC bias current. When thisarchitecture is implemented with a standard supply voltage (>2v t),

the overall transconductance can be increased significantlydepending on how transistors in the inverters are sized and theresulting current through the inverter. High current through the

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inverter allows significantly high bandwidths to be achieved.Another advantage of this topology is an increase in output swing

and linearity when compared to a traditional common source orcascode amplifier if the respective transconductances of the p and n

type transistors are approximately equal in magnitude. For noise, theinverter-based topology offers lower equivalent noise resistance

compared to the equivalent common source topology [20]. Assumingthe p and n type transistors are balanced and the equivalent noiseresistances for the n and p type transistors is RNn, and RNp,

respectively, the equivalent noise resistance for the inverter basedamplifier is

( )

2 2

2 2

mn Nn mp Np NnN

mn mp

G R G R RR

G G

+

= =

+

One weakness of the inverter-based amplifier is its limitedCMRR when configured in a differential mode as shown in Figure 1.

This issue will be addressed in the next sub-section.

Sub-Threshold Operation With Current Starving Tails

When this inverter-based architecture is implemented at a lowsupply voltage (1m) and large W/L ratios (ty pically >16) to improve outp ut

impedance, and to have an increased transconductance. Largelengths, esp ecailly in the cross-coupled inverters help alleviate the

effects of PVT.

SIMULATION RESULTS AND DISCUSSIONS

The current starved inverter-based amplifier was designed forthree different supply voltages of 0.7V, 0.9V, and 1.1V, allowing itto operate at different levels of sub-threshold regions with differentdriving strength. With the aim for low-power bioelectronicsapplications, the design goal is to achieve the maximum energy

efficiency p ossible with t he performance suitable for driving internalcircuit nodes of no more than 2pF load. Table 1 shows the simulationresults of the inverter-based Op-Amp under three different supply

voltages.

TABLE 1: SIMULATION RESULTS OF THREE INVERTEROP-AMPS

Designed SupplyVoltage

700mV 900mV 1.1V

DC Gain 46.22dB 48.36dB 47.9dB

Load 1.8pF 6pF 15pF

GBW 463.9kHz 2.408MHz 3.94MHz

Overall DC

Current207.6nA 4.157A 20.56A

Power

Consumption145.32nW 3.741W 22.616W

Offset Voltage 2.273mV 2.167mV 2.443mVInput Referred

Noise25.524V 6.428V 3.5V

CMRR 124.397dB 153.055dB 177.897dB

FOM 1 4022 3475 2874

FOM 2 5746 3861 2612

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To more effectively compare energy efficiency of the inverter-based design with some of the existing p ublished designs, we use

two different Figures of Merit (FOMs) for comparison.

Figure of Merit

The first FOM we use is defined as:

( )1

( )

( )

LGBW MHz C pF FOM

I mA

=

This FOM focuses on return-on-driving-current. It does not

directly measure the impact of supply voltage scaling. If comparisonsare made on circuits operating on the same sup ply voltage, this FOM

gives an accurate comparison. Otherwise, it tends to penalize designswith lower supp ly voltages.

To compensate for the impact of supply voltage, the second FOM

is defined as:

( )2

( )

( )

LGBW MHz C pF

FOMP mW

=

The second FOM is similar to the first, except that total power is

used to measure its return on performance and overall drivingstrength.

TOPOLOGY SCALABILITY AND FLEXIBILITY

The primary advantage with our proposed topology is thescalability (overall number in a system) in terms of both power and

area, without a significant compromise in performance.

This topology can be used at higher voltage supplies, and even

outside the sub-threshold region. As supply voltage increases, theinverter transistors tend to operate less deep into the sub-threshold

region, or if supply voltage is raised significantly high, in thesaturation region. Higher supply voltages, and in turn, higher

currents, tend to have a positive effect on the bandwidth of theamplifier; however, this positive effect isnt significant enough to

completely cancel out the effect of the increased overall current on

the circuits FOM.

When designing with higher supply voltages, designers have theoption of increasing input and tail transistor lengths, keeping the low-

current properties of the topology. Again, this approach can beadvantageous when the application does not require a high

bandwidth amplifier.

Design Comparison

We would like to compare the proposed design in the context of a

wide range of existing designs from simple common sourceamplifiers, to telescopic amplifiers, to traditional Miller compensated

amplifiers, and to the more advanced three-stage amplifiers. Simpleor folded cascode operational amplifier designs typically can achieve

a FOM of 200-300[1, 2]; telescopic amplifiers typically have ahigher FOM around 500-700; traditional Miller compensated two-

stage amplifiers achieve a FOM of around 1000. State-of-the-artthree-stage Miller compensated amplifiers can achieve a FOM in the

3000-5000 range, and even over 10,000. [4, 5] As stated previously,these larger three stage Miller amplifiers require complexstabilization and compensation schemes, and can be significantly

large on silicon.

Table 2 shows the comparison of the amplifiers in this work tovarious types of operational amplifiers. The table includes all

parameters necessary for figure of merit calculation, as well as bot hthe power and current based figures of merit.

Many of the existing amplifier topologies listed in Table 2 consistof multiple stages, and employ complex stabilization schemes. Theseamplifiers are generally designed to have a high bandwidth and drive

large capacitive loads. Due to its current-starving nature, the inverter-based amplifiers are more suitable for smaller loads and less

stringent settling time requirements. Therefore, low power bio-applications will be able to take the full advantage of the design.

Trading for higher power consumption and lower FOMs, theinverter-based designs can be configured with higher supply voltageto drive larger loads as shown in Table 2. Even with the lower FOM

associated with the inverter based design at 1.1V supply voltage, itsFOM still surpasses some of the more complex designs.

TABLE 2:COMPARISON OF VARIOUS AMPLIFIERDESIGNS

Existing Designs Amplifier Type Process CL(pF) GBW(MHz) Power(mW@VDD) FOM 1 FOM2

TSEFC[3] 3-Stage Miller Comp. 0.35m 500 1.4 225@1.5 4666.5 3111

SMCFC[4] 3-Stage Miller Comp. 0.35m 150 1.6 21@1.5 17143 11430

MNMC[6] Multipath Nested MillerComp.

bipolar 100 100 76000@8 1056 132

NGCC[7] Multistage Nested Gm-CComp.

2m 20 0.61 680@2 36 18

NM CFNR[8] Nested Miller Comp. 0.8m 100 1.8 406@2 886 443DFCFC[10] 3-Stage w/Active Feedback

Freq. Comp.0.8m 100 2.6 420@2 1238 619

AFFC[11] 3-Stage w/Active FeedbackFreq. Comp.

0.6m 100 5.5 250@1.5 330 220

DLPC[12] Dual Path, Dual-Loop ParallelComp.

0.6m 120 7 330@1.5 3817.5 2545

ACBCF[13] 3-Stage AC Boosting Comp. 0.35m 500 1.9 324@2 5864 2932

700mV supply,Inverter-based

Inverter-Based 0.18m 1.8 0.4639 0.14532@0.7 4022 5746

900mV supply,

Inverter-based

Inverter-Based 0.18m 6 2.408 3.741@0.9 3475 3861

1.1V supply,

Inverter-based

Inverter-Based 0.18m 15 3.94 22.616@1.1 2874 2612

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CONCLUSION

In this paper, a fully-differential inverter-based amplifiertopology with the current starving feature has been evaluated. While

the idea of inverter based amplifiers is not conceptually novel, theidea of better controlling the current through the inverters using the

concept of current starving for low power applications, as well asbetter CMRR and common-mode control makes the concept ofinverter-based amplifiers more practical in real applications,

part icularly for applications for low p ower and low supply voltages.Simple modifications or considerations during the design phase can

considerably increase the circuits usability. The concept of self-cascoded transistors can be applied to the tail transistors to further

increase the benefits of increased impedance, such as additionalcurrent starvation and added common-mode noise and signal

rejection while not giving up too much headroom. The overall size ofthe transistors in the input inverter pair can be increased, allowing

this amplifier to be used in applications requiring a low-offset, low-noise op-amp. Tail transistor width, as well as input inverter pair

width can be increased, allowing higher current flow, making thistop ology useable in app lications requiring a high bandwidth.

The most advantageous principle of this topology is its simplicity.

As the task of designing low-voltage high gain amplifiers in sub-mdigital processes is becoming more complicated for designers, this

proves t o be a simple circuit to design and op timize. This topologyefficiently provides a significant gain for a single-stage amplifier,

and can be used in many configurations, including both continuoustime and switched-capacitor circuitry.

REFERENCES

[1] K-J. de Langen and J.H. Huijsing , Compact 1.8V low-poweroperational amplifier cell for VLSI, ISSCC, 1997.

[2] F. Schlogl, H. Zimmermann, Opamp with 106 dB DC gain in120nm digital CMOS,Solid-State C ircuits Conference, 2003.

ESSCIRC '03. Proceedings of the 29th European , vol., no.,pp .381-384, 16-18 Sept. 2003

[3] A. D. Grasso, G. Palumbo, S. Pennisi, Three-Stage CMOSOTA for Large Capacitive Loads With Efficient FrequencyCompensation Scheme,Circuits and Systems II: Express

Briefs, IEEE Transactions on , vol.53, no.10, pp.1044-1048,Oct. 2006

[4] S. O. Cannizzaro, A. D. Grasso, G. Palumbo, S. Pennisi,

Single Miller capacitor frequency compensation with nulling

resistor for three-stage amplifiers,Circuit Theory andDesign, 2007. ECCTD 2007. 18th European Conference on ,vol., no., pp .643-646, 27-30 Aug. 2007

[5] D. Marano, G. Palumbo, S. Pennisi, Analytical figure ofmerit evaluation of RNMC networks for low-power three-stage OTAs,Circuits and Systems (ISCAS), Proceedings of2010 IEEE International Symposium on , vol., no., pp.777-

780, May 30 2010-June 2 2010

[6] R. G. H. Eschauzier, J. H. Huijsing, A 100-MHz 100-dBoperational amplifier with multipath nested miller

compensation,IEEE J. Solid-State Circuits, vol. 27, no. 12,pp. 17091716, Dec. 1992.

[7] F. You, S. Embabi, E. Sanchez-Sinencio, Multistageamplifier topologies with nested Gm-C compensation,IEEE

J. Solid-State Circuits, vol. 32, no. 12, pp. 20002011, Dec.1997.

[8] K. N. Leung, P. K. T. Mok, Nested Miller compensation inlowpower CMOS design, IEEE Trans. Circuits Syst. I,

Fundam. Theory Appl., vol. 48, no. 4, pp. 388394, Apr. 2001.

[9] K. N. Leung, P. K. T. Mok, W. H. Ki, J. K. O. Sin, Three-stage large capacitive load amplifier with damping-factor-control frequency compensation, IEEE J. Solid-State

Circuits, vol. 35, no. 2, pp . 221230, Feb. 2000.[10] H. Lee, P. K. T. Mok, Active-feedback frequency-

compensation technique for low-power multistage amplifiers,IEEE J. Solid-State Circuits, vol. 38, no. 3, pp . 511520, Mar.

2003.[11] H. Lee, P. K. T. Mok, Advances in active-feedback

frequency compensation with power optimization and

transient improvement,IEEE Trans. Circuits Syst. II, AnalogDigit. Signal Process, vol. 51, no. 9, pp. 16901696, Sep.

2004.[12] H. Lee, K. N. Leung, P. K. T. Mok, A dual-path bandwidthextension amplifier topology with dual-loop parallel

compensation,IEEE J. Solid-State Circuits, vol. 38, no. 10,pp. 17391744, Oct. 2003.

[13] X. Peng, W. Sansen, AC boosting compensation scheme forlowpower multistage amplifiers, IEEE J. Solid-State Circuits,vol. 39, no. 11, pp. 20742077, Nov. 2004.

[14] C. Chanapromma, K. Daoden, A CMOS fully differentialoperational transconductance amplifier operating in sub-

threshold region and its application, Signal Processing

Systems (ICSPS), 2010 2nd International Conference on ,

vol.2, no., pp.V2-73-V2-77, 5-7 July 2010[15] M. Figueiredo, E. Santin, J. Goes, R. Santos-Tavares, G.

Evans, Two-stage fully-differential inverter-based self-biased

CMOS amplifier with high efficiency,Circuits and Systems(ISCAS), Proceedings of 2010 IEEE International Symposium

on , vol., no., p p.2828-2831, May 30 2010-June 2 2010[16] H. Voorman, H. Veenstra, Tunable High-Frequency Gm-C

Filters, JSSC, Aug. 2000[17] B. Nauta, A CMOS Transconductance-C Filter Technique for

Very High Frequencies, IEEE JSSC, vol. 27, no. 2, pp 142-153, Feb. 1992

[18] C.-L. Chen, Y.-C. Chang, Self-biased cross-coupled low-cost

fully-differential CMOS operational amplifier,Electronics

Letters , vol.41, no.9, p p. 512- 514, 28 April 2005

[19] E. Vittoz, Analog Circuits in Weak Inversion, in Sub-threshold design for ultra-low power systems. Springer, 2006.