Rev A 2003-12-18 1

Chapter 6Clocks and Synchronization

AXE Hardware Maintenance, LZU 108 6131

Rev A 2003-12-18 2

Objectives

• After this chapter you will be able to:– Describe what is implemented in the clock function.– Describe the clock hardware and cabling,– Configure the clocks.– Describe how network synchronization is delt with in AXE.– Configure network synchronization.

Rev A 2003-12-18 3

The BYB 501 1.4 Clock ModuleCL128M

Rev A 2003-12-18 4

CL128M ArchitectureAll three CLMs supply clock and sync to all diagonal SPMs (SPDBs) in both planes.

GS HWNS HW

CLT HW

RLCF

SPM Plane A

RLCFSPM Plane B

0…7

0…7

CLF

CLF

CLF

ICF

CL128M

CLREF 0-80…8

Rev A 2003-12-18 5

Subrack layout clock magazine CL128M

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

CC

B

CLB

-0

CC

B

CLB

-1

ICB

Slot

5C

RC

RC

R

Slot

4I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

2I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

3-4

8VC

LSC

LSC

LSC

LS

Slot

1-4

8VC

LSC

LSC

LSC

LS

8kS

8kS

8kS

(RC

LB-0

)

Slot

68k

S8k

S8k

S

Slot

7

Test

CC

BSl

ot 0

-48V

CLS

CLB

-2Sl

ot 1

I/OI/O

I/O

ICB

Slot

2

(RC

LB-1

)

Slot

38k

S8k

S8k

S

Slot

4

Test D

UM

MY

Slot

5

DU

MM

YSl

ot 7

RP4

-FSl

ot 8

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

EM

BTO

CC

R8k

S

CLS

CLS

CLS

CR

CR

CR

8kS

8kS

8kS

Slot

6

Rev A 2003-12-18 6

Board Types in CL128M

• CLB – Clock Board– Clock generation

• CCB – Clock Connection Board– Connects to SPDB

• RCLB – Reference Clock Board– Local Reference in case of loss of Incoming Reference– Generates 8 kHz signal to CLB

• ICB – Incoming Clock Board– Incoming references from ETC5, Cesium clocks, etc.– Generates 8 kHz signal to CLB

Rev A 2003-12-18 7

SW and HW names for CL128M

SW Name HW Name

CLM CLB

RCM RCLB

Rev A 2003-12-18 8

The split-cable for synchronization

Splitbox

ME4

ME2

ME3

ME1Single End

ME = Multiple End

Rev A 2003-12-18 9

CC

BSl

ot 1

-48V

CLS

CLS

CLS

CLS

The split-cable outlets towards GS, GS16M

35

2722

17

17

22

27

35

ME1ME2ME3ME4

SPM-A-0-0SPM-A-1-1SPM-B-0-0SPM-B-1-1SPM-A-2-2SPM-A-3-3SPM-B-2-2SPM-B-3-3SPM-A-4-4SPM-A-5-5SPM-B-4-4SPM-B-5-5SPM-A-6-6SPM-A-7-7SPM-B-6-6SPM-B-7-7

Split cable(Single End)in connector

number (on CCB)

Split cable(Multiple End)

SPMnumber

in GS16M

ME1ME2ME3ME4ME1ME2ME3ME4ME1ME2ME3ME4

SPD

B, S

PM-A

-1-1

Slot

9C

LKC

LKC

LKID

SPD

B, S

PM-A

-1-1

Slot

9C

LKC

LKC

LKID From CLM-0

From CLM-1

From CLM-2

Rev A 2003-12-18 10

SPD

B, S

PM-B

-0-0

Slot

9C

LKC

LKC

LKID

Split-cable example

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

CC

B

CLB

-0Sl

ot 2

I/OI/O

I/OE

MB

TOC

CR

8kS

Slot

1-4

8VC

LSC

LSC

LSC

LS

SPD

B, S

PM-B

-1-1

Slot

9C

LKC

LKC

LKID SP

DB

, SPM

-A-1

-1Sl

ot 9

CLK

CLK

CLK

ID

SPD

B, S

PM-A

-0-0

Slot

9C

LKC

LKC

LKID

From CLM-0

From CLM-1

From CLM-2

Rev A 2003-12-18 11

The split-cable outlets towards GS, GS4M

ME1ME2ME3ME4

-SPM-A-0-0SPM-B-0-0

-

Split cable(Multiple End)

SPMnumberin GS4M

SPD

B, S

PM-A

-1-1

Slot

9C

LKC

LKC

LKID

SPD

B, S

PM-A

-1-1

Slot

9C

LKC

LKC

LKID From CLM-0

From CLM-1

From CLM-2

CLB

-1Sl

ot 4

I/OI/O

I/OE

MB

TOC

CR

8kS

Rev A 2003-12-18 12

I/O cables and loop-back cables, CL128M

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

CC

B

CLB

-0

CC

B

CLB

-1

ICB

Slot

5C

RC

RC

R

Slot

4I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

2I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

3-4

8VC

LSC

LSC

LSC

LS

Slot

1-4

8VC

LSC

LSC

LSC

LS

8kS

8kS

8kS

(RC

LB-0

)

Slot

68k

S8k

S8k

S

Slot

7

Test

CC

BSl

ot 0

-48V

CLS

CLB

-2Sl

ot 1

I/OI/O

I/O

ICB

Slot

2

(RC

LB-1

)

Slot

38k

S8k

S8k

S

Slot

4

Test D

UM

MY

Slot

5

DU

MM

YSl

ot 7

RP4

-FSl

ot 8

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

EM

BTO

CC

R8k

S

CLS

CLS

CLS

CR

CR

CR

8kS

8kS

8kS

Slot

6

Rev A 2003-12-18 13

EM-BUS cable allocation, CL128M

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

AD

R

CC

B

CLB

-0

CC

B

CLB

-1

ICB

Slot

5C

RC

RC

R

Slot

4I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

2I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

3-4

8VC

LSC

LSC

LSC

LS

Slot

1-4

8VC

LSC

LSC

LSC

LS

8kS

8kS

8kS

(RC

LB-0

)

Slot

68k

S8k

S8k

S

Slot

7

Test

CC

BSl

ot 0

-48V

CLS

CLB

-2Sl

ot 1

I/OI/O

I/O

ICB

Slot

2

(RC

LB-1

)

Slot

38k

S8k

S8k

S

Slot

4

Test D

UM

MY

Slot

5

DU

MM

YSl

ot 7

RP4

-FSl

ot 8

-48V

RP

BR

PB

RP

BE

MB

AD

R

EM

BTO

CC

R8k

S

CLS

CLS

CLS

CR

CR

CR

8kS

8kS

8kS

Slot

6

EM

B

EM

B

Rev A 2003-12-18 14

Serial RP bus cable in CL128M

RP4

-FSl

ot 0

-48V

RP

BR

PB

RPB

EM

BE

MB

AD

R

CC

B

CLB

-0

CC

B

CLB

-1

ICB

Slot

5C

RC

RC

R

Slot

4I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

2I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

3-4

8VC

LSC

LSC

LSC

LS

Slot

1-4

8VC

LSC

LSC

LSC

LS

8kS

8kS

8kS

(RC

LB-0

)

Slot

68k

S8k

S8k

S

Slot

7

Test

CC

BSl

ot 0

-48V

CLS

CLB

-2Sl

ot 1

I/OI/O

I/O

ICB

Slot

2

(RC

LB-1

)

Slot

38k

S8k

S8k

S

Slot

4

Test D

UM

MY

Slot

5

DU

MM

YSl

ot 7

RP4

-FSl

ot 8

-48V

RP

BR

PB

RPB

EM

BE

MB

AD

R

EM

BTO

CC

R8k

S

CLS

CLS

CLS

CR

CR

CR

8kS

8kS

8kS

Slot

6

Rev A 2003-12-18 15

RCLB cables in CL128M

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

CC

B

CLB

-0

CC

B

CLB

-1

ICB

Slot

5C

RC

RC

R

Slot

4I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

2I/O

I/OI/O

EM

BTO

CC

R8k

S

Slot

3-4

8VC

LSC

LSC

LSC

LS

Slot

1-4

8VC

LSC

LSC

LSC

LS

8kS

8kS

8kS

(RC

LB-0

)

Slot

68k

S8k

S8k

S

Slot

7

Test

CC

BSl

ot 0

-48V

CLS

CLB

-2Sl

ot 1

I/OI/O

I/O

ICB

Slot

2

(RC

LB-1

)

Slot

38k

S8k

S8k

S

Slot

4

Test D

UM

MY

Slot

5

DU

MM

YSl

ot 7

RP4

-FSl

ot 8

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

EM

BTO

CC

R8k

S

CLS

CLS

CLS

CR

CR

CR

8kS

8kS

8kS

Slot

6

Rev A 2003-12-18 16

GS4M

Clocks in the 4K GS

Rev A 2003-12-18 17

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

TS4B

Slot

1D

L3D

L3D

L3D

L3E

MB

DL3

TS4B

Slot

1D

L3D

L3D

L3D

L3E

MB

DL3

SPD

BSl

ot 3

CLK

CLK

CLK

ID

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

SRSB

2Sl

ot 1

DL3

DL3

EM

B

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

Clocks in GS4M

CLB

-0Sl

ot 1

CLK

ICIC

EM

BIC

ICIS

I

CLB

-1Sl

ot 1

CLK

ICIC

EM

BIC

ICIS

I

(RC

LB)

Slot

38k

S8k

S8k

S

Slot

4

Test

CLB

-2Sl

ot 1

CLK

ICIC

EM

BIC

ICIS

I

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

SRSB

2Sl

ot 1

DL3

DL3

EM

B

RP4

-FSl

ot 0

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

SPD

BSl

ot 3

CLK

CLK

CLK

ID

TS4B

Slot

1D

L3D

L3D

L3D

L3E

MB

DL3

TS4B

Slot

1D

L3D

L3D

L3D

L3E

MB

DL3

RP4

-FSl

ot 7

-48V

RP

BR

PB

RP

BE

MB

EM

BA

DR

4K A-plane SRS-A Clocks and NS SRS-B 4K B-plane

Rev A 2003-12-18 18

CL128M Handling

Commands, OPIs, Printouts

Rev A 2003-12-18 19

Commands to handle the Clocks

• Create, delete and print:– GSCOI:CLM=clm, CLMV=clmv;

– GSCOE:CLM=clm;

– GSSTP[:CLM=clm];

• Block and deblock:– GSBLI:CLM=clm;

– GSBLE:CLM=clm;

• Test:– GSTEI:CLM=clm;

• Control value:– GSCVP;

Rev A 2003-12-18 20

Printout of the Group Switch State <GSSTP;GROUP SWITCH STATE

UNIT STATE BLSTATE VARIANT STATUS

CLM-0 WO 5 SLAVECLM-1 WO 5 MASTERCLM-2 WO 5 SLAVE

UNIT STATE BLSTATE VARIANT UNIT STATE BLSTATE

SPM-A-0-0 WO 11 SPM-B-0-0 WO

TSM-A-0 WO 31 TSM-B-0 WOTSM-A-1 WO 31 TSM-B-1 WOTSM-A-2 WO 31 TSM-B-2 WOTSM-A-3 WO 31 TSM-B-3 BLOC ABLEND

Rev A 2003-12-18 21

Printout of CLM Control Value

<GSCVP;GROUP SWITCH CLM CONTROL VALUE

CLM CONTRVALUE AVERAGEVALUE FAULTCASECLM-0 2119CLM-1 2048CLM-2 1966END

The value is an average of the value during one second in the oscillator

Rev A 2003-12-18 22

States and blocking states

The CLMs can have these different states:– BLOC Blocked– WO/S Working but suspected– WO Working

The BLSTATE parameter means blocking state:– MBL&CBL Manually and control-blocked – CBL Control-blocked (EM not working)– MBL Manually blocked (GSBLI/GSBLE)– TBL Test-blocked (During GSTEI command)– ABL Automatically blocked (Probably HW fault)

Rev A 2003-12-18 23

CLMV, Clock Module Variants

0 CLM16, BFD 324 0061 CLM64, BFD 117 034 and CLM4, BFD 323 5082 3CLM4, BFD 744 0013 CLM14, BFD 322 0234 CLM64C, BFD 748 533 5 ROJ 207 065/1 (in GS4M, BFD 511 012/n)6 CL128M, BFD 561 004/2 and BFD 561 009/27 GS16M-CLM, BFD 511 018/1

Rev A 2003-12-18 24

OPIs to handle the Clocks

• Group Switch, Clock Module, Connect/Repair

Rev A 2003-12-18 25

The AXE810 Clock ModuleCL890

Rev A 2003-12-18 26

The new Clock Module – CL890

GroupSwitch

AB

CLM(CGB, ClockGeneration

Board)

CLM(CGB, ClockGeneration

Board)

Rev A 2003-12-18 27

Clock Architecture in CL890

Switch corePlane A

and Plane B

8 kHzCLM(CGB-0)

CLM(CGB-1)

RCM(LRB)

ICF(IRB)

Stand aloneclock

(CBC orGSC)

MV

MV

2 Mbit/sGPS

ETC,ET155, RCM orStandaloneclocks

Rev A 2003-12-18 28

Target size

• Target size affects the implementation of clocks• 16K - Clocks in GEM 0-0• 128K - Clocks in GEM 0-0 and 0-1• 512K - Clocks in separate CLM subracks

Rev A 2003-12-18 29

GS Size Limited to 16k

XDB

XDB

IRB

CGB-0

CGB-1

IRB

SCB-RP

SCB-RP

8 device slots 8 device slots

Rev A 2003-12-18 30

GS Size Limited to 128k

XDB

XDB

IRB

CGB-0

CDB

SCB-RP

SCB-RP

8 device slots 9 device slots

CDB

XDB

XDB

IRB

CGB-1

CDB

SCB-RP

SCB-RP

8 device slots 9 device slots

CDB

Rev A 2003-12-18 31

GS Size up to 512k

SCB-RP

CDM-0

CDB CDB

CDB

CDBSCB-R

P

IRB

CGB-0LRB

SCB-RP

CDM-1

CDB CDB

CDB

CDBSCB-R

P

IRB

CGB-1LRB

Rev A 2003-12-18 32

Cabling from XDB Board

XDB

3 Vertical Connections

7 Horizontal Connections

2 Connections from clocks

1234567123

Rev A 2003-12-18 33

Clock cabling between CDB and CGB

XDB

CG

B-0GEM-0

CD

B

XDB

CD

B

XDB

CG

B-1

XDB

XDB

XDBGEM-2

GEM-1

CD

BC

DB

Rev A 2003-12-18 34

Commands to handle the clocks

• Define clocks:– GDCOI:UNIT=CLM-0/1,VAR=n;

– Variant value 10Synchronization is distributed in backplane. Only used in the 16K single-GEM switch.

– Variant value 11Synchronization sent through CDB via front cables to XDB

• Test clocks:– GDTEI:UNIT=CLM-0/1;

• Deblock clocks:– GDBLE:UNIT=CLM-0/1;

Rev A 2003-12-18 35

Printout of group switch state

<gdstp:unit=clm-0&-1;DISTRIBUTED GROUP SWITCH STATE

UNIT STATE BLSTATE VAR STATUS

CLM-0 WO 11 MASTERCLM-1 WO 11 SLAVE

END

Rev A 2003-12-18 36

Printout of CLM control values

gdcvp;DISTRIBUTED GROUP SWITCH CLM CONTROL VALUE

CLM OSCILLATOR CONTRVALUE AVERAGEVALUE FAULTCASE

CLM-0 0 2048 20491 2053 2050

CLM-1 0 2048 20491 2053 2050

END

Rev A 2003-12-18 37

Network Synchronization

Rev A 2003-12-18 38

The synchronization problem

Internal clock Internal clock

Out of synch

Traffic

Buffer

Rev A 2003-12-18 39

3 methods of synchronization

Master

Plesiochronous

Slave

Slave/2nd levelMaster

SlaveSlave

Master-slave

Mutual

Rev A 2003-12-18 40

Network Synchronization Modes

• Single Mode– Only one clock signal controls the exchange clock

(used for master-slave network synchronization)

• Multi Mode– A number of clock signals are used together for controlling the

exchange clock(normally used for mutual single-ended network synchronization)

Rev A 2003-12-18 41

Different Possible Clock References

• CCM Cesium Clock Module• RCM Reference Clock Module• DIP Digital Path Connected via SNT• SDIP Synchronous Digital Hierarchy DIP• EXT External Clock Reference

Rev A 2003-12-18 42

Commands to Handle the Synchronization

• Create/Delete:– NSCOI:RCM/DIP/CCM/EXT/SDIP=…,CLREFINL=…;

– NSCOE:RCM/DIP/CCM/EXT/SDIP=…;

• Block/Deblock:– NSBLE:RCM/DIP/CCM/EXT/SDIP=…;

– NSBLI:RCM/DIP/CCM/EXT/SDIP=…;

• Clock Reference Data:– NSDAC / NSDAP / NSDAR / NSDAT

• Test:– NSTEI:RCM/DIP/CCM/EXT/SDIP=…[,NOP];

Rev A 2003-12-18 43

Frequency Deviation and Wander

f

Time

NSDAC:RCM=RCM-0,FDL=20,WDL=10,ACL=A1;

8 kHz

Wander

Frequencydeviation

Rev A 2003-12-18 44

Printout of Clock Reference Supervision Data<NSDAP;CLOCK-REFERENCE SUPERVISION DATA

SYNCHMODE STATESINGLE OPERATING

STATIC DATA

REF CLREFINL REFGRP PRI FDL WDL ACLRCM-0 9 1 100 10 A2

DYNAMIC DATA

REF FD WD FREQMEMRCM-0 0 0 0END

Rev A 2003-12-18 45

Printout of the States of the Clock References

<NSSTP;CLOCK-REFERENCE STATE

RCM/CCM/DIP/EXT STATE BLSCCM-0 EXRCM-0 SBRCM-1 SB

END

Rev A 2003-12-18 46

OPIs to handle Clocks and Synchronization

• Network Synchronization, Initiate• Network Synchronization, End• Network Synchronization, Clock Reference, Connect• Network Synchronization, Clock Reference, Disconnect• Network Synchronization, Clock Reference, Repair