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A Digitally Controlled DC-DC Buck Converter Using

Frequency Domain ADCsHani Ahmad and Bertan Bakkaloglu

Ira A Fulton School of EngineeringArizona State University

Tempe, AZ 85287-08406, USA

Hani.ahmad@asu.edu, Bertan.bakkaloglu@asu.edu

Abstract- The design of a 0.18-m CMOS digital control

architecture for a buck converter is presented. Several features

are implemented. These include: 1) Frequency-domain

digitization technique based on first-order non-feedback Sigma-

Delta frequency Discriminators (NF-SDFD); 2) a robust

arrangement for the feedback ADCs to guard against false output

voltage variation due to temperature and process variation; 3) A

new improved hybrid Digital Pulse Width Modulator (DPWM)

architecture. The proposed system has additional attractive

futures such simplicity, scalability, low power, close to all digital

implementation in addition to its capability of satisfying tight

regulation requirements for wide range of applications. An 8-bit

ADC resolution is achieved with less than 110 A current

consumption. A 9-bit DPWM consumes around 370 A . A 2%

output voltage regulation accuracy is achieved with less than 10

mVpp ripple.

I. INTRODUCTION

A typical digital PWM DC-DC controller is shown in Fig. 1.

The main building blocks of such controller are the ADC,

compensator and digital PWM generator (DPWM) [1-3]. The

ADC and DPWM blocks are typically the most challenging to

design from the standpoint of power consumption, complexity

and area. In this work, we present new frequency-domaindigitization technique based on NF-SDFD [4-6]. Dual ADCs

in the feedback loop is implemented to guard against false

regulated voltage variation due to temperature, process or

external effects. This digitization architecture is simple,

scalable and can be implemented in standard digital CMOS

Figure 1 A typical digital PWM DC-DC controller

process. A high-frequency, high-resolution DPWM circuit isone of the critical blocks for successful practical realization ofdigital control for switching power converters A New hybridDPWM architecture; DLL followed by a counter is presented.

A charge-pump based DLL driving a counter is described togenerate the required duty cycle. This solution combines thetraditional advantages of the hybrid DPWM architecture [7]

with guaranteed linearity and monotonicity and lower power

consumption by using current-starved delay elements in theDLL.

II. PROPOSED ARCHITECTURE

The block diagram for the proposed architecture is shown in

Fig. 2. The digitized scaled output voltage is compared to thedigitized reference and the difference between the two (errorsignal) is then decimated and supplied to the compensator

(PID). The PID calculates the required duty cycle to set theoutput voltage at a desired value. Finally, the DPWM converts

this duty cycle value into a driver signal to drive the PFET andNFET via a gate driver. At regulation, the error signal should

be within the zero bin error of the ADC. In this ADCarchitecture, when output voltage and reference voltage are

equal, the VCOs and the frequency discriminators generatesimilar output and hence the difference is equal to zero.

Vin

PID

Compensator

Power Stage

Binary digits

L

C

Load

Discriminator

VCO

Discriminator

VCO

+-

Vref

Decimator

DPWM

GateDriver

Vout

Scalar

f1

f2

fref

fref

Z-1+

+Z

-1++

+++

+ Z-1++

X[n]

Y[n]

b3 b2 b1 b0

a1a2a3

4-bit DLL

5-bit Counter

IICC R

Figure 2 Proposed digitally controlled DCDC converter

architecture

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The first-order NF-SDFD is shown in Fig. 3. It digitizes

Figure 3 A first-order non-feedbacks SDFD

instantaneous frequency of a modulated carrier similar to anADC that digitizes the amplitude of input signals [4-6]. This

non-feedback SDFD is equivalent to the traditional modulator in the sense that it performs the same three main

functions on a signal similar to the traditional modulator. These

functions are integration, quantization and differentiation. Itaccomplishes the integration via the FM modulator; thequantization via the detection of the FM phase zero-crossings

position utilizing D-type flip flops (DFF) and the

differentiation via the digital differentiator gate (XOR).Fig. 4 depicts the block diagram of the proposed DPWM.

At the beginning of every switching frame, the DPWM output

is set. The selected delay of the DLL is used as input to theclock signal of the counter. Once the MSB bits match the count,

the DPWM outputs get reset. This new architecture produces aduty cycle with high linearity and guaranteed monotonicity.

With the DLL (Fig. 5) using current-starved inverter baseddelay elements, it aids lower power implementation. The DLL

is designed to generate 16 taps with 3.9ns (1/16Mhz/16) phasedelay between consecutive taps.

LSBs(4 bits)

Selected Delay

16-to- 1 MUX

MSBs

( 5 bits)

Counter

(5 bits)

D

Q

R

fswvdd

DPWM

out

Digital

Comparator(5 bits)

4_ bit DLL (16 taps)16 Mhz

clk

Figure 4 proposed DPWM architecture

The Gate drive shown in Fig. 6 is based on [8]. It has built in

dead time to avoid shoot through current. The transistors in the

gate drivers are designed to have enough strength to drive thepower FETs and generate appropriate dead time to prevent

shoot through current, and at the same time, minimize powerloss during switching. The PFET and NFET are sized up basedon 100m ohms on-resistance as a compromise for efficiencyand silicon area.

The PID is designed to achieve 60 degrees of phase marginand maintain stability with wide input voltage range and load

variation. A typical design procedure is followed inconstructing the PID transfer function and deriving the controllaw. For the decimator, A two-stage CIC structure is used with

16 MHz sampling frequency.

Figure 5 DLL architecture

Figure 6 Gate driver with built-in dead time

III. SCHEMATICS AND SIMULATION RESULTS

The design parameters used in this implementation are

listed in table 1 below.

Table IDESIGN PARAMETERS

Parameter Value Unit

Switching frequency 500 KHz

Cross-over frequency 50 KHz

fref(Sampling Frequency) 16 MHz

DPWM frequency 16 MHz

L 18.8 H

C 22 F

R in series with C 0.1

R in series with L 0.1

Vout 1.8 2% V

Vin 3.3 V

Imax 1 A

Load Transient 0.2-1 A

The schematic for the ADC is shown in Fig. 7. It is

composed of a VCO followed by first-order NF-SDFD. The

input control voltage x(t) at the input of the VCO represents

the converter output or reference voltage. The VCO is designed

to generate 5 MHz voltage at the set voltage level of 1.8 V. Its

transfer function has a slope of 2 MHz/V. The transfer function

of the VCO is shown in Fig. 8.

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Figure 7 ADC schematic

Figure 8 VCO transfer function

The DPWM is composed of 4-bit DLL followed by 5-bit

counter. The DLL is used for the fine resolution and thecounter is used for the coarse resolution. The schematicdiagram for the DLL is shown in Fig. 9.

The DLL is considered in lock state when the reference clockand the feedback clock from tap 16 have close to zero phase

shift, at which, the control voltage and the voltages to the delayelements remain constant as seen in Fig. 10.

The inductor current and the bias output voltage are shown

in Fig. 11. An expanded view of the inductor current and theoutput voltage is shown in Fig. 12.

Figure 9 DLL schematic

Vcontrol[V]

P_

bias[V]

N_

bias[V]

Figure 10 DLL in a lock state

Inductor Current (Zoomed in)

Output Voltage (Zoomed in)

I_inductor[A]

Vout[V]

Time [s]

I_Inductor

[A]

Vout[V]

Figure 11 Inductor current and output voltage with 200 mAload transient

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I_inductor[A]

Vout

[V]

Figure 12 Expanded views of Inductor current and outputvoltage

IV. CONCLUSIONS

Frequency-domain DC-DC digital control architecture withnew digitization technique and new hybrid DPWM architecture

is presented. The proposed digitization technique is simple,scalable and can be implemented in standard digital CMOS

process. The new hybrid DPWM guarantees high linearity andmonotonicity of the duty cycle in addition to its low powerimplementation. An output voltage regulation with 2%

accuracy has been achieved with less than 10 mVpp ripple.The 8-bit ADC resolution is achieved with less than 110 A

current consumption. The 9-bit DPWM consumes around 370

A .

.

REFERENCES

[1] Prodic, D. Maksimovic and W. Erickson, Design andImplementation of a Digital PWM Controller for a High-Frequency

Switching DC-DC Power Converter, IECON'01: The 27th AnnualConference of the IEEE Industrial Electronics Society, vol. 2, pp.

893-898, Nov 2001.[2] R .W. Erickson and D. Maksimovic, Fundamentals of Power

Electronics, Second Edition, Kluwer Academic Publishers, 2000.

[3] Syed, E. Ahmad and D. Maksimovic, Digital Pulse ModulatorArchitectures, 35th AnnualIEEE PESC, Aashen, Germany, vol. 6,pp. 4689-4695, June 2004.

[4] M. Hovin, A. Olsen, T.S Lande and C. Toumazou, Delta-SigmaModulators using Frequency-Modulated Intermediate Values

IEEE Journal of Solid-Sate Circuits, vol. 32, no. 1, pp. 13-22, Jan

1997.

[5] M. Hovin, T. Saether, A Narrow-band Delta-Sigma Frequency-to-Digital ConverterIEEE proc. ISCAS, vol. 1, pp.77-80, Jan 1997.

[6] D.T. Wisland, M E. Hovin, T.S. Lande, , A Novel MultibitParallel FMtodigital Converter with 24bit resolution,Proceedings ofthe 28th European Solid-State Circuits Conference,pp. 687-690, 2002

[7] Prodic, D. Maksimovic and W. Erickson, Design of a Digital PIDRegulator Based on Look-Up Tables for Control of High-

Frequency DC-DC Converters ,IEEE COMPEL,pp. 18 22, June

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[8] Changsik, A CMOS Buffer Without Short-Circuit, IEEETCASII, VOL. 47, NO. 9, September 2000.

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