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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010 2115

ADC Static Characterization UsingNonlinear Ramp Signal

Santosh C. Vora and L. Satish, Senior Member, IEEE

Abstract Static characteristics of an analog-to-digital con-verter (ADC) can be directly determined from the histogram-based quasi-static approach by measuring the ADC output whenexcited by an ideal ramp/triangular signal of sufciently lowfrequency. This approach requires only a fraction of time com-pared to the conventional dc voltage test, is straightforward, iseasy to implement, and, in principle, is an accepted method asper the revised IEEE 1057. However, the only drawback is thatramp signal sources are not ideal. Thus, the nonlinearity presentin the ramp signal gets superimposed on the measured ADCcharacteristics, which renders them, as such, unusable. In recentyears, some solutions have been proposed to alleviate this problem

by devising means to eliminate the contribution of signal sourcenonlinearity. Alternatively, a straightforward step would be to getrid of the ramp signal nonlinearity before it is applied to the ADC.Driven by this logic, this paper describes a simple method aboutusing a nonlinear ramp signal, but yet causing little inuence onthe measured ADC static characteristics. Such a thing is possiblebecause even in a nonideal ramp, there exist regions or segmentsthat are nearly linear. Therefore, the task, essentially, is to identifythese near-linear regions in a given source and employ themto test the ADC, with a suitable amplitude to match the ADCfull-scale voltage range. Implementation of this method revealsthat a signicant reduction in the inuence of source nonlinearitycan be achieved. Simulation and experimental results on 8- and10-bit ADCs are presented to demonstrate its applicability.

Index Terms Analog-to-digital converter (ADC) static charac-teristics, ADC testing, best segment identication, nonlinear ramp,quasi-static histogram testing, ramp testing.

I. INTRODUCTION

T HE RESOLUTION and speed of analog-to-digital con-verters (ADC) are constantly increasing due to advancesin very large scale integration design techniques, manufactur-ing, and newer architectures. It is well recognized that perfor-mance of even the best available high-speed high-resolutionADC is known to decline when acquiring fast-rising high-frequency nonrepetitive signals. Errors arising due to a loweredADC performance can tend to be unacceptable, particularlywhen higher accuracies have to be achieved, e.g., when theADC is a part of a reference measuring system and/or duringcalibration activities. Static and dynamic nonlinearities of theADC are accepted indices that assist in the evaluation of

Manuscript received May 15, 2009; revised August 8, 2009; acceptedAugust 12, 2009. Date of publication October 16, 2009; date of current versionJuly 14, 2010. The Associate Editor coordinating the review process for thispaper was Dr. Dario Petri.

The authors are with the High Voltage Laboratory, Department of Electri-cal Engineering, Indian Institute of Science (IISc), Bangalore 560012, India(e-mail: [email protected]; [email protected]).

Color versions of one or more of the gures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TIM.2009.2031852

performance and to ascertain suitability of ADCs for use in suchenvironments.

Literature reveals that estimation of static nonlinearity char-acteristic by conventional dc test [1][3] involves 69 h for a12-bit ADC. Undoubtedly, this much test time is prohibitivelyhigh, and in fact, it becomes unrealistic to test ADCs with morethan 12 bits. Therefore, there arises a need to reduce static testtime. This paradox attracted the attention of standardizationcommittees, and the outcome is evident in the IEEE 1057-2007 [1]. Specically with a view to reduce static test time,

this standard, in addition to the conventional dc test method,now permits the use of triangle-based histogram methods forstatic testing of ADCs. Although, overall testing time has beensignicantly reduced with this inclusion, the attention nowshifts to tackling the issue of nonlinearity contribution fromthe input signal. This is a bottleneck, and it affects the ADCresults. Therefore, it is imperative that newer methods that notonly reduce overall time of static test, but also can overcomethe effects of source nonlinearity on the measured ADC resultsare devised.

II. REVISED IEEE 1057-2007 A ND MOTIVATION

There is no doubt whatsoever that evaluation of static char-acteristics of high-resolution ADCs has to be accomplished bythe quasi-static histogram-based method using a ramp signalexcitation possessing a nonlinearity of less than one leastsignicant bit (LSB) [4]. As per denition, ramp nonlinearity isthe maximum deviation of the input excitation with referenceto the ideal ramp of the same amplitude and is quantiedas a percentage [4]. The presence of any linearity error inthe excitation automatically gets carried forward and appearsas an equivalent error in the measured ADC characteristics,signicantly affecting its shape and magnitude. Separation of the error contribution due to source nonlinearity from the actual

ADC errors is certainly not a trivial issue.The histogram-based static testing of high-resolution ADCs

necessitates a source, which can produce a highly linear spec-trally pure stable low-noise ramp/triangular signal [5]. As amatter of fact, signal sources satisfying these stringent require-ments may not be easily available (and even if available, theywould be expensive) to test such high-resolution ADCs. Forexample, to test a 16-bit ADC with an accuracy of 1/4 LSB,a source with a resolution of at least 18 bits and a linearityerror better than 0.0015% is needed. In contrast, commerciallyavailable analog ramp sources possess a linearity error of 0.1%[6] and a 16-bit digital source comes with an error of 0.0015%[7]. Thus, sources satisfying required specications are hard to

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2116 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010

nd, if not impossible. Therefore, some relaxations must bepermissible so that available nonideal sources could be used,of course, with suitable mechanisms to eliminate source errorcontributions from the measured ADC characteristics.

Most probably, as a direct consequence of taking this mat-ter into consideration, the revised IEEE 1057 includes three

methods based on triangular wave excitation, depending onthe resolution of the ADC under test and the accuracy of the triangle/ramp signal available. Individually, each of thesemethods has demonstrated its ability to signicantly reduce testtime. Further, the estimated ADC characteristics using thesemethods are in good agreement with those obtained from dctest. Perhaps, the only matter of concern is that every rampapplication covers only a few code bins. Hence, the number of ramp applications and the overall test time may tend to becomehigh with an increase in ADC resolution.

Therefore, in summary, it is evident that although ramp-signal-based characterization is the most appropriate for high-resolution ADCs, the presence of ramp nonlinearity is the mainissue that needs to be resolved. Fortunately, from a study of the analytical models of ramp signals reported in the literatureand based on actual measurements by authors on a few signalsources, it emerges that there exist particular regions or seg-ments of a nonideal ramp that are nearly linear compared to theentire ramp. Hence, identifying and utilizing the most linearsegment of the ramp to estimate static characteristics appears tobe encouraging and worthy of further consideration.

III. L ITERATURE

Ever since the standards included the conventional dc-based

test, it was quite obvious that the overall time for a static testwas going to be very high for high-resolution ADCs. Searchfor alleviating this problem began and led to the followingalternatives, which were, in principle, adhering to the mainphilosophy of the dc test, but were innovative and reducedtotal test time. Nevertheless, the reduction achieved was notsufcient enough. In this context, particular mention must bemade about the following methods: 1) the servo-loop-basedmethod [8]; 2) variable step-size estimation using extrapolatedconvergence factor algorithm [9]; 3) small triangular signalmethod [10]; and 4) the authors method based on a staircasesignal [11]. As a matter of fact, the superiority demonstratedby the triangular/ramp-based methods has been instrumentalin their inclusion into the standard [1], and a brief summaryemphasizing their ideas is included.

A method proposed in [7] exploits the noise property of ADCs and employs an imperfect ramp with a resolutionof about one standard deviation of ADC equivalent noise.In this method, every ramp application covers a few codebins. The signal ramps up the discrete steps to cover thefull-scale (FS) range of the ADC. A histogram of theoutput codes is generated, and the transfer characteristicis extracted from the resultant response.

The quasi-static histogram-based ramp vernier test [10],[12] is now one of the three standard methods [1]. Itemploys small-amplitude triangular signals with accuratedc biases to achieve reduction in ramp nonlinearity. This

method permits the use of low-linearity ramp sources, andthe reduced slope gives rise to nearly static test conditionsand uniformly stimulates code bins.

An algorithm is proposed to identify the stimulus errorand remove it accurately from the output data to estimateADC nonlinearity [13], employing two functionally re-

lated excitations. It is an accurate full-code test suitablefor production line tests and offers BIST capabilities. In [6], a unied error model based on triangular excitation

is proposed. Determination of the model parameters withsufcient accuracy can be achieved. The histogram proce-dures employed are different and utilize signal processingalgorithms to meet the source accuracy requirements.

In summary, it is evident that the ramp signal nonlinear-ity undermines the estimation of actual static characteristicof the ADC under test. It becomes imperative to attemptremoval/reduction of source nonlinearity contribution before itis applied to the ADC or employ postprocessing techniques

to eliminate it from the ADC output data. Adopting the for-mer option, this paper attempts a simple solution wherein aramp source having about 1012 times more than the speciednonlinearity could still be employed. Basically, the conceptis to make the ADC to see the most linear part of thenonlinear ramp and then estimate static characteristics by theconventional histogram-based test procedures.

IV. CONCEPT

The principle of the proposed method depends on the follow-ing two basic facts.

1) The percentage linearity of the ramp/triangle waveformremains practically unaltered irrespective of its ampli-tude [4]. This implies that the ramp/triangular waveformamplitude can be increased or decreased without signi-cantly affecting the percentage nonlinearity of the signal.This fact is veried (and found to be true) for a signalsource, whose result is presented later.

2) A nonlinear ramp waveform can be thought of as acurve, which can be approximated by a number of shortsegments of different lengths. It can easily be visualizedthat some of these segments can be much more linear (ina local sense), compared to the entire curve. Utilizingthis important concept, the most linear segment of thenonlinear ramp is to be determined. Once such a segmentis identied, its amplitude is suitably altered to matchthe FS voltage (FSV) range of the ADC to be tested.Finally, the ramp signal is provided with an appropriatedc bias/offset to ensure that only the most linear segmentof the ramp will be seen by the ADC. This is exactlywhat is required to measure the static characteristics. Asthe ramp amplitude is higher than the ADC FS range,the ADC converts only the most linear part of the rampwaveform that falls within its voltage range, while theremaining parts (lying outside the voltage range) areclipped and, later, discarded.

Analysis of models for source nonlinearity existing in literaturereveals that certain segments of the ramp could, in fact, be

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VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL 2117

Fig. 1. Nonlinear ramp and its nonlinearity considering the FS signal com-pared to that due to a segment. The reduction in % NL is evident.

more linear than the entire ramp. (Note: In some models, theopposite can also be true, i.e., some segments can possesshigher nonlinearity than the entire waveform.) Fig. 1 depictsthis basic idea. From the gure, it is evident that consideringthe entire waveform yields a nonlinearity of p%, whereas anarbitrarily chosen segment has only a small fraction of p%nonlinearity.

The amount of overdrive to be used is an important parameterto be selected in an FS ramp-based histogram testing. Theoverdrive requirement in a ramp signal is preferred mainly tominimize the bias error caused by input-equivalent noise. Anoverdrive also helps in avoiding inuence of high nonlinearityat the discontinuity. An overdrive, in most cases, equivalent to

three standard deviation of input equivalent noise is found tobe sufcient. Further details can be found in [14]. However,in the proposed method, only a part of the ramp (i.e., a ramp-segment) is being used as the input to the ADC. Parts of theramp signal above and below the selected segment are automat-ically clipped. Hence, the need for the overdrive is eliminated,unless the best segment is located at the extreme ends of the ramp.

A. Best Segment Identication

Generate a low-frequency ramp signal (about 10 Hz or less)

with an amplitude equal to N times the ADC input voltagesetting V fs . Typically, N can be chosen as 2 or more, de-pending on signal source capabilities. To determine the mostlinear segment (based on its percentage nonlinearity in a localsense) of the source output voltage V s (i.e., N V fs ), it isnecessary to scan the entire ramp signal for a selected segmentlength. One simple way is to select a segment length suchthat it exactly covers the ADC input voltage range. This is aconvenient choice, as this will excite all the ADC bins in asingle application. To begin with, let m overlapping segmentsbe chosen to scan the entire ramp signal. The number of segments (m) considered for identication of the best segmentis dictated by the overlapping desired. A larger value of m leadsto a higher identication time, and hence, initially selectingm to 11 was found convenient. The next task is to mea-

sure the segment linearity, and the following possibilities areincluded:

1) measuring the ramp generator values using a precisioninstrument during a calibration cycle and assumed to beknown to an appropriate absolute accuracy [7];

2) using a high-accuracy high-resolution sampling oscillo-

scope or a data acquisition board;3) obtaining the histogram-based static characteristics of

the ADC for every segment of the imperfect ramp andcomparing the segment-wise integral nonlinearity (INL)with the conventional dc-based static INL (i.e., true INL)obtained for the same ADC, thus establishing nonlinear-ity of each segment, from which best segment can beidentied.

The identied best segment, for a xed N and ADC FSrange, can be used for the future static testing of other ADCs.The actual procedure adopted for the identication of the bestsegment is described in Section VII. A ramp signal with an

appropriate dc offset will produce a particular segment at theADC input. For a bipolar ADC, the dc offset C i for the ithsegment is given as follows:

C i = V fs (N 1)2(i 1)m 1

1 , i = 1 , . . . , m (1)

where segment count starts from the positive peak and goesdown the ramp.

Fig. 2 depicts the difference between the conventional FSramp testing and the proposed method. Fig. 2(a) shows theconventional FS ramp testing, where the signal source outputvoltage (with small overdrive) is the same as the ADC FS range.As opposed to this, in the proposed case, the ratio of sourcevoltage output and the ADC input range (N = 4) is shownin Fig. 2(b). The ADC captures only a segment of the rampthat is within its vertical range (Fig. 2b), while the waveformoutside this range gets clipped. Data points corresponding tothe linear portion are gathered to build the histogram, whilethose corresponding to the clipped regions are discarded.

V. S IMULATION D ETAILS AND RESULTS

Simulations were performed for three nonlinear ramp modelsavailable in the literature [4], [6], [12] for different ADCresolutions and percentage nonlinearities. For brevity, results

are presented for 12-bit ADCs. The ADCs are modeled byconning its static INL (chosen randomly) to lie within 0.5%of the FSV or equivalent LSB. Further, this range of staticINL happens to be the prescribed limit recommended for adigital impulse waveform recorder to be used in an approvedmeasuring system [2]. The source models along with theirmaximum nonlinearity for producing a 1-V ramp signal is givenas follows:

x1 (t) = t 1 . 03 or t0 . 97 (1.09%NL)[4] (2)x2 (t) = t p + tq ( p = 0 .8, q = 1 .2, 1.1%NL , scaled )[6] (3)x3 (t) = t + 0 .04 (t 2 . 0 t) (1.00%NL)[12] (4)

By denition, the nonlinearity of a segment (or FS signal) is themaximum deviation of the segment (or FS signal) with respect

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Fig. 2. (a) Conventional FS ramp testing. (b) Principle of the proposed method. (Note: Signal source amplitudes for FS range and proposed method are different.)

Fig. 3. Nonlinear ramp signals (exaggerated for the sake of clarity), position of maximum nonlinearity, and best segment are marked for the models describedby (a) (2), (b) (3), and (c) (4).

to an ideal ramp of the same amplitude [4]. Fig. 3 depicts

the output signal produced due to the above three models,respectively, together with the ideal ramp and maximum non-linearity (vertical lines) marked. The best segment identied isalso marked with a thick line in Fig. 3(a) and (b). Particularattention must be paid to their individual shapes, nonlinearities,and locations as well.

All the three models output a ramp signal whose amplitudeis four times (N = 4) the ADC input voltage range, and thesegment amplitude equal to ADC voltage range is selected. It isnow required to examine which segment of the nonlinear ramp,in each model, is the most linear. The value of nonlinearityconsidering the entire ramp (FS) and for different positions of the segment along the ramp are determined and plotted in Fig. 4(starting by initially aligning the segment from the positive peak of the ramp). It is evident from Fig. 4 that, by using the proposed

method, as much as 90% and 96% reduction in nonlinearity is

achievable for the model in (2) and (3), respectively, whereasit is 77% in the case of the model represented by (4). Sinceeach source has its own nonlinearity (value and shape), oneshould not attach too much importance to the position of thebest segment with respect to the FS ramp.

In simulation studies, an ideal ramp signal and a nonidealramp signal modeled by (2) were used as the excitation for asimulated ADC. To begin with, maximum nonlinearity of aninput ramp wave was chosen to be 1.09%, which is much higherthan the desired value of 0.024% (corresponding to the 1 LSBrequirement of the 12-bit ADC [4]). The resulting static INLcharacteristics are presented in Fig. 5. The INL estimated fromthe FS ideal and FS nonlinear ramp is shown in Fig. 5(a), fromwhich it is evident that the ADC nonlinearity is superimposedon the concave-shaped source nonlinearity. However, Fig. 5(b)

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Fig. 4. FS and segment-wise percentage nonlinearity of the nonideal rampmodels described by (a) (2), (b) (3), and (c) (4).

Fig. 5. (a) INL characteristics due to FS ideal ramp and FS nonlinear rampwave [dened by (2)]. (b) INL characteristics due to FS ideal ramp and bestsegment of nonlinear ramp.

demonstrates the outcome due to the proposed technique. Usingthe most linear segment [segment 1, as per Fig. 4(a)] of thenonlinear ramp, the INL estimated is shown in Fig. 5(b) andcompared with the true INL. It is important to note that INL

( INL is the maximum difference between the true and theestimated INLs [4], [10]) in Fig. 5(a) is 44.6 LSB, conrmingthe 1.09% nonlinearity, whereas INL in Fig. 5(b) is just4.41 LSB (0.107%). It emerges that a reduction of 90% on theinuence of source nonlinearity is achievable, and hence, sucha ramp source with a nonlinearity as high as 0.24% can still beused to test a 12-bit ADC employing the proposed method.

Next, consider the nonlinear ramp model dened by (3), with p = 0 .9 and q = 1.1 corresponding to a maximum nonlinearityof 0.271% (or equivalently 11.08 LSB INL). Fig. 6(a) showsINL characteristics obtained for a different ADC model due toFS ideal and FS nonlinear ramp, whereas the INL estimateddue to the FS ideal ramp and that due to the best segment(segment 7) are depicted in Fig. 6(b). The estimated INL whenthe best segment is used is almost indistinguishable from that

Fig. 6. (a) INL characteristics due to FS ideal ramp and FS nonlinear ramp[dened by (3), with p = 0 . 9 and q = 1 . 1 ]. (b) INL characteristics due to FSideal ramp and best segment of nonlinear ramp.

due to the ideal ramp, thus proving the potential of the pro-posed idea.

The source model corresponding to (4) [Fig. 3(c)], as re-ported in [12], has an almost uniform nonlinearity in all thesegments, as depicted in Fig. 4(c). In such a case, any segmentalong the ramp would produce similar results. By raising thesource voltage to six times the ADC input range, an 84% reduc-tion in nonlinearity became achievable. This is a peculiar case,and such a source should be avoided, unless the best segmentnonlinearity is less than 1 LSB of the ADC. However, forreal sources, in general, the source contribution to nonlinearitycan be further reduced by raising the source amplitude and/or

reducing the ADC input range setting by selecting shortersegment lengths.

VI. EXPERIMENTAL DETAILS

The proposed technique was validated for three ADCs [two8-bit digital storage oscilloscopes and a 10-bit real-time digi-tizer (RTD)] using a 12-bit arbitrary waveform generator. Thedevices were computer controlled over GPIB and programswere coded in VEE Pro. The INL obtained for every deviceunder test (DUT) using the proposed test was compared withthat obtained by a conventional dc-based static test.

For testing of 8-bit digital storage oscilloscopes (DSOs) with

an FS ramp, the digital signal source was set to output anin-built ramp at a frequency of 10.01243398 Hz (fraction of frequency intentionally used to avoid coherent sampling) withthe voltage amplitude set to 0.25 V, with no offset. The DSOswere set to operate in 50 mV/div input range with a samplingfrequency of 20 ksamples/s. For implementing the proposedtest, the source voltage amplitude was set to 1.0 V (implyingN = 4 ).

For a 10-bit ADC FS testing with an FS ramp, the digitalsignal source was set to output an in-built ramp at the frequencyof 10 Hz with the voltage amplitude set to 0.5 V, with no offset.For implementing the proposed method, the source voltageamplitude was set to 0.8 V (corresponding to N = 1 .6). TheRTD was set for a voltage range of 0.5 V and a samplinginterval of 9 s.

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A small overdrive, as suggested in [14], was used whileperforming FS ramp testing of ADCs. An appropriate dc offsetwas calculated as per (1) for 11 overlapping segments, and eachsegment amplitude was set equal to the ADC input range inall the tests. The number of sample required to maintain theaccuracy level (to avoid code transition level uncertainty due

to noise as suggested by [1]) was met for FS histogram-basedtesting, as well as for the proposed testing, after discarding theclipped portions of the ramp. A minimum of 1024 samples percode bin were gathered to ensure uncertainty of code transitionlevel estimate to correspond to 12% of the rms noise level[1, clauses 4.7.3 and 4.7.10.1.1].

VII. EXPERIMENTAL RESULTS

A. Signal Nonlinearity Invariance Verication

The proposed technique exploits one of the basic propertiesof signal sourcesinvariance of the signal nonlinearity withits amplitude. Hence, linearity testing at various FSV ranges isnecessary. Of the three possibilities mentioned in Section IV-A,the results reported here are based on possibility #2, viz.employing an accurate high-resolution sampling oscilloscope.The sampling oscilloscope used in this case offered a 13-bitresolution when operated in the high-resolution mode. Selecta nonlinear ramp of frequency f in (e.g., 10.01243398 Hz)that is slightly offset with the oscilloscope sampling frequencyf s (e.g., 10 Hz). The signal amplitude and the scope verticalrange are set to be equal. Acquiring data with these settingsresults in the capture of successive samples on every subsequentramp cycle. Acquire sufcient samples to form an FS nonlinearramp, and construct an ideal ramp using the selected voltage

range to determine the ramp nonlinearity. The nonlinearityinvariance property was veried for a 12-bit signal source usedin this work. The linearity tests for FS ramp inputs were carriedout for four signal amplitudes, i.e., 200 mV, 800 mV, 2 V, and4 V at 10 Hz, and nonlinearity was found to be 1.194%, 1.206%,1.245%, and 1.285%, respectively (results are based on anaverage of ten measurements). Assuming the nonlinearity at2 V range as reference, the variation in nonlinearity for thetested range is about 0.04%, which can be considered asreasonable for low-precision testing.

B. Segment-Wise Linearity Estimation

The above-described procedure is repeated to determine thesegment-wise nonlinearity, with N = 4 , m = 11 , oscilloscopeinput range based on N , and signal source frequency andoscilloscope sampling rate settings as above. The measured% NL for these settings is plotted in Fig. 7. It is evident thatsegment 2 appears to be the best, and the nonlinearity has beenreduced to 0.28% which implies a reduction of 77% from itsinitial value (FS NL of 1.206%). It is evident that the bestsegment with a nonlinearity of 0.28% is suitable for statictesting of an 8-bit ADC.

C. ADC Static Characterization by the Proposed Method

In conventional static testing of ADCs, the input signal reso-lution is expected to be at least four times better than the resolu-

Fig. 7. Percentage nonlinearity estimated for individual ramp segments of the12-bit signal source.

Fig. 8. Static INL characteristics of an 8-bit ADC (DSO-1). (a) True INLand INL due to the FS nonlinear ramp. (b) True INL and INL due to the bestsegment of the nonlinear ramp.

tion of the ADC. To achieve a similar resolution, N > 4 is notfeasible for an 8-bit ADC using a 12-bit signal source. Hence,for the 8-bit DSO testing, the proposed method is employedwith N = 4 . (Note: ADCs have a maximum voltage that cansafely be applied to their inputs without risking damage. As aprecaution, when use of larger N is possible, it is recommendedto use a limiting circuit at the ADC input as a safeguard.)

The static INL measurements for two 8-bit ADCs are pre-sented in Figs. 8 and 9, respectively. In Fig. 8(a), static INLcharacteristics for DSO-1 obtained by the conventional dc-based test (true INL) and histogram-based FS nonlinear ramp

are compared. It is observed that the ADC characteristic issuperimposed on the signal source nonlinearity, rendering theINL results unusable and the source unt for the testing. The INL obtained from these data sets is 2.85 LSB, which impliesa source nonlinearity of 1.12%. Contrary to this, when theidentied best segment (segment 2) of the source was used toexcite the same ADC, the INL characteristic shown in Fig. 8(b)results. The true INL is also plotted in the same subplot. Agood match is seen at majority of the code bins, with INLbeing 0.6 LSB. Further, the true shape of the INL characteristicsand its ne structure are well reproduced. However, the minordifferences in the INL that still exist are due to the presenceof the residual nonlinearity in the best segment. Nonlinearityhas been signicantly reduced but not entirely eliminated. Thetime required to complete this test is about 3 min, which is

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Fig. 9. Static INL characteristics of an 8-bit ADC (DSO-2). (a) True INL andINL due to the FS nonlinear ramp. (b) True INL and INL due to best segmentof the nonlinear ramp.

inclusive of source signal generation, sample acquisition by theADC, data transfer to a personal computer, and removal of theclipped portion of the signal. In all, about 1.05 Msamples werecollected, of which 270 000 ( 1/N times) corresponded to thelinear portion and used to construct the histogram.

A necessity was felt to verify the possibility of using thesame best identied segment for another ADC(DSO-2), and theresults are presented in Fig. 9. Again, the effect of nonlinearityexisting in FS ramp is visible in Fig. 9(a), with reference tothe true INL of DSO-2. The identied best ramp segmentwas then applied for the determination of static INL, and theexcellent match is evident in Fig. 9(b). It thus proves the claimof the proposed method. The shape of the INL is preserved,

and the INL values are very close to the true values. A minorinuence of the residual nonlinearity of the best segment is stillperceivable in the results.

The proposed concept was next examined for a 10-bit ADCusing the same 12-bit signal source. Obviously, N in this casecannot exceed 1 for reasons discussed earlier. A large N willresult in a large number of hits for certain bins, which isundesirable. As a compromise to avoid this phenomena and yetexamine the applicability of the method, N = 1 .6 was selectedfor 10-bit ADC characterization, letting the source to be just2.5 times better than the DUT. The best segment identicationwas reworked for the desired ADC input range, and segment 1

emerged as the best segment. This shows that the best segmentlocation does not signicantly change with variations in N . Theresults are presented in Fig. 10. A considerable inuence of the existing nonlinearity of the FS ramp (indicating N = 1)on the ADC INL is observed in Fig. 10(a). The INL of 11.6 LSB, again, proves the source nonlinearity of 1.1%.Testing the ADC with the best segment (segment 1) resultsin the static INL shown in Fig. 10(b). In this particular case,1.7 Msamples were acquired, of which 1 050 000 correspondedto the best segment and were used to build the histogram. Thereduction in the ramp nonlinearity inuence is evident, while INL is 2.35 LSB, indicating a nonlinearity of 0.23%. Thelarge variations observed at certain code bins in Fig. 10(b) canbe attributed to the signal and DUT resolution ratio not beingfour times or better.

Fig. 10. Static INL characteristics of a 10-bit ADC (RTD). (a) True INL andINL due to the FS nonlinear ramp. (b) True INL and INL due to the bestsegment of the nonlinear ramp.

The simulation and experimental results prove that a low-linearity ramp source with an appropriate dc bias can be effec-tively employed to estimate the static INL characteristics of anADC. Some of the related issues are summarized as follows.

The method proposes to use a low-frequency ramp signal.However, the change in signal slope when using increasedvalues of N will not be appreciable since in all the cases, itwill be much less than the device slew rate, thus ensuringstatic-ness of the test.

The method excites all the ADC code bins in a singleapplication when the segment length spans a voltage thatis same as the ADC input voltage range. The sample

requirement and, hence, the test time, is N times thenumber of samples required by FS ramp and remainsconstant, irrespective of the ADC resolution. It indicatesthat the method is time efcient compared to the otherhistogram-based ramp test techniques.

The choice of N is governed by the resolutions of thesource and the ADC, or in other words, digital sourceswith a resolution better by at least 3 bits is preferred.Furthermore, with a greater value of N , subject to thesource capability, the segment linearity is expected toimprove.

Once the best segment is identied, acquisition of a largenumber of samples is the only component that involvestime since the proposal does not necessitate any major postprocessing.

VIII. C ONCLUSION

A simple and effective method has been described by whicha nonideal low-frequency ramp generator possessing more thanthe stipulated nonlinearity could still be employed to test anADC for estimating its static characteristics. Normally, a sourcemust have a nonlinearity of less than 1 LSB to qualify for usein such tests. However, by employing the proposed method,a signicant reduction in source nonlinearity accrues, therebyrendering it usable. The basic idea is to identify and use onlythe most linear segment/region of the nonlinear ramp to test the

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ADC, and a simple procedure for its identication is discussed.In summary, the proposed approach is not only time efcient,but also excites all the ADC code bins in a single application,involves very little post processing, and is capable of addressingissues concerning source nonlinearity to an acceptable extent.Experimental results on two 8-bit and one 10-bit ADCs demon-

strate the applicability of the approach.

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[3] Standard for Terminology and Test Methods for Analog-to-Digital Con-verters, IEEE Standard 1241-2000, 2001.

[4] F. C. Alegria, Proposal for high accuracy linearity test of triangularwaveform generators, in Proc. AFRICON , Sep. 2628, 2007, pp. 15.

[5] T. Kuyel, Linearity testing issuesof analogto digital converters, in Proc. Int. Test Conf. , 1999, pp. 747756.

[6] L. Michaeli, J. Saliga, and P. Michalko, Triangular testing signal for

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Santosh C. Vora was born in 1974. He received theB.E. degree in electrical engineering from SaurashtraUniversity, Gujarat, India, in 1997, and the M.E.degree in electrical engineering, with specializationin high-voltage engineering, from the Indian Insti-tute of Science (IISc), Bangalore, India, in 2004.He is currently on deputation from the Institute of Technology, Nirma University, Ahmedabad, India,to work toward the Ph.D. degree with the HighVoltage Laboratory, Department of Electrical Engi-neering, IISc.

His research interests include evaluation of ADC test techniques and high-

voltage measurements related instrumentation and diagnostics.

L. Satish (SM02) was born in 1964. He receivedthe Ph.D. degree from the Indian Institute of Science(IISc), Bangalore, India, in 1993.

He is currently a Professor with the High VoltageLaboratory, Department of Electrical Engineering,IISc. His research interests include ADC testing, ap-plication of signal processing to HV impulse testing,diagnostics, and condition monitoring.

Dr. Satishis a memberof theInternational Councilon Large Electric Systems (CIGRE) Working GroupD1-33.

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