04_Chapter 4 - Modular Comb Logic_2

8/12/2019 04_Chapter 4 - Modular Comb Logic_2

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Chapter 4

Modular Combinational Logic


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Decoders


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Decoders

n to 2ndecoder

n inputs

2noutputs

For each input, one and only one outputwill be active.

Uses:

Minterm generator

Wordline (memory) circuit

Code conversion

Routing data


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2 to 4 Decoder Example


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2 to 4 DecoderTruth Table

2 to 4 decoder

X1 X0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0


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2 to 4 Decoder Equations

0 1 0

1 1 0

2 1 0

3 1 0

Y X X

Y X X

Y X X

Y X X


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2 to 4 Decoder: Block Symbol

SymbolCircuit


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3 to 8 Decoder Example


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3 to 8 DecoderTruth Table

x2 x1 x0 y7 y6 y5 y4 y3 y2 y1 y0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0


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3 to 8 Decoder Equations

0 2 1 0

1 2 1 0

2 2 1 0

3 2 1 0

Y X X X

Y X X X

Y X X X

Y X X X

4 2 1 0

5 2 1 0

6 2 1 0

7 2 1 0

Y X X X

Y X X X

Y X X X

Y X X X


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3 to 8 Decoder: Circuit


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3 to 8 Decoder: Block Symbol

Symbol

Circuit


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Example

Using only a 3x8 decoder and two-input OR gates, design a logiccircuit which implements thefollowing Boolean equation

, , 2, 4,5F a b c m


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Solution

m2

m4m5


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2 to 4 Decoder with Enable


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2x4 Decoder with Enable

Enable is abbreviated as EN

EN is called a Control Signal

Control Signals can be Active High Signal

EN = 1 Turns ON Decoder

Active Low Signal

EN=0 Turns ON Decoder


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2 x 4 Decoder with Active High Enable

Truth Table

En x1 x0 y3 y2 y1 y0

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0


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2 to 4 Decoder with Enable Equations

0 1 0

1 1 0

2 1 0

3 1 0

n

n

n

n

Y E X X

Y E X X

Y E X X

Y E X X


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2 to 4 Decoder with Enable Circuit


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2 to 4 Decoder with Enable Symbol


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2 x 4 Decoder with Active High Enable

Truth Table (Short hand notation)

En x1 x0 y3 y2 y1 y0

0 d d 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

d = dont care

En has highest priority.If En=0, we dont care about x1 or x0 because Y=0


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2 x 4 Decoder with Active LowEnable

Truth Table (Short hand notation)

EnL x1 x0 y3 y2 y1 y0

1 d d 0 0 0 0

0 0 0 0 0 0 1

0 0 1 0 0 1 0

0 1 0 0 1 0 0

0 1 1 1 0 0 0

d = dont care

En has highest priority.If En=1, we dont care about x1 or x0 because Y=0


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2 to 4 Decoder with Active Low Enable

Circuit


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Design Example


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Example

Design a 3x8 decoder using only2x4 decoders and NOT gates.


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Solution

On when A=1

On when A=0


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Encoders


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Encoders

Opposite of a decoder

2n to n encoder

2n

inputs n outputs

For each input, the circuit willproduce an encoded output


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Example: 4to 2 Binary Encoder

Truth Table

X3 X2 X1 X0 Y1 Y0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Assume only one input high at a time!!


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4 to 2 Encoder Equations

0 1 3

1 2 3

Y X X

Y X X


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Problems with initial design

Q: How do we tell the differencebetween an input of all 0s (i.e.X=0) and X=1?

A: Add another output (IA) thatindicates that the input is valid.Lets make IA active low.

0 1 2 3IA X X X X


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Problems with initial design

If IA = 1 => all lines are 0

If IA = 0 => at least one line is 1

Q: What happens if more than one inputis high at the same time?

A: Design a priority encoder that willencode the input with the highest priority.

Lets set X3 with the highest priority,followed by X2, X1, and X0


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Example: 4to 2 Priority Binary Encoder

Truth Table

X3 X2 X1 X0 Y1 Y0

0 0 0 1 0 0

0 0 1 d 0 1

0 1 d d 1 0

1 d d d 1 1


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Solution

x3x2x1x0 00 01 11 10

00

01

11

10

Y1

x3x2x1x0 00 01 11 10

00

01

11

10

Y0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1 2 3Y X X 0 1 2 3Y X X X


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4 to 2 Priority Encoder Equations

0 1 2 3

1 2 3

Y X X X

Y X X

0 1 2 3IA X X X X


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Multiplexer/Data Selectors


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Multiplexer(MUX)/Data Selector

N to 1 multiplexer

n data input lines

Log2(n) control inputs

One output

This circuit will connect theselected input to the output. The

selected input is specified by adecoding of the control inputs.


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Example: 4to 1 MUX Truth Table

D3 D2 D1 D0 A B F

d d d D0 0 0 D0

d d D1 d 0 1 D1

d D2 d d 1 0 D2

D3 d d d 1 1 D3

d = dont care / Di = data on input i

Data InputsControlInputs

Output


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4 to 1 MUX Equation

0 1 2 3F D AB D AB D AB D AB 3

0

i i

i

F D m

Ds are the DATA inputs, AB are control inputs and calledthe select lines.


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4 to 1 MUX Circuit

2x4 Decoder Only a single AND gate willbe ON at a time.

Output

Control Inputs Data Inputs


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4 to 1 MUX Symbol

Data

Inputs

ControlInputs

Output


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Data and Control Paths

Logic

Data PathInputs

Data PathOutputs

Control PathInputs

Control PathOutputs


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MUX Applications


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Example

Using a 4x1 MUX, design a logiccircuit which implements:

Y a b We have,

Y

0 1 2 3Y D AB D AB D AB D AB


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Example

Using a 4x1 MUX, design a logiccircuit which implements:

Y a b

a b Y Dn

0 0 0 D0

0 1 1 D1

1 0 1 D2

1 1 0 D3

0 1 1 0Y AB AB AB AB AB AB


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Solution


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Multibit Multiplexers


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Multi-bit Multiplexers

J-bit nx1 mux

sel

d0d1

dn-1

d2 FJ bitsdeep

log2n

J bitsdeep

0

j

i i

i

F j D j m

j=0 to 3This is just J separatenx1 multiplexers


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Example 4-bit 4x1 MUX

A B

D0[3..0]

D1[3..0]

D3[3..0]

D2[3..0]F[3..0] 4 bits

deep

D0[3..0]

D1[3..0]

D2[3..0]

D3[3..0]

A B

F[3..0]

3

0

i i

i

F j D j m

j=0 to 3This is just 4 separate 4x1 muxes


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Example

4-bit 4x1 MUX

0 1 2 30 0 0 0 0F D AB D AB D AB D AB

0 1 2 31 1 1 1 1F D AB D AB D AB D AB

0 1 2 32 2 2 2 2F D AB D AB D AB D AB

0 1 2 33 3 3 3 3F D AB D AB D AB D AB

Bit 0

Bit 3

Bit 2

Bit 1


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Example 4 bit 4x1 MUX

For the jth output, we have

D0[j]

D1[j]D2[j]

D3[j]

A

B

F[j]


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For the bit 0 output, we have

D0[0]

D1[0]D2[0]

D3[0]

A

B

F[0]


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D0[1]

D1[1]D2[1]

D3[1]

A

B

F[1]


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D0[2]

D1[2]D2[2]

D3[2]

A

B

F[2]


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D0[3]

D1[3]D2[3]

D3[3]

A

B

F[3]


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Example 4 bit 4x1 Mux

F[0]

F[1]

F[2]

F[3]

Complete Circuit

Bit 0

Bit 1

Bit 2

Bit 3


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Symbol


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Design Example

Using a 4bit 4x1 MUX, design a 8bit

4x1 MUX


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Solution


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DeMultiplexers/Data Distributors


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Demultiplexer/Data Distributor

Opposite of a multiplexer

1 to N demultiplexer 1 data input

N data outputs Log2(n) control inputs

This circuit will connect a datainput to one and only one output.The selected output is specified by adecoding of the control inputs.


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Example: 1to 4 DeMUX Truth Table

D A B F3 F2 F1 F0

D 0 0 0 0 0 D

D 0 1 0 0 D 0

D 1 0 0 D 0 0

D 1 1 D 0 0 0

d = dont care / Di = data on input i


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1 to 4 DeMUX Equations

3 3F DAB Dm

j jF Dm

D is the DATA inputs, AB are control inputs and calledthe select lines.

1 1F DAB Dm

2 2F DAB Dm

0 0F DAB Dm


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1 to 4 DEMUX Circuit

Only 1 AND gate willbe ON

2x4 DecoderOnly oneF will beactive


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1 to 4 DEMUX Symbol

DataInput

Selected

Lines Outputs


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Example

Design a 3x8 decoder using only2x4 decoders and NOT gates.


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Solution

On when A=1

On when A=0

TUGAS


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1. Desain sirkuit dengan decoder dan gerbang eksternal untukfungsi boolean berikut :

F1 = XY + XYZ, F2 = Y + ZF1 = XY + XYZ, F2 = XZ + Y

F1 = XYZ + XZ, F2 = XYZ + XY, F3 = XYZ + XY

F1 = XYZ + YZ, F2 = XYZ + XY, F3 = XYZ + XY

2. Implementasikan fungsi boolean berikut dengan 4x1multiplexer

F(A,B,C) = (1,2,4,7)

F(X,Y,Z) = (0,3,5,7)

F(A,B,C) = (2,4,5,6)

3. Implementasikan fungsi boolean berikut dengan 8x1multiplexer

F(A,B,C,D) = (0,2,4,7,8,10,13,15)F(W,X,Y,Z) = (0,1,3,5,6,8,10,12)

F(A,B,C,D) = (1,4,7,9,11,13,14,15)


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Basic Arithmetic Elements

Half Adder


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Half Adder-Truth Table

S=A+B (arithmetic sum)

A B S1 S0

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

0S a b

1S ab


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Half Adder Circuit


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Full Adder-Truth Table

S=A+B+C (arithmetic sum)

A B C S1 S0

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

0S a b c 1S ab ac bc

A B C S1 S0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1


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Full Adder

0S a b c

1S ab ac bc You can show!!!

1S ab c a b


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Synthesis

(0)S A B C

Logic Equation

Logic Circuit


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Synthesis

(1)S AB C A B Logic Equation

Logic Circuit

Synthesis


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17

AND2 18

OR2

19 coutOUTPUT

16

AND2

VCC14 Cin INPUT

VCC13 B INPUT

10

XOR

11

XOR

15 sumOUTPUT

VCC12 A INPUT

Synthesis

Full Adder Circuit

S(0)

S(1)

C

AB

S(0)S(1)

Simulation


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Verification

S(0)S(1)

We verify the circuit via a simulation

Logic SimulationInputs

OutputsS 00 01 01 10 01 01 01 11


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17

AND2 18

OR2

19 coutOUTPUT

16

AND2

VCC14 Cin INPUT

VCC13 B INPUT

10

XOR

11

XOR

15 sumOUTPUT

VCC12 A

INPUT

Verification Summary

S(0)

S(1)

C

AB

S(0)

S(1)

Simulation

Circuit

D t ti


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Documentation

17

AND2 18

OR2

19 coutOUTPUT

16

AND2

VCC14 Cin INPUT

VCC13 B INPUT

10

XOR

11

XOR

15 sumOUTPUT

VCC12 A

INPUT

S(0)

S(1)

C

AB

FullAdder

C

ABS(0)

S(1)

Block Diagram


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Ripple Carry Adder


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Conceptualization

4-bit adder (worst case)

1111

111111110

111

For the worst case we need to add

three bits to generate a single output bitwith a possible carry out.

Can we use our single bit adder for this?


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Ripple Carry Adder

We can cascade several full addersto create a ripple carry adder

The circuit gets its name becausethe carry bit ripples from one bitposition to the next


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Conceptualization

FullAdderC

A

B S(0)

S(1)

FullAdder

C

AB

S(0)

S(1)

First, lets look at two bits

A(0)

B(0)

B(1)

A(1)

Sum(0)

Sum(1)

What about the carry?


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Conceptualization

FullAdderC

A

B S(0)

S(1)

FullAdder

C

AB

S(0)

S(1)

Lets connect the two full adders

A(0)

B(0)

B(1)

A(1)

S(0)

S(1)

Set carry in for first bit to 0. Why?

Cout

Cin

0


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Analysis

FullAdderC

A

B S(0)

S(1)

FullAdder

C

AB

S(0)

S(1)

Lets test this for a few cases:

0

0

0

0

0

0

0

0

0

0

00

00000

Correct!!!

Rule of thumb: Always test simple cases first!!


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Analysis

FullAdderC

A

B S(0)

S(1)

FullAdder

C

AB

S(0)

S(1)

Lets test this for the a few cases

0

1

1

1

1

1

1

0

1

1

11

11110

Correct!!!


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Analysis

FullAdderC

A

B S(0)

S(1)

FullAdder

C

AB

S(0)

S(1)

Lets test this for the a few cases

1

1

0

0

0

1

1

1

0

0

01

01010

Correct!!!


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Four Bit Ripple Adder

Carry in

Carry out


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Logic Simulation


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8-bit Ripple Carry Adder

Use two 4-bit adders


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16-bit Ripple Carry Adder

Use two 8-bit adders


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Subtraction Circuit

Calculate 2s complement of B

Add B to A

ADDER

INV

A

B

S

1

Cin

A

B

1S A B A B A B

B

1

1S A B


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Add/Sub Circuit


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Add/Sub Circuit Module

Add/SubModule

A

B

S

Add

A

B

Add

S


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Function Table for Add/Sub Module

Add Functional

Result0 S=A+B

1 S=A-B

Add is a control input. It is active low. This meansthat the module will compute A+B when Add=0. Itwill compute A-B when Add=1.


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Add/Sub Circuit

Design using Modules


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Add/Sub Circuit

ADDER

INV

2x1

MUX

A

B

S

B

B

A

S Cin

A

Add


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Add/Sub Circuit

ADDER

INV

2x1

MUX

A

B

S

B

B

AS Cin

A

Add

Add operation. Add=0

0 0

S A B


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Add/Sub Circuit

ADDER

INV

2x1

MUX

A

B

S

B

B

AS Cin

A

Add

Sub operation. Add=1

1 1

1S A B

B


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Overflow/Underflow Detection


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Numerical Overflow/Underflow

2s complement number

We have S=A+B

Range of sum

Overflow occurs if

Underflow occurs if

1 12 2 1n nS

12 1nS

12

nS


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Example: Overflow

Let n=4, Range is

Let A=$7, B=$7, thenS=$7+$7=$E, but $E=%1110 = -2,so Overflowhas occurred.

8 7S

3 3

2 2 1S


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Example: Overflow

Lets examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+7

So, overflow is the same as wrap around.

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7


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Example: Underflow

Let n=4, let A=-7 and B=-7,

in 2s complement, A=B=$9,S=$9+$9=$12=$02

so underflowhas occurred.


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Example: Underflow

Lets examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+6

So, underflow is the same as wrap around.

+1


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How do we detect overflow andunderflow?

First adding a positive to a negative

number is always OK. 4 bit example: 7 + (-8) = -1

Lets examine the sum of the MSBs todetermine overflow and underflow.

Set V=1, if overflow/underflow occurs


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Examination of MSB

b a cin S Co V Explanation

0 0 0 0 0 0 A+B < 2n-1 (OK)

0 0 1 1 0 1 A+B>2n-1

-1 (overflow)

0 1 0 1 0 0 -A+B (OK)

0 1 1 0 1 0 -A+B (OK)

1 0 0 1 0 0 A-B (OK)

1 0 1 0 1 0 A-B (OK)

1 1 0 0 1 1 -A-B< -2n-1 (underflow)

1 1 1 1 1 0 -A-B > -2n-1 (OK)

a,b are the MSBs of A and B. cin is carry in; cout=carry out


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We find

1 1 , 1 1 1 , 1n n in n n n in nV a b c a b c


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, 1 , 1in n out nV c c

You can also use

That is, if for the MSB carry_in isnot equal to carry_out, overflow or

underflow has occurred.


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Comparators

C


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Equal Comparator

Design a logic circuit which willcompute

F0 = (A = B)


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2-bit Equal Comparator Truth Table

b1 b0 a1 a0 F0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 11 0 1 1 0

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1


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N bit E l C t


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N-bit Equal Comparator

0 1 1 1 1 0 0n nF a b a b a b

N t E l C t


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Not Equal Comparator


F = (A B)

F = (A = B)i.e. Just invert our Equal Comparator circuit

M it d C t


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Magnitude Comparator


F2 = (A>B)

F1 = (A


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Truth Table

b1 b0 a1 a0 F2 F1

0 0 0 0 0 0

0 0 0 1 1 0

0 0 1 0 1 00 0 1 1 1 0

0 1 0 0 0 1

0 1 0 1 0 0

0 1 1 0 1 0

0 1 1 1 1 0

2-bit Magnitude (unsigned) Comparator

T th T bl


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Truth Table

b1 b0 a1 a0 F2 F1

1 0 0 0 0 1

1 0 0 1 0 1

1 0 1 0 0 01 0 1 1 1 0

1 1 0 0 0 1

1 1 0 1 0 1

1 1 1 0 0 1

1 1 1 1 0 0

Y h


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You can show

2 1 1 0 1 0 1 0 0F a b a b b a a b

1 1 1 1 0 0 0 1 0F a b a a b a b b


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Arithmetic Logic Units (ALUs)

Arithmetic Logic Unit (ALU)


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Arithmetic Logic Unit (ALU)

ALU

A[n-1,,0]

B[n-1..0]

F

S[m-1..0]

A,B are data inputs of n bits each in depth

S is a control input. We have 2m

operationsF is the output

Example


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Example

Let n=4,m=3 We have A[3..0] and B[3..0]

With m=3, we have 23= 8 operations

Lets look at a possible function table

Function Table


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Function Table

s2 s1 s0 Function

0 0 0 F=AB

0 0 1 F=A+B (logical OR)

0 1 0 F=NOT A0 1 1 F=A XOR B

1 0 0 F=A+B (Arithmetic)

1 0 1 F=A-B1 1 0 F=A + 1

1 1 1 F=A - 1

Design using a Truth Table


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Design using a Truth Table

How large is the truth table? 2n from data inputs A and B

Example: n=8, we have 16 data inputs A[7..0] and B[7..0]

3 control inputs Total of 2n+3 inputs

N=8, we have 19 inputs

Our truth table will have 192(361) rows and 8 outputs

Too complex. Lets explore anotheralternative using a system or modularapproach



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Note:

For S2=0, we have logic operations

For S2=1, we have arithmetic

operations So, lets use S2 to control a 2x1 MUX

to select between logic and arithmeticoperations, so our top level design

would look like:

ALU Design


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ALU Design

Logic

Module

Arithmetic

Module

2x1

MUX

S[2]

A B

A

A

B

F

A

BF

S[1..0]

S[1..0]

B

F F

ALU Design S2=0


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ALU Design S2=0

Logic

Module

Arithmetic

Module

2x1MUX

S[2]

A B

A

A

B

F

A

BF

S[1..0]

S[1..0]

B

F F

With S2=0, F is the output fromthe logic module

ALU Design S2=1


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ALU Design S2=1

Logic

Module

Arithmetic

Module

2x1MUX

S[2]

A B

A

A

B

F

A

BF

S[1..0]

S[1..0]

B

F F

With S2=1, F is the output fromthe arithmetic module


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Logic Module Design

Function Table for Logic Module


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Function Table for Logic Module

S2=0

s2 s1 s0 Function

0 0 0 F=AB0 0 1 F=A+B (logical OR)

0 1 0 F=NOT A

0 1 1 F=A XOR B

We can use a 4x1 mux toimplement this module

Logic Module Design


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Logic Module Design

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

Logic Module Design


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Logic Module Design

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

AND OperationS[1..0]=00

0 0

F=AB

Logic Module Design


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Logic Module Design

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

OR OperationS[1..0]=01

0 1

F=A+B

Logic Module Design


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Logic Module Design

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

NOT OperationS[1..0]=10

1 0

F=A

Logic Module Design


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Logic Module Design

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

XOR OperationS[1..0]=11

1 1

F=A XOR B


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What do these logic modules

look like?

AND Module


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AND Module

ANDA

B

F

OR Module


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OR Module

OR

A

B

F

NOT Module


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NOT Module

NOTA F

XOR Module


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XOR Module

XOR

A

B


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Arithmetic Module

Lets use our ADD/SUB Module



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Add/SubModule

A

B

S

Add

A

B

Add

S

Function Table for Arithmetic Ops


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Function Table for Arithmetic Ops

s2 s1 s0 Function

1 0 0 F=A+B (Arithmetic)

1 0 1 F=A-B

1 1 0 F=A + 11 1 1 F=A - 1

Note:S0 can be use to indicate Addition or Subtraction.S1 can be use to indicate the B data input

Arithmetic Module Design


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Add/SubModule

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S



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Add/SubModule

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S

00

F=A+B

S[1..0]=00



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Add/SubModule

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S

10

F=A-B

S[1..0]=01



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Add/Sub

Module

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S

01

F=A+1

S[1..0]=10



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t et c odu e es g

Add/Sub

Module

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S

11

F=A-1

S[1..0]=11


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Overall Design

We have

ALU Design


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g

Logic

Module

Arithmetic

Module

2x1

MUX

S[2]

A B

A

A

B

F

A

BF

S[1..0]

S[1..0]

B

F F

Logic Module Design


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g g

OR

NOT

XOR

AND

A

B

C

D

4

X

1F

S[1..0]

S1 S0

A

A

BF

A

B

F

A

B

F

A F

B



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g

Add/Sub

Module

S0

A

B

Add

S

S

2

X

1

A

B

FVDD

S1

B

A

S

Total Design


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g

OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

Add/SubModule

A

S

S0

A

B

Add

S

B

S

F2X1

S2

S

2X1

A

B

FVDD

S1 S0

S1

A B

A

B

F

A

BF

A

B

F

A F

Logic Module

Arithmetic Module


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End of Chapter 4

04_Chapter 4 - Modular Comb Logic_2

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