IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER 2007 755

A High Slew-Rate Push–Pull Output Amplifier forLow-Quiescent Current Low-Dropout Regulators

With Transient-Response ImprovementTsz Yin Man, Student Member, IEEE, Philip K. T. Mok, Senior Member, IEEE, and

Mansun Chan, Senior Member, IEEE

Abstract—A high slew-rate amplifier with push–pull outputdriving capability is proposed to enable an ultra-low quiescentcurrent ( 1 A) low-dropout (LDO) regulator with im-proved transient responses. The proposed amplifier eliminates thetradeoff between small and large slew-rate that is imposedby the tail-current in conventional amplifier design. Push–pulloutput stage is introduced to enhance the output driving ability.Small dropout voltage ( DO) with large-size pass transistor andultra-low can thus be used to minimize power loss of LDOregulator without transient-response degradation. The proposedamplifier helps to improve stability of LDO regulators withoutusing any on-chip and off-chip compensation capacitors. This isbeneficial to chip-level power management requiring high-areaefficiency. An LDO regulator with the proposed amplifier has beenimplemented in a 0.18- m standard CMOS process and occupies0.09 mm2. The LDO regulator can deliver 50-mA load current at1-V input and 100-mV DO. It only consumes 1.2 A and isable to recover within 4 s even under the worst case scenario.

Index Terms—High slew rate, low-dropout (LDO) regulator,low-quiescent current, tail current.

I. INTRODUCTION

LOW-DROPOUT (LDO) regulators are often used inbattery-powered mobile systems requiring small size

and clean supply voltage. To prolong the battery life, powerefficiency of LDO regulators can be improved by reducing thequiescent current ( ) and dropout voltage ( ). Fig. 1(a)shows the regulator efficiency as a function of load current( ) with different and under a particular output voltage( ) and . It shows that the use of ultra-low effec-tively improves the regulator efficiency at small , whichoften happens when systems are operating in standby modeto extend the battery life. From the efficiency expression inFig. 1(a), small also improves the regulator efficiency andthis improvement is more significant in the small case.

However, reduction of and unavoidably slows downthe transient responses of an LDO regulator. This can be ex-plained with a generic LDO regulator shown in Fig. 1(b). Thetail-current of amplifier is equal to of the LDO regulator.

Manuscript received January 15, 2007; revised April 3, 2007. This work wassupported by the Research Grant Council of Hong Kong SAR Governmentunder Project 617705. This paper was recommended by Associate EditorT. C. Carusone.

The authors are with the Department of Electronic and Computer Engi-neering, The Hong Kong University of Science and Technology, Hong Kong.(e-mail: eesm@ece.ust.hk; eemok@ece.ust.hk; mchan@ece.ust.hk).

Digital Object Identifier 10.1109/TCSII.2007.900347

Fig. 1. (a) Plot of regulator efficiency. (b) Schematic of LDO regulator withconventional amplifier. (c) Plot of regulator dropout voltage.

Since this sets the maximum current to charge and dischargethe gate capacitance ( ) of the pass transistor, requirementof ultra-low inevitably reduces the slew-rate ( ) atthe gate of the pass transistor. Transient responses are thereforedegraded.

reduction also degrades transient responses of an LDOregulator. As shown in Fig. 1(c), can be reduced byenlarging the width of the pass transistor ( ). To achievethe same at smaller input voltage ( ), needs tobe greatly enlarged to compensate for the limited gate-drivevoltage. As is proportional to , time requiredto charge or discharge is greatly increased when bothultra-low and small at low are required. Transientresponses of an LDO regulator are hence significantly degraded.

of existing LDO regulators [1]–[6] is normally rangedfrom several tens of to few hundreds of microamperes. For ap-plications required ultra-fast responses [7], the is up to sev-eral thousands of microamperes. Efficiency of those LDO reg-ulators at small is degraded.

In this work, a high slew-rate amplifier with push–pull outputstage is thus proposed to enable an ultra-low LDO regulator

1549-7747/$25.00 © 2007 IEEE

756 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER 2007

Fig. 2. Conceptual schematic of an LDO regulator with the proposed high slew-rate amplifier with push–pull output configuration.

with improved transient responses. Concept of the proposed am-plifier is discussed in Section II. Circuit design and implemen-tation are shown in Section III. Experimental results and con-clusions are given in Sections IV and V, respectively.

II. CONCEPT OF PROPOSED AMPLIFIER

Fig. 2 shows the conceptual schematic of an LDO regu-lator with the proposed amplifier, which is constructed bytwo common-gate differential-input transconductance ( )cells, and , and a current-summation circuit. Each

-cell is made by a constant current source ( ) and a pair ofmatched transistors, and , in the form of current mirror.

The maximum output current of -cell ( ), and there-fore the maximum amplifier-output current ( ), are no longerlimited by the constant-current source as in the case ofconventional amplifier with a tail-current. As shown in Fig. 2,the common-gate configuration enables depending onits input-voltage difference, which is the difference betweenthe reference voltage ( ) and the . Since all the tran-sistors of the -cell operate in saturation region has aquadratic dependence on its input-voltage difference accordingto the square-law characteristic of MOS transistor [8]. Even ifan ultra-low is used, the amplifier-output current ( ) andalso the amplifier slew-rate is no longer limited.

High slew-rate in both positive and negative direction isachieved with the current-summation circuit and the cross-cou-pled connection scheme. As shown in Fig. 2, the inputs of thetwo -cells, and , are connected in a cross-cou-pled manner. The outputs of -cells are connected by acurrent-summation circuit. Regardless of whether thebecomes larger or smaller than the during transientresponses, the large from either one of the -cells isable to charge or discharge the gate capacitance quickly.As a result, both positive and negative direction slew-rates canbe successfully enhanced even if an ultra-low is used.

The small input-resistance of the -cell helps to improvestability of LDO regulator without using any off-chip andon-chip compensation capacitors. As shown in Fig. 2, thesource terminal of transistor insider the -cell, ,is directly connected to the output of the LDO regulator. Theopen-loop output resistance of LDO regulator is now modifiedfrom its original value to . Thisprovides the regulator with a small open-loop output resistanceunder a wide range of from several tens of milliamperesto several A. Even the output-parasitic capacitance ( )due to the metal lines used to perform chip-level power distribu-tion is as large as several hundreds of pF (e.g., ), theregulator-output pole is stilllocated at high frequency and much far away from the low-fre-quency amplifier-output pole ( ). Stabilityof an LDO regulator with the proposed amplifier is greatlyimproved without using any on-chip and off-chip compensationcapacitors. Area efficiency of such LDO regulator is highlyimproved. This is particular suitable for chip-level powermanagement requiring multiple LDO regulators with highchip-area efficiency. In case a large off-chip output capacitor isused to improve transient responses under fast changing loadcurrent, stability of proposed LDO regulator can be achievedlike conventional LDO regulators by the pole-zero cancellation[3], [5] where the zero is generated from the output capacitorand its equivalent-series resistor.

III. CIRCUIT DESIGN AND IMPLEMENTATION

Fig. 3 shows the schematic of the proposed LDO regulator,which consists of a pMOS pass transistor ( ), the pro-posed high slew-rate push–pull output amplifier and a refer-ence buffer. As mentioned before, the reduction, especiallyunder a very-low (e.g., 1 V in our case), is very important tothe efficiency improvement and is usually achieved by enlargingthe pass transistor width . Hence, to provide 50-mA loadcurrent at 100-mV dropout under 1-V input, the aspect ratio of

( ), where is the channel length of, is chosen to be 5940 m/0.18 m in a 0.18- m stan-

dard CMOS process where the threshold voltage of is.

To ensure the proposed amplifier has fast-transient responsesand large voltage-gain for input-offset reduction, the channellengths of all transistors except the are designed to betwo and half times of the minimum feature size of 0.18- mprocess, which balances the tradeoff between the need for small-gate capacitance and large-drain resistance.

To make sure the proposed regulator can be tested under sev-eral- A (e.g., 1.2 A in our case), gate-to-source voltageof , , and , (e.g., ) is generated by injectinga well-defined DC current to the drain terminal of diode-con-nected transistor (not shown in Fig. 3) that has the same size asand is closely integrated on the same chip with, , ,and . Impact of process variation on the bias current (e.g.,100 nA in our case) generated by those transistors is greatly min-imized. It is important to note that conventional supply-insensi-tive biasing circuits [8] can be used to define the and be inte-grated with the proposed LDO regulator without any problems.

The proposed amplifier is constructed by two common-gate-cells, and , and a current-summation circuit. As

MAN et al.: HIGH SLEW-RATE PUSH–PULL OUTPUT AMPLIFIER 757

Fig. 3. Schematic of an LDO regulator with the proposed high slew-rate push–pull output amplifier and a reference buffer.

TABLE IDIMENSIONS OF TRANSISTORS

shown in Fig. 3, the ( ) consists of two pMOS transis-tors, and ( and ), and one nMOS transistor,

( ), acting as a constant-current source. Mismatch be-tween the input transistors (e.g., and ) can be reducedwith methods commonly used in conventional amplifier designsuch as placing these input transistors with common-centroidmethod and designing them in large width. The current-sum-mation circuit is made by three current mirrors, and ,

and , and and , respectively.To enable the proposed amplifier with sink and source output-

driving ability, the three current mirrors are required to con-struct the push–pull output stage. As shown in Fig. 3, the cur-rent mirror constructed with transistors, and , redirectsthe output current of to the amplifier output. The largetransient-output current of is now able to discharge thelarge gate capacitance of , from which sink ability isachieved. Source ability is achieved using current mirrors madeby transistors, and , and and . The large tran-sient-output current of is redirected to the output of am-plifier and is now able to charge the large gate capacitance of

. To further enhance this sink and source output-drivingability, the size of transistors, and , is set to three timesof the size of transistors, and , respectively. Ratios ofdifferent transistors shown in Fig. 3 are summarized in Table I.

Moreover, the push–pull output stage constructed with tran-sistors and enables the proposed amplifier with largeoutput-voltage swing, which facilitates an LDO regulator usingonly moderate size to provide a wide range of load cur-rents under small . The amplifier-output voltage is able to gofrom nearly zero to almost of the regulator when comparedwith the amplifiers using telescopic output stage. In other words,

can operate in cut-off region for small load current, oroperate in saturation region or even linear region to handle heavyload current. Hence, very-large size used to compensatethe limited amplifier-output swing is no longer required in theproposed LDO regulator. The use of moderate size alsoreduces its gate capacitance, and with the proposed slew-rate en-hanced amplifier, the transient responses of an LDO regulator isfurther improved.

Since most of voltage reference circuits do not haveoutput-current-driving ability, a reference buffer is introducedhere to transfer the supply- and temperature-independent refer-ence voltage to both the inverting input of and thenon-inverting input of . As shown in Fig. 3, the referencebuffer is a two-stage amplifier in unity-gain feedback. Since

will not be changed quickly with time, high slew-rateis not required in the design of reference buffer. Therefore, aconventional common-source differential-input amplifier withsmall tail-current is chosen as the first gain stage, which isconstructed with transistors, , , and , and

acted as a tail-current. Transistors, , , and, make up the second gain stage.

Moreover, it is important to note that the output of refer-ence buffer is connected to a low-resistance node, which is thesource terminal of transistor inside . The pole at theoutput of reference buffer is therefore pushed to high frequencyregime, where is much far away from the low-frequency poleat the output of first gain stage. Frequency compensation ishence not required in the reference buffer when compared witha stand-alone two-stage amplifier in unity-gain feedback.

IV. EXPERIMENTAL RESULTS

The proposed LDO regulator has been implemented inTSMC 0.18- m CMOS process. The chip micrograph is shownin Fig. 4. Since the proposed regulator does not require anyarea-consuming on-chip compensation capacitors, the LDOregulator, including all the pads, only occupies 0.09 mm only.

The total quiescent current of the proposed LDO regulatoris 1.2 A only. Even when the input voltage is changed from1.8 V (the maximum voltage allowed in the 0.18- m standardCMOS process) down to 1 V, the regulator is still able to providea 50-mA load current and 0.9-V output voltage .

758 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 9, SEPTEMBER 2007

Fig. 4. Chip micrograph of the proposed LDO regulator.

Fig. 5. Measured line regulation under 50 �A and 50-mA load current.

Fig. 5 shows the measured line regulation with different load-current levels (e.g., 50 A and 50 mA). The line regulation ismeasured to be 4.75 mV/V at 50- A and 3.625 mV/Vat 50 mA . The load regulation at 1.0 V is measuredto be 148 mA. From the measurement results, satisfactoryline and load regulation are successfully achieved using only1.2 A .

In Fig. 5, it is found that the is decreasing but notincreasing with an increasing . With extensive simulationsand detailed analyses, the origin of this interesting phenomenonis found to be caused by the process-variation induced drain-re-sistance mismatch between and . Since the channellengths of and are in deep sub-micron regime,channel length modulation (CLM) and short-channel effectsuch as drain-induced barrier lowering (DIBL) [9] make thedrain resistance of these transistors to be very sensitive to theabsolute value of channel length. Even though these transistorsare matched in the layout using common-centroid method,any process variation induced channel-length mismatch stillinevitably introduces mismatch between the drain resistance oftransistors and .

Fig. 6 shows the simulated line regulation with different levelsof channel-length mismatch between and . When thechannel length of ( ) is smaller than that of ( ),the drain resistance of becomes smaller than that of .Once is increased, the drain current of becomes largerthan that of . To match the drain currents of transistorand , is forced to be decreased by the negative-feed-back action of the amplifier. The negative slope of the measuredline regulation (Fig. 5) is resulted from the channel-length mis-match between and (e.g., ).

Fig. 6. Simulated line regulation with different levels of channel length mis-match between transistors M and M .

Fig. 7. Measured load-transient responses of the proposed LDO regulatorwithout an off-chip output capacitor.

Load and line transient responses are measured to evaluatethe transient performance of LDO regulator with the proposedamplifier. Fig. 7 shows the measured load-transient responseswithout an off-chip output capacitor. The varies from50 A to 50 mA, and is 1.2 V. Measurement result showsthat the proposed LDO regulator responds within ns andis fully recovered within s at 1.2 A .

Fig. 8 shows the measured load-transient responses with a100 pF off-chip output capacitor. It is used to model the reg-ulator-output-parasitic capacitance from the metal lines usedto implement chip-level power distribution. The againvaries from 50 A to 50 mA at 1.2 V . Measurement re-sult shows the proposed LDO regulator is fully recovered within3 s at 1.2 A .

The measured line-transient responses without an off-chipoutput capacitor and with a 100 pF off-chip output capacitor areshown in Figs. 8 and 9, respectively. The varies from 1.2 to1.7 V and the load current is 50 mA. Measurement results showthat the output voltage of the LDO regulator can be recoveredwithin s.

The measurement results shown in Figs. 7–10 confirm thatstability of LDO regulator with the proposed amplifier is suc-cessfully achieved without using any on-chip and off-chip com-pensation capacitors. Even a parasitic capacitor with severalhundreds of pF existed at the regulator output, stability is alsoguaranteed.

MAN et al.: HIGH SLEW-RATE PUSH–PULL OUTPUT AMPLIFIER 759

Fig. 8. Measured load-transient responses of the proposed LDO regulator witha 100 pF off-chip output capacitor.

Fig. 9. Measured line-transient responses of the proposed LDO regulatorwithout an off-chip output capacitor.

Fig. 10. Measured line-transient responses of the proposed LDO regulator witha 100 pF off-chip output capacitor.

Table II provides comparison between performance of theproposed LDO regulator and other published designs that aretargeted for chip-level power management. A figure of merit( ) used in [7] is adopted here toevaluate the effect of to the load transient response time ( )in different designs. A lower FOM implies a better slewing per-formance. The proposed regulator has very comparable FOM(0.067 ns) to the design in [7]. However, the proposed regulatoronly requires 1.2 A compared with 6 mA in [7]. It makes theproposed regulator with superior current efficiency at light-loadcondition. This feature is very important and attractive to anybattery-powered mobile systems.

TABLE IIPERFORMANCE COMPARISON

V. CONCLUSION

A high slew-rate amplifier with push–pull output stage is in-troduced to improve transient responses of an LDO regulatorwhich uses ultra-low to improve light-load efficiency andlarge-size pass transistor to reduce dropout loss. The proposedamplifier is able to provide a push–pull transient-output current,which is much larger than its quiescent current. Time requiredto charge or discharge the large pass transistor gate capacitanceis greatly reduced. Both load and line transient responses of anLDO regulator are thus improved.

Experimental results show that the proposed LDO regulatorwith only 1.2 A is able to recover within s underthe worst case scenario. It also proves that the proposed uniquestructure enables a stable LDO regulator without using anyon-chip and off-chip compensation capacitors. Chip-area effi-ciency is thus greatly improved and multiple proposed LDOregulators can be applied in chip-level power management.

ACKNOWLEDGMENT

The authors would like to thank A. Ng’s technical support.

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