04/26/05 Anthony Singh, Carleton University, 2005 1 MCML - Fixed Point - Integer Divider...
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04/26/05 Anthony Singh, Carleton University, 2005 1 MCML - Fixed Point - MCML - Fixed Point - Integer Divider Integer Divider Presentation #2 High-Speed Low Power VLSI – Prof. Shams By Anthony Singh
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Transcript of 04/26/05 Anthony Singh, Carleton University, 2005 1 MCML - Fixed Point - Integer Divider...
04/26/05 Anthony Singh, Carleton University, 2005
1
MCML - Fixed Point - Integer DividerMCML - Fixed Point - Integer Divider
Presentation #2
High-Speed Low Power VLSI – Prof. Shams
By Anthony Singh
04/26/05 Anthony Singh, Carleton University, 2005
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AgendaAgenda
Project Goal Discussion of Divider circuit design Discussion on Divider circuits simulation
results Conclusions
04/26/05 Anthony Singh, Carleton University, 2005
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Project GoalsProject Goals
Build a Fixed Point Integer Divider, using MCML circuits
Compare Energy saving of a standard MCML to Clock Delayed MCML (Dynamic MCML)
04/26/05 Anthony Singh, Carleton University, 2005
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Discussion of Divider Circuit DesignDiscussion of Divider Circuit Design
Built all analog circuits (gates): XOR2, Full Adder, D-latch, etc... using MCML logic style
Used a State Machine to control all blocks to sequence the division process.
Coded the State Machine using Verilog Combined the analog circuits and Verilog state
machine into a Mixed signal system design, to simulate the entire design operation
04/26/05 Anthony Singh, Carleton University, 2005
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Radix-2 SRT Divider CircuitRadix-2 SRT Divider Circuit
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System simplifications made during the System simplifications made during the design processdesign process
Power Supply voltage, VDD = 1.2V.
Single ended ΔV=400mV output swing, 0.8mV to 1.2mV.
Fixed Current Source, Ibias, of 10uA was used for all gates.
04/26/05 Anthony Singh, Carleton University, 2005
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Circuit simplifications made during Circuit simplifications made during designdesign
transistor sizes were determined by using the transistor sizing ratios from Jason Musicer's Thesis[7] and scaling them accordingly for CMOS 0.18um.
While keeping the transistors sizes for multi-level transistors stacks such as the 3-input XOR, was not optimal, I found from the simulations that this simplification did not effect the speed or shape of the output waveform from the gate too much.
the reference voltages for the NMOS current source transistor and PMOS load transistor were determined by sweeping the Gate to Source voltage with the requirements MCML gate specifications from above.
While I could have achieved greater speed from the MCML gates by increasing the Ibias current or reducing the output voltage swing, I decided to keep the Ibias current the same across all gates to simplify the over design. Also, 400mVpp is an industry standard for MCML gates.
GateMCML gate 0.36/0.18 1.44/0.36 0.36/0.288
(W/L)NMOS (W/L)Current Source(W/L)Load
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More resultsMore results
Total power consumption from VDD was measured to be 1.17mA rms. Independent of clock frequency (as expected).
GateInverter 112XOR2 205MUX2 100D-latch 224D-flip-flop 224Sum Gate (XOR3)300Carry Gate 255Shift Register (one DFF to another DFF)10216-bit Ripple Carry Adder2350
Tp (ps)
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Output WaveformsOutput Waveforms
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More Output waveformsMore Output waveforms
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ConclusionsConclusions Standard MCML is not a good choice for building a
Divider circuit, since blocks which are not actively processing data, consume power regardless. A Divider circuit spends most of its time in an iterative loop, while many components wait for data to pass through the Adder/Subtracter
Speed of Adder/Subtracter is vital to speed of the Divider circuit.
A Divider is a good circuit to be implemented using Asynchronous design techniques. Inherently an Ack/Nack type of process.
Idea: use the Req/Ack signals as clock signals to into the MCML gate for switching the current source on/off
04/26/05 Anthony Singh, Carleton University, 2005
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ReferencesReferences
[1] David A. Patterson and John L. Hennessy, “Computer Organization & Design – The Hardware/Software Interface”, Morgan Kaufmann Publishers, San Mateo, CA, 1993
[2] V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky, “Computer Organization – 3 rd Edition”, McGraw-Hill, 1990
[3] Joseph J. F. Cavanagh, “Digital Computer Arithmetic – Design and Implementation”, McGraw-Hill, 1984
[4] C. C. Wang, C.J. Huang, and G. C. Lin, “Cell-based implementation of radix-4/2 64b dividend 32b divisor signed integer divider using the COMPASS cell library”, IEE Proc. Comput. Digit. Tech, Vol.147, No.2, pp.109-115, March 2000
[5] M. W. Allam and Mohamed I. Elmasry, “Dynamic current mode logic (DyCML): a new low-power high-performance logic style”, Solid-State Circuits, IEEE Journal of ,Volume: 36 , Issue: 3, Pages:550 – 558, March 2001
[6] Mohab H. Anis and Mohamed I. Elmasry, “Self-Timed MOS Current Mode Logic for Digital Applications”, IEEE, V-113-116, 2002
[7] Jason Musicer, “An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic”, Thesis, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
