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Challenges for Sub-10 nm CMOS Devices

Tohru Mogami *

Selete, Inc., Tsukuba, Ibaraki 305-8569, Japan

* E-mail: mogami.toru@selete.co.jp

Abstract

Sub-10nm CMOS devices are the critical

issue, because CMOS scaling is going to be

sub-25nm regime. Scaling issues of nano-size

MOSFETs can be discussed on the basis of

sub-10 nm MOSFETs characteristics, which

have been developed and confirmed switching

characteristics and low-temperature character-

istics. Studying device limitationissues and

developing new breakthrough technologies are

required to challenge sub-10-nm CMOSdevices.

1. Introduction

Si-LSIs have been leading in micro-

electronics devices since 1970s. Device

scaling in Silicon MOSFETs has been

producing advantages of performance

improvement in Si-LSIs. However, several

limitation factors are emerging in sub-50 nm

CMOS devices, because of quantum effects,

intrinsic material characteristics, and so on. To

overcome these limitations, studying

ultra-small device characteristics and issues is

very important for scaling MOSFETs. In this

paper, device limitation factors and new

breakthrough technologies will be discussed.

2.Scaling challenges for sub-10nm CMOS

Sub-10 nm gate length MOSFETs have

been developing with a variety of structures.

One of the smallest devices is 5 nm MOSFETusing a bulk silicon substrate1). For that device

process, the notched poly-Si gate shown in

Fig.1 and the channel design with shallow

SDE/halo structure were used. Good switching

character- istics for n-/p-FETs are observed

shown in Fig.2, while DIBL effects become

increase with gate length reduction. For the

subthreshold characteristics of 6 nm gate length

at 2.7 Kelvin, negative-differential trans-

conductance is observed only for low

temperature and low drain voltage, shown in

Fig.3. Peak to valley current ratio is 1.74, and it

decreases with the increase in temperature.

This might be caused the Coulomb blockade by

double-barrier in channel region.

Direct tunneling current between source

and drain can be one of the device operation

limits. Fig.4 shows the subthreshold slope

dependence on temperature for various gatelengths. At higher temperature, subthreshold

slope is proportional to temperature. This

means that the thermal current is dominant

around 300 Kelvin until 6 nm gate MOSFET.

On the other hand, below 30 Kelvin,

subthreshold slope is almost constant. This is

because the S/D direct tunneling current is

dominant below 30 Kelvin even for 17 nm gate

MOSFET. Furthermore, it has been reported

that S/D-direct tunneling currents depend on

gate length, gate voltage, temperature and drain

voltage. Fig.5 shows the subthreshold slope

dependence on drain voltage for n-/p-FETs at

30 Kelvin, in which the tunneling current

should be dominant. Drain voltage lowering

reduces the subthreshold slope. This result

indicates that the control method of the direct

tunneling may be the drain voltage reduction

with gate length shrinkage.

In order to clarify the S/D direct tunneling

current behavior in the drain current at 300 K,the transport simulation was carried out.2)

Figure 6 shows the simulated subthreshold

characteristics of both drain currents and

tunneling currents at various temperatures in

0.8 V drain voltage for the nMOSFETs with

6-nm gate lengths. It is obtained that the

temperature enhances not only the thermal

current but also the S/D direct-tunneling

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currents. This can be due to the

direct-tunneling currents of higher-energy

electrons through a thinner potential barrier.

Figure 7 shows the calculated results at various

drain voltages for 6 nm gate length at 300 K.

This shows that the ratio values of tunnelingcurrent decrease with the decrease in the drain

voltage. Therefore, it is shown that the S/D

direct-tunneling currents strongly depend on

not only the gate length but also the

temperature, drain- and gate-voltages. In order

to suppress the tunneling behavior, it is

important to reduce the supply voltage even

under the room temperature.

3.Summary

Transport properties of sub-10-nm planar

bulk MOS-FETs were discussed. It was found

that direct-tunneling currents between source

and drain (S/D) regions depend on not only the

gate-length, but also drain voltage for sub-10

nm CMOS devices at low temperature. A

quantum mechanical simulation shows that the

tunneling currents increase with the increase in

the temperatures and gate voltages, resulting in

the significant contribution to the subthreshold

current even at 300 K. Therefore, it is strongly

required that the supply-voltage should be

reduced to suppress the drain-induced

tunneling modulation effects for the sub-10 nm

CMOS devices even under the room-

temperature operations.

References

[1] H. Wakabayashi et al., IEDM Tech. Digest,

p.989, 2003.

[2] H. Wakabayashi et al., IEDM Tech. Digest,p.429, 2004.

Fig.1 Cross sectional SEM of 5 nm gate MOSFET

20 nm

Gate

SiN SW

SiO2liner

Si-sub.20 nm

Gate

SiN SW

SiO2liner

Si-sub.

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100

101

102

20

40

6080

100

200

400

600800

Temperature T [K]

Subthresholdslope[mV/de

c.] Vds= 0.8 V

17 nm

11 nm

Lg= 6 nm

nMOS

ST:

therm

al

curre

nt

3

0K

300K

0.0 0.5 1.020

40

6080

100

200

400

600800

Drain voltage |Vds| [V]

Subthresholdslope[mV/de

c.]

T = 30K

17 nm

11 nm

Lg = 6 nm

nMOS

pMOS, Lg = 8 nm

0.0 0.5 1.020

40

6080

100

200

400

600800

Drain voltage |Vds| [V]Drain voltage |Vds| [V]

Subthresholdslope[mV/de

c.]

T = 30K

17 nm

11 nm

Lg = 6 nm

nMOS

pMOS, Lg = 8 nm

1.5 1.0 0.5 0.0 0.5 1.0 1.510

9

108

107

106

105

104

103

Gate voltage V g[V]

DraincurrentId[A

/m]

light haloLg= 5 nm

|Vd| = 0.05, 0.10,..., 0.40 V

0.0 0.1 0.20

100

200

300

400

500

Gate voltage Vgs[V]

SourcecurrentIs[p

A/m]

Lg= 6 nm

Vds= 0.1 V

2.7 K5.0 K

10K3

0K5

0K

PVCR@ 2.7 K= 1.74

100 K w/o NDT

50

K

30

K

10K

5.0 K

Fig.2 Id-Vg characteristics for 5 nm n-/p-FETs Fig.3 Negative differential Is-Vg characteristics

Fig.5 Subthreshold slope vs. Drain voltageFig.4 Subthreshold slope vs. Temperature

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1.0 0.5 0.0 0.5 1.010

12

1011

1010

109

108

107

106

105

104

Gate voltage Vgs[V]

DraincurrentId[A/m] Lg= 6 nm

Vds= 0.8 V

300

K

100K 3

0

K

50K

Dash: tunnel

Solid: drain current

1.0 0.5 0.0 0.5 1.00.0

0.1

0.2

0.3

0.4

0.5

Gate voltage Vgs[V]

Idtunnel /Id

Lg= 6 nmVds= 0.8 V

0.4 V

0.1 V

T = 300 K

Fig.6 Simulated tunneling drain current vs.

gate voltage.Fig.7 Simulated tunneling drain current vs.

gate voltage.